On Aug 14, 2020, Nathan Sidwell wrote:
> 'exalias' sounds either like a used-to-be alias
*nod*
> or it sounds like exa-lias, making me wonder what a 'lia' is, and why
> I want 10^18 of them
heh
>>> I'm sure we can bikeshed the name 'exalias' doesn't seem very mnemonic
>>> to me.
Hi!
On Fri, Aug 14, 2020 at 03:32:47PM -0700, Carl Love wrote:
> On Fri, 2020-08-14 at 16:33 -0500, Segher Boessenkool wrote:
> > So _vsx if it is for all VSRs, but _altivec for just the VRs?
>
> Yes, I worked off the rule that Altivec registers are designated with
> 5-bits and VSR registers are
We no longer need to give name_lookup_real not name_lookup_nonclass
different names to the name_lookup functions. This renames the lookup
functions thusly.
gcc/cp/
* name-lookup.h (lookup_name_real, lookup_name_nonclass): Rename
to ...
(lookup_name): ... these
Hi!
On Fri, Aug 14, 2020 at 03:20:03PM +0800, HAO CHEN GUI wrote:
> section *
> select_jump_table_section (tree decl)
> {
> int reloc;
> bool section_reloc;
>
> reloc = (! CASE_VECTOR_PC_RELATIVE && flag_pic &&
> ! targetm.asm_out.generate_pic_addr_diff_vec ()) ? 1 :
> 0;
On 8/13/20 11:44 AM, Martin Sebor wrote:
On 8/13/20 10:21 AM, Jeff Law wrote:
On Fri, 2020-07-31 at 17:55 -0600, Martin Sebor via Gcc-patches wrote:
The folders for these functions (and some others) call c_getsr
which relies on string_constant to return the representation of
constant strings.
This patch adds a few new instructions to inline expansion of
memcpy/memmove. Generation of all these is controlled by
the option -mblock-ops-unaligned-vsx which is set on by default if the
target has TARGET_EFFICIENT_UNALIGNED_VSX.
* unaligned vsx load/store (V2DImode)
* unaligned vsx pair
Hi All,
I sent an initial RFC of this patch[1] some time ago. I believe it is
now in a complete state, with added the test cases for the builtins.
The builtin optimizations presented here were originally in glibc, but
were removed and suggested that they were a good fit as gcc
builtins[2].
So,
PR testsuite/96609 and PR analyzer/96616 report various testsuite
failures seen on powerpc64, aarch64, and arm in new tests added by
r11-2694-g808f4dfeb3a95f50f15e71148e5c1067f90a126d.
Some of these failures (in gcc.dg/analyzer/init.c, and on arm
in gcc.dg/analyzer/casts-1.c) relate to
On Fri, 2020-08-14 at 16:33 -0500, Segher Boessenkool wrote:
> Hi Carl,
>
> On Thu, Aug 13, 2020 at 09:12:48AM -0700, Carl Love wrote:
> > The macro expansion for the bfloat convert intrinsics XVCVBF16SP
> > and
> > XVCVSPBF16 need to be restricted to P10.
> > The following patch creates new
On 8/14/20 3:24 PM, Alexandre Oliva wrote:
On Aug 14, 2020, Nathan Sidwell wrote:
This seems a useful feature. I don;t think it needs language
lawyering -- it's an extension, right?
Well, yeah, but I think it's usually good for even extensions to be
sound language-wise.
By
Hi!
On Fri, Aug 14, 2020 at 01:42:24PM +0800, Kewen.Lin wrote:
> > I think personally I'd prefer an option (3): call
> > target_option_override_hook directly in decode_options,
> > if help_option_arguments is nonempty. Like you say,
> > decode_options appears to be the only caller of print_help.
Hi Carl,
On Thu, Aug 13, 2020 at 09:12:48AM -0700, Carl Love wrote:
> The macro expansion for the bfloat convert intrinsics XVCVBF16SP and
> XVCVSPBF16 need to be restricted to P10.
> The following patch creates new macro expansions BU_P10V_VSX_# and
> BU_P10V_AV_# for the VSX and Altivec
PR analyzer/96611 reports an ICE within the handling for unknown
functions, when passing a pointer to something accessed via a
global pointer, after an unknown function has already been called.
The first unknown function leads to the store being flagged, so
the access to the global pointer leads
gcc/ChangeLog:
* doc/analyzer.texi (Overview): Add tip about how to get a
gimple dump if the analyzer ICEs.
---
gcc/doc/analyzer.texi | 5 +
1 file changed, 5 insertions(+)
diff --git a/gcc/doc/analyzer.texi b/gcc/doc/analyzer.texi
index b5d6d0f393e..92c12e19401 100644
---
On Fri, 2020-08-14 at 10:49 +0200, Christophe Lyon wrote:
> Hi David,
>
>
> On Thu, 13 Aug 2020 at 22:58, David Malcolm via Gcc-patches
> wrote:
> > This large patch reimplements how the analyzer tracks regions and
> > values.
[...]
> > Pushed to master as
On Aug 14, 2020, Nathan Sidwell wrote:
> This seems a useful feature. I don;t think it needs language
> lawyering -- it's an extension, right?
Well, yeah, but I think it's usually good for even extensions to be
sound language-wise.
> By 'same-linkage', do you mean same linkage as the *symbol*
On Tue, 2020-08-11 at 12:23 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 5 adds the 128-bit integer to/from 128-floating point
> conversions. This patch has to invoke the routines to use the 128-bit
> hardware instructions if on Power 10 or use software routines if
> running on a pre Power
This patch deals with LOOKUP_HIDDEN, which originally meant 'find hidden
friends', but it's being pressed into service for not ignoring
lambda-relevant internals. However these two functions are different.
(a) hidden friends can occur in block scope (very uncommon) and (b) it
had the semantics
On Tue, 2020-08-11 at 12:23 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 4 adds 128-bit integer shift instruction support.
I suggest having a few more words here to better describe what this
patch is doing.
i.e.
This is adding the VEC_I128 iterator which contains the V1TI and TI
types,
On 8/14/20 12:05 PM, Aldy Hernandez wrote:
I made some minor changes to the function comments.
gcc/ChangeLog:
* vr-values.c (check_for_binary_op_overflow): Change type of store
to range_query.
(vr_values::adjust_range_with_scev): Abstract most of the code...
On Tue, 2020-08-11 at 12:22 -0700, Carl Love wrote:
> Segher, Will:
>
> Path 3 adds support for converting to/from 128-bit integers and 128-bit
> decimal floating point formats.
>
> Carl Love
>
Some cosmetic comments below. overall lgtm.
Thanks,
-Will
>
>
We don't elide a copy from a function returning a class by value into a base
because that can overwrite data laid out in the tail padding of the base
class; we need to handle [[no_unique_address]] fields the same way, or we
ICE when the middle-end wants to create a temporary object of a
On 8/14/20 11:39 AM, Alexandre Oliva wrote:
Ping?
In case there isn't immediate approval for the patch proper (I suppose
different parts will require review by different subsystem maintainers),
I'd appreciate at least community and language lawyers buy-in (or
turn-down) for the new feature
I made some minor changes to the function comments.
gcc/ChangeLog:
* vr-values.c (check_for_binary_op_overflow): Change type of store
to range_query.
(vr_values::adjust_range_with_scev): Abstract most of the code...
(range_of_var_in_loop): ...here. Remove
On 8/11/20 7:53 AM, Aldy Hernandez via Gcc-patches wrote:
-- Forwarded message -
From: Aldy Hernandez
Date: Tue, Aug 4, 2020, 13:55
Subject: [PATCH 1/2] Add statement context to get_value_range.
To:
Cc: , Aldy Hernandez
This is in line with the statement context that we have
Ping?
In case there isn't immediate approval for the patch proper (I suppose
different parts will require review by different subsystem maintainers),
I'd appreciate at least community and language lawyers buy-in (or
turn-down) for the new feature hereby proposed for C-family languages,
namely,
Attached is a patch adding a -Wlong-distance-friends flag to diagnose long
distance (cross module) friendship.
2020-08-14 Jeff Chapman II
gcc/c-family/
* c.opt (Wlong-distance-friends): New.
gcc/cp/
* cp-tree.h (module_friendship_compatible): New.
* friend.c
Hello again,
This is part one of a patchset to add an optional warning for long distance
(cross module) friendship when the friendship has no useful/sensical meaning.
Attached is a patch to error when trying to define a member function of a type
owned by a different module. This also fixes an
Hello!
Attached is a patch that fixes an ICE on the devel/c++-modules branch caused
by a slot invalidation edge case in push_namespace.
It's been sitting around for a while and I wasn't sure if I should use the
original date or not. Feel free to adjust that to the commit date if that's
what it
Continuing fixing name lookup's API we have two parameters saying what
we'd like to find 'prefer_type', which is a tri-valued boolan with
meaning 'don't care', 'type or namespace', 'type or death'. And we have
a second parameter 'namespaces_only', which means 'namespace or death'.
There are
Use parameterized pattern names to simplify calling of named patterns.
2020-08-14 Uroš Bizjak
gcc/ChangeLog:
* config/i386/i386-builtin.def (__builtin_ia32_llwpcb)
(__builtin_ia32_slwpcb, __builtin_ia32_lwpval32)
(__builtin_ia32_lwpval64, __builtin_ia32_lwpins32)
On Fri, 2020-08-14 at 10:01 -0400, Lewis Hyatt wrote:
> On Wed, Aug 12, 2020 at 12:54 PM Richard Sandiford
> wrote:
[...]
> > OK with those changes in 24 hrs if noone objects or asks for a
> > delay.
> >
> > Thanks,
> > Richard
>
> Thanks for the review, and sorry about the formatting
On Wed, Aug 12, 2020 at 12:54 PM Richard Sandiford
wrote:
>
> Lewis Hyatt writes:
> > Hello-
> >
> > Attached is the patch I mentioned in another discussion here:
> > https://gcc.gnu.org/pipermail/gcc-patches/2020-August/551442.html
> >
> > This adds a new option -fdiagnostics-plain-output that
Hi,
Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm
consisting of two components: a set of 2-dimensional registers (tiles)
representing sub-arrays from a larger 2-dimensional memory image, and
accelerators able to operate on tiles. Capability of Intel AMX
On Fri, 2020-08-14 at 09:26 +0200, Martin Liška wrote:
> On 8/14/20 9:22 AM, Martin Liška wrote:
> > On 8/13/20 10:58 PM, David Malcolm via Gcc-patches wrote:
> > > PR analyzer/93032 (missing leak diagnostic for
> > > zlib/contrib/minizip/mztools.c)
> > > PR analyzer/93938 (ICE in analyzer)
> > >
On Fri, 2020-08-14 at 09:22 +0200, Martin Liška wrote:
> On 8/13/20 10:58 PM, David Malcolm via Gcc-patches wrote:
> > PR analyzer/93032 (missing leak diagnostic for
> > zlib/contrib/minizip/mztools.c)
> > PR analyzer/93938 (ICE in analyzer)
> > PR analyzer/94011 (ICE in analyzer)
> > PR
Hello
I have backported Tobias' patches for PR94690 from master to devel/omp/gcc-10.
These are:
[Fortran] OpenMP - permit lastprivate in distribute + SIMD fixes (PR94690)
(commit f884bef2105d748fd7869cd641cbb4f6b6bb)
[Fortran] OpenMP 5 – permit more sharing clauses for SIMD (PR94690)
On Fri, Aug 14, 2020 at 6:54 AM Hongtao Liu wrote:
>
> On Tue, Aug 11, 2020 at 5:56 PM Uros Bizjak wrote:
> >
> > On Tue, Aug 11, 2020 at 11:36 AM Hongtao Liu wrote:
> > >
> > > On Tue, Aug 11, 2020 at 4:38 PM Uros Bizjak wrote:
> > > >
> > > > On Tue, Aug 11, 2020 at 5:30 AM Hongtao Liu
On Fri, Aug 14, 2020 at 8:03 AM Hongtao Liu wrote:
>
> Hi:
> For struct initialization, when it fits in a TImode, gcc will use
> pinsr insn which causes poor codegen described in PR93897 and PR96562.
You should probably remove TImode handling also from ix86_expand_pextr.
Uros.
> Bootstrap
Ping.
Though I will hold back on supporting 'in ref' until it has been formalized.
Current discussions are around what value might it have over 'ref const scope'
(so far, none).
Iain.
On 07/08/2020 13:32, Iain Buclaw wrote:
> Hi,
>
> This patch adds support for 'in' as a first-class storage
Ping.
Though I wonder if there's any point adding a check at all over just swapping
the order that mem_loc_descriptor and tls_mem_loc_descriptor are called in.
Iain.
On 07/08/2020 13:33, Iain Buclaw wrote:
> Hi,
>
> On x86, a memory reference reference to a TLS address can be broken out
> and
On Fri, 14 Aug 2020 at 11:21, Jan Hubicka wrote:
>
> > Hi,
> > >
> > > Since this was backported as
> > > r10-8623-g0d96c3424bbb5e5f994b78c8f65d8704d215be54,
> >
> > Yes, after discussion with Jakub on IRC.
> > > I've noticed ICEs on arm and aarch64:
> > > gcc.dg/pr34457-1.c (internal
Hi,
Ok & thanks.
Jojo
在 2020年8月14日 +0800 PM3:02，Xianmiao Qu ，写道：
> Hi Jojo,
>
> > gcc/ChangeLog:
> > * gcc/config/csky/csky-elf.h (ASM_SPEC): Use mfloat-abi.
> > * gcc/config/csky/csky-linux-elf.h (ASM_SPEC): mfloat-abi.
> >
> I have committed it to trunk. But there two points you shoud
> Hi,
> >
> > Since this was backported as
> > r10-8623-g0d96c3424bbb5e5f994b78c8f65d8704d215be54,
>
> Yes, after discussion with Jakub on IRC.
> > I've noticed ICEs on arm and aarch64:
> > gcc.dg/pr34457-1.c (internal compiler error)
> > gcc.dg/torture/pr92088-1.c -O2 -flto
Hi,
>
> Since this was backported as
> r10-8623-g0d96c3424bbb5e5f994b78c8f65d8704d215be54,
Yes, after discussion with Jakub on IRC.
> I've noticed ICEs on arm and aarch64:
> gcc.dg/pr34457-1.c (internal compiler error)
> gcc.dg/torture/pr92088-1.c -O2 -flto -fno-use-linker-plugin
>
Hi,
On 2020/8/13 20:52, Jan Hubicka wrote:
>> Since there are no other callers outside of these specialized nodes, the
>> guessed profile count should be same equal? Perf tool shows that even
>> each specialized node is called only once, none of them take same time for
>> each call:
>>
>>
Hi David,
On Thu, 13 Aug 2020 at 22:58, David Malcolm via Gcc-patches
wrote:
>
> This large patch reimplements how the analyzer tracks regions and
> values.
>
> Elimination of region_id and svalue_id
> **
>
> The patch eliminates region_id and svalue_id in
Hi,
On Thu, 6 Aug 2020 at 16:39, Richard Biener wrote:
>
> On Thu, 6 Aug 2020, Jan Hubicka wrote:
>
> > Hello,
> > as discussed some time ago, I would like to discuss possibility to
> > backport the straming and enum improvements. The motivation is that
> > this brings quite noticeable
Enable operator or/xor/and/andn/not for mask register, kxnor is not
enabled since there's no corresponding instruction for general
registers.
gcc/
PR target/88808
* config/i386/i386.md: (*movsi_internal): Adjust constraints
for mask registers.
(*movhi_internal):
1. Set cost of movement inside mask registers a bit higher than gpr's.
2. Set cost of movement between mask register and gpr much higher than movement
inside gpr, but still less equal than load/store.
3. Set cost of mask register load/store a bit higher than gpr load/store.
--
BR,
Hongtao
Enable direct move between masks and gprs in pass_reload with
consideration of cost model.
Changelog
gcc/
* config/i386/i386.c (inline_secondary_memory_needed):
No memory is needed between mask regs and gpr.
(ix86_hard_regno_mode_ok): Add condition TARGET_AVX512F for
Hi:
First, since avx512 masks involve both vector isa and general part,
so i add both maintainers to the maillist.
I'm doing this in 4 steps:
1 - Add cost model for operation of mask registers.
2 - Introduce new cover class INT_MASK_REGS, this will enable direct
move between gpr and mask
Hi,
This patch adds non-relative jump table support on Power Linux. It
implements ASM_OUTPUT_ADDR_VEC_ELT and adds four new expansions for
non-relative jump table in rs6000.md. It also defines a rs6000
option(mrelative-jumptables). If it's set to false, the non-relative
jump table is picked
On 8/14/20 9:22 AM, Martin Liška wrote:
On 8/13/20 10:58 PM, David Malcolm via Gcc-patches wrote:
PR analyzer/93032 (missing leak diagnostic for zlib/contrib/minizip/mztools.c)
PR analyzer/93938 (ICE in analyzer)
PR analyzer/94011 (ICE in analyzer)
PR analyzer/94099 (ICE in analyzer)
PR
On 8/13/20 10:58 PM, David Malcolm via Gcc-patches wrote:
PR analyzer/93032 (missing leak diagnostic for zlib/contrib/minizip/mztools.c)
PR analyzer/93938 (ICE in analyzer)
PR analyzer/94011 (ICE in analyzer)
PR analyzer/94099 (ICE in analyzer)
PR analyzer/94399 (leak false positive with
Hi,
This patch adds a section selection for jump tables. The jump tables can
be put into read-only data section or relocation read-only data section
by the relocation flags. When the PIC flag is set and jump table is
non-relative, the jump table is put into relocation read-only section.
Hi,
This patch adds a section selection for jump tables. The jump tables can
be put into read-only data section or relocation read-only data section
by the relocation flags. When the PIC flag is set and jump table is
non-relative, the jump table is put into relocation read-only section.
On August 14, 2020 8:58:55 AM GMT+02:00, Jakub Jelinek wrote:
>Hi!
>
>As mentioned earlier, embedded_size is broken on vecs of long long,
>double
>etc. on some platforms, which breaks bootstrap.
>E.g. on i686-linux, the problem is mostly with older GCC versions being
>used
>as stage1 compiler
Hi Jojo,
gcc/ChangeLog:
* gcc/config/csky/csky-elf.h (ASM_SPEC): Use mfloat-abi.
* gcc/config/csky/csky-linux-elf.h (ASM_SPEC): mfloat-abi.
I have committed it to trunk. But there two points you shoud pay
attention to,
1. line should start with a tab not spaces
2. The path of
Hi!
The following testcase shows various problems with -Wunused-but-set*
warnings and _Generic construct. I think it is best to treat the selector
and the ignored expressions as (potentially) read, because when they are
parsed, the vars in there are already marked as TREE_USED.
Hi!
As mentioned earlier, embedded_size is broken on vecs of long long, double
etc. on some platforms, which breaks bootstrap.
E.g. on i686-linux, the problem is mostly with older GCC versions being used
as stage1 compiler (GCC 4.8 to 7.* in particular), because alignas (long long)
makes U 64-bit
Hi:
For struct initialization, when it fits in a TImode, gcc will use
pinsr insn which causes poor codegen described in PR93897 and PR96562.
Bootstrap is ok, regression test is ok for i386/x86-64 backend.
Ok for trunk?
ChangeLog
gcc/
PR target/96562
PR target/93897
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