From: Juzhe-Zhong
Before this patch:
...
.L2:
addia4,a1,100
add t1,a0,a2
mv t0,a0
beq a2,zero,.L1
vsetvli zero,a3,e8,mf8,tu,mu
.L4:
addia6,t0,100
addia7,a4,-100
vle8.v v1,0(t0)
addit0,t0,1
> Am 05.05.2023 um 01:41 schrieb Andrew Pinski via Gcc-patches
> :
>
> There is already an `ABS == 0` to `a == 0` pattern,
> this just extends that to ABSU too.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
Ok
Richard
>PR tree-optimization/109722
>
>
I tried the memory profiling by valgrind --tool=memcheck --trace-children=yes
for this change, target the SPEC 2006 INT part with rv64gcv. Note we only count
the bytes allocated from valgrind log like this "==2832896== total heap
usage: 208 allocs, 165 frees, 123,204 bytes allocated".
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
In the testcase the assert fails because we use one member function from
another while we're in the middle of instantiating them all, which is
perfectly fine. It seems complicated to detect this situation, so let's
remove the assert again.
There is already an `ABS == 0` to `a == 0` pattern,
this just extends that to ABSU too.
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR tree-optimization/109722
gcc/ChangeLog:
* match.pd: Extend the `ABS == 0` pattern
to cover `ABSU == 0` too.
On 5/4/23 03:56, Tamar Christina wrote:
-Original Message-
From: Kyrylo Tkachov
Sent: Wednesday, May 3, 2023 4:19 PM
To: Tamar Christina ; Jeff Law
; gcc-patches@gcc.gnu.org
Cc: nd ; bonz...@gnu.org; nero...@gcc.gnu.org;
aol...@gcc.gnu.org; ralf.wildenh...@gmx.de
Subject: RE: [PATCH
So it turns out I messed checking which edge was true/false for the diamond
form. The edges, e0 and e1 here are edges from the merge block but the
true/false edges are from the conditional block and with diamond/threeway,
there is a bb inbetween on both edges.
Most of the time, the check that was
Ping.
On 4/18/23 7:22 AM, Pat Haugen via Gcc-patches wrote:
Updated from prior patch to also disable for int128.
Disable generation of scalar modulo instructions.
It was recently discovered that the scalar modulo instructions can suffer
noticeable performance issues for certain input values.
On 5/4/23 09:59, Richard Biener wrote:
I've previously sent
https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608077.html
adding ADDR_EXPR_NONZERO and there were comments from Jason
where I just realized I ignored ARRAY_REF for the following.
Anyway, here's a more aggressive variant not
On 4/28/23 08:54, Patrick Palka wrote:
On Thu, 27 Apr 2023, Patrick Palka wrote:
On Thu, Apr 27, 2023 at 4:46 PM Patrick Palka wrote:
Now that with r14-11-g2245459c85a3f4 made us coerce the template
arguments of a bound ttp again after level-lowering, this unfortunately
causes a crash from
I'd like to pull in Dan's upstream libffi commit into trunk to fix a
wrong code bug/testsuite failure on powerpc64le-linux with long double
defaulting to ieee128. This passed bootstrap and regtesting with no
regressions. Ok for trunk?
This bug is also on the GCC 12 and GCC 11 release branches.
The predicates of ashift to lea post-reload splitter were too broad
so the splitter tried to convert the mask shift instruction. Tighten
operand predicates to match only general registers.
gcc/ChangeLog:
PR target/109733
* config/i386/predicates.md (index_reg_operand): New predicate.
On 5/4/23 12:33, Patrick Palka wrote:
* Harden some tree accessor macros and fix some incorrect uses of
PLACEHOLDER_TYPE_CONSTRAINTS.
* Use strip_innermost_template_args in outer_template_args.
* Add !processing_template_decl early exit tests to some dependence
predicates.
OK.
On 5/4/23 12:33, Patrick Palka wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?
OK.
PR c++/85979
gcc/cp/ChangeLog:
* cxx-pretty-print.cc (cxx_pretty_printer::unary_expression)
: Consider ALIGNOF_EXPR_STD_P.
* error.cc
We were not able to match the CTZ sign extend pattern on RISC-V
because it get optimized to zero extend and/or to ANDI patterns.
For the ANDI case, combine scrambles the RTL and generates the
extension by using subregs.
gcc/ChangeLog:
PR target/106888
*
When (a & (1 << bit_no)) is tested inside an IF we can use a bit extract.
gcc/ChangeLog:
* config/riscv/bitmanip.md
(bext): Rename one to avoid name clash.
(branch_bext): New split pattern.
gcc/testsuite/ChangeLog:
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?
PR c++/85979
gcc/cp/ChangeLog:
* cxx-pretty-print.cc (cxx_pretty_printer::unary_expression)
: Consider ALIGNOF_EXPR_STD_P.
* error.cc (dump_expr) : Likewise.
gcc/testsuite/ChangeLog:
* Harden some tree accessor macros and fix some incorrect uses of
PLACEHOLDER_TYPE_CONSTRAINTS.
* Use strip_innermost_template_args in outer_template_args.
* Add !processing_template_decl early exit tests to some dependence
predicates.
gcc/cp/ChangeLog:
* cp-tree.h
On Fri, Apr 28, 2023 at 8:54 AM Patrick Palka wrote:
>
> On Thu, 27 Apr 2023, Patrick Palka wrote:
>
> > On Thu, Apr 27, 2023 at 4:46 PM Patrick Palka wrote:
> > >
> > > Now that with r14-11-g2245459c85a3f4 made us coerce the template
> > > arguments of a bound ttp again after level-lowering,
On 26.04.23 08:10, Sebastian Huber wrote:
---
htdocs/gcc-13/changes.html | 5 +
1 file changed, 5 insertions(+)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 4515a6af..bae65219 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -154,6
On 03/05/2023 12:55, Richard Biener wrote:
On Fri, 28 Apr 2023, Andre Vieira (lists) wrote:
Hi,
I'm posting the patches separately now with ChangeLogs.
I made the suggested changes and tried to simplify the code a bit further.
Where internal to tree-vect-stmts I changed most functions to
On May 4, 2023, Jonathan Wakely wrote:
> And we could use strtod for a target that doesn't support locales *at all*
> (so strtod always behaves as specified for LANG=C).
Oh, sorry, I misread the *_USELOCALE macro as *_USE_LOCALE, and I
thought this was what I was doing. Nevermind, patch
On Thu, 4 May 2023 at 13:06, Alexandre Oliva via Libstdc++ <
libstd...@gcc.gnu.org> wrote:
>
> When we're using fast_float for 32- and 64-bit floating point, use
> strtold for wider long double, even if locales are unavailable.
>
> On vxworks, test for strtof's and strtold's declarations, so that
Hi all,
Similar to the previous patch, this one converts the high-half versions of the
patterns.
With this patch we can remove the UNSPEC_* codes involved entirely.
Bootstrapped and tested on aarch64-none-linux-gnu. Also tested on
aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
Hi all,
We can implement the halving-narrowing add/sub patterns with standard RTL codes
as well rather than relying on unspecs.
This patch handles the low-part ones and the second patch does the high-part
ones and removes the unspecs themselves.
The operation ADDHN on V4SI, for example, is
I've previously sent
https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608077.html
adding ADDR_EXPR_NONZERO and there were comments from Jason
where I just realized I ignored ARRAY_REF for the following.
Anyway, here's a more aggressive variant not going for an extra
flag set by the
On 5/3/23 16:50, Patrick Palka wrote:
On Wed, 3 May 2023, Jason Merrill wrote:
On 5/2/23 15:53, Patrick Palka wrote:
on Tue, 2 May 2023, Patrick Palka wrote:
On Tue, 2 May 2023, Jason Merrill wrote:
On 5/1/23 15:59, Patrick Palka wrote:
Here we're incorrectly deeming the templated call
> On May 4, 2023, at 9:05 AM, Martin Liška wrote:
>
> On 5/4/23 14:54, Qing Zhao wrote:
>>
>>
>>> On May 4, 2023, at 4:30 AM, Martin Liška wrote:
>>>
>>> On 5/3/23 21:10, Qing Zhao via Gcc-patches wrote:
Hi, Jan,
You added the following patch into gcc10:
From
From: Ju-Zhe Zhong
This patch is fixing V3 patch:
https://patchwork.sourceware.org/project/gcc/patch/20230407014741.139387-1-juzhe.zh...@rivai.ai/
Fix issues according to Richard Sandiford && Richard Biener.
1. Rename WHILE_LEN pattern into SELECT_VL according to Richard Sandiford.
2. Support
On 04.05.23 13:02, Richard Biener wrote:
So since we expect the linker to use the host side table is there a way
for the plugin to exactly query that
Background - feel free to skip to the next quote / reply bit.
The following is what we have for the host side:
We have (→
On 5/4/23 14:54, Qing Zhao wrote:
>
>
>> On May 4, 2023, at 4:30 AM, Martin Liška wrote:
>>
>> On 5/3/23 21:10, Qing Zhao via Gcc-patches wrote:
>>> Hi, Jan,
>>>
>>> You added the following patch into gcc10:
>>>
>>> From 34fbe3f0946f88828765184ed6581bda62cdf49f Mon Sep 17 00:00:00 2001
>>>
> On May 4, 2023, at 4:30 AM, Martin Liška wrote:
>
> On 5/3/23 21:10, Qing Zhao via Gcc-patches wrote:
>> Hi, Jan,
>>
>> You added the following patch into gcc10:
>>
>> From 34fbe3f0946f88828765184ed6581bda62cdf49f Mon Sep 17 00:00:00 2001
>> From: Jan Hubicka
>> Date: Thu, 5 Dec 2019
On vxworks, isunordered is defined as a macro that ultimately calls a
_Fpcomp function, that GCC doesn't recognize as a builtin, so it
can't optimize accordingly.
Use __builtin_isunordered instead to get the desired code for the
test.
Regstrapped on x86_64-linux-gnu. Also tested on
When we're using fast_float for 32- and 64-bit floating point, use
strtold for wider long double, even if locales are unavailable.
On vxworks, test for strtof's and strtold's declarations, so that they
can be used even when cross compiling.
Include stdlib.h in the decl-checking macro, so that
Pushed to trunk and gcc-13.
-- >8 --
libstdc++-v3/ChangeLog:
* doc/xml/manual/abi.xml (abi.versioning.history): Document
libstdc++.so.6.0.32 and GLIBCXX_3.4.32 version.
* doc/html/manual/abi.html: Regenerate.
---
libstdc++-v3/doc/html/manual/abi.html | 6 +++---
On Mon, 24 Apr 2023 at 15:00, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > [aarch64] Recursively intialize even and odd sub-parts and merge with zip1.
> >
> > gcc/ChangeLog:
> > * config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback):
> > Rename
> >
Use the same approach as in register_no_elim_operand predicate, but also
reject stack_pointer_rtx operands.
gcc/ChangeLog:
* config/i386/predicates.md (index_register_operand): Reject
arg_pointer_rtx, frame_pointer_rtx, stack_pointer_rtx and
VIRTUAL_REGISTER_P operands. Allow
On Thu, 4 May 2023, Tobias Burnus wrote:
> Based on the the discussion with Richard B. on #gcc, some more details why the
> linker does
> (and might want) to call the plugin for files it does not need:
>
> For LTO with no-fat binaries, a symbol in a static library might still be
> needed but the
When fixing PR109672 I noticed we let SImode AND through when
target_support_p even though it isn't word_mode and I didn't want to
change that but had to catch the case where SImode PLUS is supported
but emulated vectors rely on it being word_mode. The following
makes sure to preserve the
Based on the the discussion with Richard B. on #gcc, some more details why the
linker does
(and might want) to call the plugin for files it does not need:
For LTO with no-fat binaries, a symbol in a static library might still be
needed but the linker
does not know as the file might only
On Thu, 4 May 2023, Martin Uecker wrote:
> Am Donnerstag, dem 04.05.2023 um 09:53 + schrieb Richard Biener:
> > On Thu, 4 May 2023, Martin Uecker wrote:
> >
> > >
> > > Can I please get permission for fixing this ICE?
> > >
> > >
Am Donnerstag, dem 04.05.2023 um 09:53 + schrieb Richard Biener:
> On Thu, 4 May 2023, Martin Uecker wrote:
>
> >
> > Can I please get permission for fixing this ICE?
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616221.html
>
> Please wait until after the branch is
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Wednesday, May 3, 2023 4:19 PM
> To: Tamar Christina ; Jeff Law
> ; gcc-patches@gcc.gnu.org
> Cc: nd ; bonz...@gnu.org; nero...@gcc.gnu.org;
> aol...@gcc.gnu.org; ralf.wildenh...@gmx.de
> Subject: RE: [PATCH 5/5] match.pd: Use splits in
On Thu, 4 May 2023, Martin Uecker wrote:
>
> Can I please get permission for fixing this ICE?
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616221.html
Please wait until after the branch is unfrozen. When patches were
approved for trunk and they are regressions there's no further
On Thu, May 4, 2023 at 7:37 AM Hongtao Liu via Gcc-patches
wrote:
>
> On Thu, May 4, 2023 at 1:35 PM Hongtao Liu wrote:
> >
> > On Thu, Dec 22, 2022 at 4:04 PM Uros Bizjak wrote:
> > >
> > > On Thu, Dec 22, 2022 at 5:40 AM Hongtao Liu wrote:
> > > >
> > > > On Thu, Dec 22, 2022 at 6:46 AM
On Thu, May 4, 2023 at 2:10 AM Hans-Peter Nilsson via Gcc-patches
wrote:
>
> Ping again.
OK.
> > From: Hans-Peter Nilsson
> > Date: Thu, 27 Apr 2023 01:55:24 +0200
> >
> > > From: Hans-Peter Nilsson
> > > Date: Wed, 19 Apr 2023 18:59:14 +0200
> > [...]
> >
> > > So again: Approvers: pdf
On Thu, May 4, 2023 at 1:13 AM Andrew Pinski via Gcc-patches
wrote:
>
> While looking at differences between what minmax_replacement
> and match_simplify_replacement does. I noticed that they sometimes
> chose different edges to remove. I decided we should be able to do
> better and be able to
On Thu, May 4, 2023 at 1:13 AM Andrew Pinski via Gcc-patches
wrote:
>
> While improving replace_phi_edge_with_variable for the diamond formed bb
> case, I need a way to copy phi entries from one edge to another as I am
> removing a forwarding bb inbetween. I was pointed out that jump threading
>
On Thu, May 4, 2023 at 1:11 AM Andrew Pinski via Gcc-patches
wrote:
>
> When I added the dce_ssa_names argument, I didn't realize bitmap was a
> pointer so I used the default argument value as auto_bitmap(). But
> instead we could just use nullptr and check if it was a nullptr
> before calling
From: Pan Li
This patch try to legitimise the const0_rtx (aka zero register)
as the base register for the RVV indexed load/store instructions
by allowing the const as the operand of the indexed RTL pattern.
Then the underlying combine pass will try to perform the const
propagation.
For example:
Could you rebase this patch, we have some changes on
> All "zcmpe" means Zcmp with RVE extension.
Use zcmp_rve instead, zcmpe seems like a new ext. name
> diff --git a/gcc/config/riscv/riscv-zcmp-popret.cc
> b/gcc/config/riscv/riscv-zcmp-popret.cc
> new file mode 100644
> index
Hi,
This patch adds a new insn for vector splat with small V2DI constants on P8.
If the value of constant is in RANGE (-16, 15) and not 0 or -1, it can be loaded
with vspltisw and vupkhsw on P8. It should be efficient than loading vector from
TOC.
Compared to last version, the main change is
Hi all,
More pattern annotations and tests to eliminate redundant vec-concat with zero
instructions.
These are for the abd family of instructions and the pairwise floating-point
max/min and fadd
operations too.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
Hi all,
We're now moving onto various simple ternary instructions, including some lane
forms.
These include intrinsics that map down to mla, mls, fma, aba, bsl instructions.
Tests are added for lane 0 and lane 1 as for some of these instructions the
lane 0 variants
use separate simpler patterns
Thanks Juzhe, make sense, let me update it soon.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 4, 2023 4:40 PM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Li, Pan2 ; Wang,
Yanzhang
Subject: Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed
load/store
vluxei32.v
vluxei32.v v1,(0),v1 is not correct assembly.
Instead, it should be vluxei32.v v1,(zero),v1
You should change the assembly print: (%1) --> (%z1)
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-04 16:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject:
Plz drop those testcase which just contain inline asm in foo, that
should belong to binutils's testsuite IMO.
On Thu, Apr 6, 2023 at 2:23 PM Jiawei wrote:
>
> From: Charlie Keaney
>
> Add all ZC* extensions march args tests.
>
> Co-Authored by: Nandni Jamnadas
> Co-Authored by: Jiawei
>
From: Pan Li
This patch try to legitimise the const0_rtx (aka zero register)
as the base register for the RVV indexed load/store instructions
by allowing the const as the operand of the indexed RTL pattern.
Then the underlying combine pass will try to perform the const
propagation.
For example:
> @@ -1151,14 +1169,26 @@ riscv_subset_list::parse (const char *arch,
> location_t loc)
>subset_list->handle_implied_ext (itr);
> }
>
> + /* Zce only imply zcf when 'f' extension exist. */
Grammarly and gmail told me it should be "Zce only implies zcf when
'f' extension exist." :P
Hello.
After discussion with the consumers of the format:
https://github.com/gcovr/gcovr/issues/282#issuecomment-1534239536
I'm going to push a patch that prints JSON version in gcov -v.
Thanks,
MartinFrom d879d68eb309561d266ddf734ab8c69f4fef3874 Mon Sep 17 00:00:00 2001
From: Martin Liska
On 5/3/23 21:10, Qing Zhao via Gcc-patches wrote:
> Hi, Jan,
>
> You added the following patch into gcc10:
>
> From 34fbe3f0946f88828765184ed6581bda62cdf49f Mon Sep 17 00:00:00 2001
> From: Jan Hubicka
> Date: Thu, 5 Dec 2019 19:12:51 +0100
> Subject: [PATCH] cgraphclones.c (localize_profile):
RISC-V Linux encodes the ABI into the path, so in theory, we can only use that
to select multi-lib paths, and no way to use different multi-lib paths between
`rv32i/ilp32` and `rv32ima/ilp32`, we'll mapping both to `/lib/ilp32`.
It's hard to do that with GCC's builtin multi-lib selection
On Thu, May 04, 2023 at 09:54:03AM +0200, Thomas Schwinge wrote:
> libgomp/
> * testsuite/libgomp.c++/c++.exp: Use 'lang_include_flags' instead
> of 'libstdcxx_includes'.
> * testsuite/libgomp.oacc-c++/c++.exp: Likewise.
Ok, thanks.
Jakub
Hi!
On 2021-05-26T14:06:53+0200, Jakub Jelinek via Gcc-patches
wrote:
> When gcc is configured for nvptx offloading [...]
> and full CUDA isn't installed, many libgomp.oacc-*/* tests fail,
> some of them because cuda.h header can't be found, others because
> the tests can't be linked against
The following adds a testcase for PR109724 which was caused by
backporting r13-2375-gbe1b42de9c151d and fixed by r11-199-g2b42509f8b7bdf.
Tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/109724
* g++.dg/torture/pr109724.C: New testcase.
---
RISC-V Linux encodes the ABI into the path, so in theory, we can only use that
to select multi-lib paths, and no way to use different multi-lib paths between
`rv32i/ilp32` and `rv32ima/ilp32`, we'll mapping both to `/lib/ilp32`.
It's hard to do that with GCC's builtin multi-lib selection
Can I please get permission for fixing this ICE?
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616221.html
Martin
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