2020-06-17 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (MININT): New defined
constant.
(exit_codes): New enum.
(consume_whitespace): New function.
(advance_line): Likewise.
(safe_inc_pos): Likewise.
(match_identifier): Likewise
This patch adds a tiny subset of the built-in and overload descriptions.
2020-06-17 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: New.
* config/rs6000/rs6000-overload.def: New.
---
gcc/config/rs6000/rs6000-builtin-new.def | 178 +++
gcc/config
2020-06-17 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (restriction): New enum.
(typeinfo): Add restriction field.
(match_const_restriction): Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 136
1 file changed, 136 insertions
2020-06-17 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (bif_file): New filescope
variable.
(ovld_file): Likewise.
(header_file): Likewise.
(init_file): Likewise.
(defines_file): Likewise.
(pgm_path): Likewise.
(bif_path
2020-06-17 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (match_basetype):
Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c
b/gcc/config/rs6000
2020-06-17 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c: New.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 142
1 file changed, 142 insertions(+)
create mode 100644 gcc/config/rs6000/rs6000-gen-builtins.c
diff --git a/gcc/config/rs6000/rs6000-gen
From: Kelvin Nilsen
Add new insns vextdu[bhw]vlx, vextddvlx, vextdu[bhw]vhx, and
vextddvhx, along with built-in access and overloaded built-in
access to these insns.
Changes from previous patch:
* Removed the int iterators
* Created separate expansions and insns
vextractl
On 5/12/20 1:21 PM, Segher Boessenkool wrote:
Hi!
On Mon, May 11, 2020 at 09:56:14PM -0500, Bill Schmidt wrote:
On 5/11/20 9:48 AM, David Edelsohn wrote:
On Sun, May 10, 2020 at 9:14 AM Bill Schmidt
wrote:
* config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant
On 5/12/20 4:54 AM, Segher Boessenkool wrote:
Hi!
Looks fine to me... Just the same generic things as before, things we
can improve later, not even limited to this series:
On Sat, May 09, 2020 at 08:16:26AM -0500, Bill Schmidt wrote:
* config/rs6000/altivec.md (UNSPEC_VSTRIR): New
On 5/11/20 9:48 AM, David Edelsohn wrote:
On Sun, May 10, 2020 at 9:14 AM Bill Schmidt wrote:
From: Kelvin Nilsen
Add new insns vextdu[bhw]vlx, vextddvlx, vextdu[bhw]vhx, and
vextddvhx, along with built-in access and overloaded built-in
access to these insns.
Bootstrapped and tested
On 5/11/20 7:16 AM, Segher Boessenkool wrote:
Hi!
On Sat, May 09, 2020 at 08:08:34PM -0500, Bill Schmidt wrote:
I should have noticed this patch before submitting Kelvin's earlier
related patches, sorry. I think it should still be fine to apply
the patches in order, but if you'd like me
On 5/11/20 5:21 AM, Segher Boessenkool wrote:
Hi!
On Sat, May 09, 2020 at 12:05:08PM -0500, Bill Schmidt wrote:
From: Carl Love
Add support for xxgenpcv[dw]m, along with individual and overloaded
built-in functions for access.
(xxgenpcvm_): New insn.
(xxgenpcvm): New
On 5/8/20 6:51 PM, Segher Boessenkool wrote:
On Fri, May 08, 2020 at 08:17:18AM -0500, Bill Schmidt wrote:
From: Kelvin Nilsen
Add support for new scalar instructions for counting leading or
trailing zeros under control of a bitmask.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu
On 5/8/20 3:47 PM, Segher Boessenkool wrote:
Hi,
On Thu, May 07, 2020 at 09:29:03PM -0500, Bill Schmidt wrote:
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 5ef4889ba55..33ba57855bc 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
From: Kelvin Nilsen
Add new insns vextdu[bhw]vlx, vextddvlx, vextdu[bhw]vhx, and
vextddvhx, along with built-in access and overloaded built-in
access to these insns.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions, using a Power9 configuration. Is this okay for
From: Kelvin Nilsen
Changes to the built-in specification occurred after early patches
added support for these. The name of vec_clzm became vec_cntlzm,
and vec_ctzm became vec_cnttzm. Four of the overloaded forms of
vec_gnb were removed, and the fourth argument redefined as an
unsigned int,
From: Carl Love
Add support for xxgenpcv[dw]m, along with individual and overloaded
built-in functions for access.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions, using a POWER9 compiler. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-09 Carl Love
From: Kelvin Nilsen
Adds new instructions vstribr, vstrihr, vstribl, and vstrihl, with
overloaded built-in support.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions, using a compiler configured for Power9. Is this okay
for master?
Thanks,
Bill
[gcc]
2020-05-08
From: Kelvin Nilsen
Add the xxeval insn and access it via the vec_ternarylogic built-in
function. As part of this, add support to the built-in function
infrastructure for functions that take four arguments.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions, using a
From: Kelvin Nilsen
Add scalar instructions for parallel bit deposit and extract, with
built-in function support.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-08 Kelvin Nilsen
*
Please ignore, I sent the wrong ChangeLog. Will try again momentarily.
Sorry,
Bill
On 5/8/20 3:05 PM, Bill Schmidt via Gcc-patches wrote:
From: Kelvin Nilsen
Add scalar instructions for parallel bit deposit and extract, with
built-in function support.
Bootstrapped and tested on powerpc64le
From: Kelvin Nilsen
Add scalar instructions for parallel bit deposit and extract, with
built-in function support.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-08 Kelvin Nilsen
*
On 5/8/20 2:00 PM, Segher Boessenkool wrote:
On Thu, May 07, 2020 at 09:11:32PM -0500, Bill Schmidt wrote:
From: Kelvin Nilsen
Add support for new vclzdm and vctzdm vector instructions that
count leading and trailing zeros under control of a mask.
Bootstrapped and tested on powerpc64le
From: Kelvin Nilsen
Add new vector instructions to clear leftmost and rightmost bytes.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-08 Kelvin Nilsen
* config/rs6000/altivec.h (vec_clrl): New
From: Kelvin Nilsen
Add support for new scalar instructions for counting leading or
trailing zeros under control of a bitmask.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-08 Kelvin Nilsen
*
From: Kelvin Nilsen
Add the new vector centrifuge-doubleword instruction and built-in
function access.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-08 Kelvin Nilsen
* config/rs6000/altivec.h
From: Kelvin Nilsen
Add the centrifuge-doubleword instruction and built-in access.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-08 Kelvin Nilsen
* config/rs6000/rs6000-builtin.def
From: Kelvin Nilsen
Add support for the vgnb instruction, which gathers every Nth bit
per vector element.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Thanks,
Bill
[gcc]
2020-05-07 Kelvin Nilsen
Bill Schmidt
Bill Schmidt
* config/rs6000/altivec.h (vec_pdep): New macro implementing new
built-in function.
(vec_pext): Likewise.
* config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
(UNSPEC_VPEXTD): Likewise.
(vpdepd): New insn.
(vpextd
Bill Schmidt
* config/rs6000/altivec.h (vec_clzm): New macro.
(vec_ctzm): Likewise.
* config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
(UNSPEC_VCTZDM): Likewise.
(vclzdm): New insn.
(vctzdm): Likewise.
* config/rs6000
From: Kelvin Nilsen
Dejagnu targets for these.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for master?
Patch shepherded by Bill Schmidt on behalf of Kelvin Nilsen.
Thanks!
Bill
2020-03-04 Kelvin Nilsen
* gcc.target/powerpc/dg-future
On 5/6/20 6:48 PM, Segher Boessenkool wrote:
On Wed, May 06, 2020 at 03:41:35PM -0500, Bill Schmidt wrote:
For all of these, I forgot to mention that they have been bootstrapped
and tested on powerpc64le-unknown-linux-gnu with no regressions. Are
these okay for trunk, after GCC 10 is fully
For all of these, I forgot to mention that they have been bootstrapped
and tested on powerpc64le-unknown-linux-gnu with no regressions. Are
these okay for trunk, after GCC 10 is fully released?
Thanks,
Bill
On 5/6/20 3:31 PM, Bill Schmidt via Gcc-patches wrote:
*** BLURB HERE ***
Bill
*** BLURB HERE ***
Bill Schmidt (4):
Add insns for setbc and setbcr
Add tests for setbc and setbcr
Add insns for setnbc and setnbcr
Add tests for setnbc and setnbcr
gcc/config/rs6000/rs6000.md | 100 +---
gcc/testsuite/gcc.target/powerpc/setbc.h| 27
2020-05-06 Segher Boessenkool
* gcc.target/powerpc/setnbc.h: New.
* gcc.target/powerpc/setnbceq.c: New.
* gcc.target/powerpc/setnbcge.c: New.
* gcc.target/powerpc/setnbcgt.c: New.
* gcc.target/powerpc/setnbcle.c: New.
*
2020-05-06 Segher Boessenkool
* gcc.target/powerpc/setbc.h: New.
* gcc.target/powerpc/setbceq.c: New.
* gcc.target/powerpc/setbcge.c: New.
* gcc.target/powerpc/setbcgt.c: New.
* gcc.target/powerpc/setbcle.c: New.
* gcc.target/powerpc/setbclt.c:
New instructions setbc and setbcr. setbc sets a GPR to 1 if some
condition register bit is set, and 0 otherwise; setbcr does it the
other way around.
2020-05-06 Segher Boessenkool
* config/rs6000/rs6000.md (setbc_signed_): New
define_insn.
(*setbcr_signed_): Likewise.
setnbc[r] is like setbc[r], but it writes -1 instead of 1 to the GPR.
2020-05-06 Segher Boessenkool
* config/rs6000/rs6000.md (*setnbc_signed_): New
define_insn.
(*setnbcr_signed_): New define_insn.
(*neg_eq_): Avoid for TARGET_FUTURE; add missing && 1.
On 4/22/20 1:20 PM, Carl Love wrote:
GCC maintainers:
The following is a trivial patch to fix a comment describing the
intrinsic function _mm_movemask_epi8. The comment was expanded to
clarify the layout of the returned result.
The patch does not make any functional changes.
Please let me
On 4/28/20 10:42 AM, Jakub Jelinek wrote:
On Tue, Apr 28, 2020 at 10:16:24AM -0500, Bill Schmidt via Gcc-patches wrote:
I think this looks good. My only comment would be to please add some
comments in the test cases about the purpose, or at least to explain
the regexes in the scan-assembler
On 4/28/20 6:38 AM, Jakub Jelinek via Gcc-patches wrote:
Hi!
Ok, I've tried:
struct X { };
struct Y { int : 0; };
struct Z { int : 0; Y y; };
struct U : public X { X q; };
struct A { float a, b, c, d; };
struct B : public X { float a, b, c, d; };
struct C : public Y { float a, b, c, d; };
Jakub, thanks for continuing to track down and fix all these cases.
I think this looks good. My only comment would be to please add some
comments in the test cases about the purpose, or at least to explain
the regexes in the scan-assembler-* directives, to save us all some
mental cycles in the
A user reported that we are still referring to a public review
draft of the ELFv2 ABI specification. Replace that by a permalink.
Tested with "make pdf" and verified the link is hot. Is this okay
for master?
Thanks,
Bill
2020-04-24 Bill Schmidt
* gcc/doc/extend.tex
On 4/22/20 11:49 AM, Jakub Jelinek wrote:
On Wed, Apr 22, 2020 at 11:24:09AM -0500, Bill Schmidt wrote:
Hm, but this patch violates the ELFv2 ABI as written. The ABI includes:
"Floating-point and vector aggregates that contain padding words and
integer fields with a width of 0 s
On 4/22/20 8:11 AM, Jakub Jelinek via Gcc-patches wrote:
Hi!
As mentioned in the PR and on IRC, the recently added struct-layout-1.exp
new tests FAIL on powerpc64le-linux (among other targets).
FAIL: tmpdir-g++.dg-struct-layout-1/t032 cp_compat_x_tst.o-cp_compat_y_tst.o
execute
FAIL:
On 4/17/20 1:53 AM, Richard Biener wrote:
Yeah well, but RTL is not in SSA form and there's no RTL IL verification
in place to track degradation. And we even work in the opposite way
when expanding to RTL from SSA, coalescing as much as we can ...
Which is itself problematic, introducing
On 3/11/20 2:00 PM, Carl Love wrote:
GCC maintianers:
The following patch add a check to make sure the user did not specify
-mno_fprnd with the builtins __builtin_vsx_xsrdpim and
__builtin_vsx_xsrdpip. These builtins are incompatible with the
-mno_fprnd command line. The check prevents GCC
error is now:
f951: Error: '-mno-altivec' turns off '-mpower9-vector'
Is this okay for master, and for backport to releases/gcc-9 after the
9.3 release? There's no urgency in getting this in 9.3.
Thanks,
Bill
2020-03-02 Bill Schmidt
* rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define
On 3/2/20 11:10 AM, Tulio Magno Quites Machado Filho wrote:
Bill Schmidt writes:
One tiny nit on the document: For the "b" value, let's just say "VSX"
rather than
"VSX as defined in PowerISA v2.07)." We will plan to only change values
in case
a diff
In 2/28/20 10:31 AM, Jakub Jelinek wrote:
On Fri, Feb 28, 2020 at 04:23:03PM +, GT wrote:
Do we want to change the name and title of the document since Segher doesn't
believe it
is an ABI. My initial suggestion: "POWER Architecture Specification of Scalar
Function
to Vector Function
On 2/27/20 2:21 PM, Bill Schmidt wrote:
On 2/27/20 12:48 PM, GT wrote:
Done.
The updated document is at:
https://sourceware.org/glibc/wiki/HomePage?action=AttachFile=view=powerarchvectfuncabi.html
Looks good. Can you please also remove the 'c' ABI from the mangling, as
earlier agreed
On 2/27/20 12:48 PM, GT wrote:
‐‐‐ Original Message ‐‐‐
On Thursday, February 27, 2020 9:26 AM, Bill Schmidt
wrote:
Upon reflection, I agree. Bert, we need to make changes to the document to
reflect this:
(1) "Calling convention" should refer to ELFv1 for powerpc64
On 2/27/20 9:30 AM, Jakub Jelinek wrote:
On Thu, Feb 27, 2020 at 09:19:25AM -0600, Bill Schmidt wrote:
On 2/27/20 8:52 AM, Jakub Jelinek wrote:
On Thu, Feb 27, 2020 at 08:47:19AM -0600, Bill Schmidt wrote:
But is this actually a good idea? It seems to me this will generate lousy
code
On 2/27/20 8:52 AM, Jakub Jelinek wrote:
On Thu, Feb 27, 2020 at 08:47:19AM -0600, Bill Schmidt wrote:
But is this actually a good idea? It seems to me this will generate lousy
code in the absence of hardware support. Won't we be better off warning and
ignoring the directive, leaving the code
On 2/26/20 8:31 AM, Jakub Jelinek wrote:
On Wed, Feb 26, 2020 at 07:55:53AM -0600, Bill Schmidt wrote:
The hope is that we can create a vectorized version that returns values
in registers rather than the by-ref parameters, and add code to GCC to
copy things around correctly following the call
On 2/27/20 4:52 AM, Segher Boessenkool wrote:
On Tue, Feb 25, 2020 at 07:43:09PM -0600, Bill Schmidt wrote:
The reason that homogeneous aggregates matter (at least somewhat) is that
the ABI ^H^H^H^HAPI requires establishing a calling convention and a name-
mangling formula that includes
On 2/26/20 2:18 AM, Jakub Jelinek wrote:
On Tue, Feb 25, 2020 at 07:43:09PM -0600, Bill Schmidt wrote:
The reason that homogeneous aggregates matter (at least somewhat) is that
the ABI ^H^H^H^HAPI requires establishing a calling convention and a name-
mangling formula that includes the length
On 2/25/20 12:45 PM, Segher Boessenkool wrote:
Hi!
On Tue, Feb 25, 2020 at 04:53:17PM +, GT wrote:
‐‐‐ Original Message ‐‐‐
On Sunday, February 23, 2020 11:45 AM, Bill Schmidt
wrote:
As I just wrote on gcc-patches, we should disable libmvec for powerpc64.
The vector ABI
On 2/25/20 4:00 PM, Segher Boessenkool wrote:
On Mon, Feb 24, 2020 at 03:20:30PM -0600, Bill Schmidt wrote:
These two test cases have assembly code that requires a valid TOC.
Make sure that we don't use the PC-relative ABI extensions that
violate this requirement.
Tested and verified
These two test cases have assembly code that requires a valid TOC.
Make sure that we don't use the PC-relative ABI extensions that
violate this requirement.
Tested and verified on powerpc64le-unknown-linux-gnu. Is this
okay for trunk?
Thanks,
Bill
2020-02-24 Bill Schmidt
On 2/24/20 11:08 AM, Jakub Jelinek wrote:
On Mon, Feb 24, 2020 at 11:04:55AM -0600, Bill Schmidt wrote:
+ if (clonei->simdlen
+ && (clonei->simdlen < 2
+ || clonei->simdlen > 1024
Assuming that clonei->simdlen matches "vector length" in the ABI,
tps://github.com/power8-abi-doc/vector-function-abi>
Bill Schmidt of IBM Linux Tech. Center has committed to eventually
integrating this ABI into the official POWER Architecture specifications.
He is a GCC and Toolchain Architect so this should ease concerns over
how much to trust an ABI which is not an of
On 2/23/20 1:12 PM, Segher Boessenkool wrote:
On Sun, Feb 23, 2020 at 10:55:53AM -0600, Bill Schmidt wrote:
Though I'm usually uncomfortable with kicking the can down the road on these
sorts of things, I can probably be convinced in this case. Tulio and I were
wondering why the libmvec
On 2/23/20 11:33 AM, Jakub Jelinek wrote:
On Sun, Feb 23, 2020 at 10:42:17AM -0600, Bill Schmidt wrote:
Have I missed something crucial?
I haven't seen anything in the patch that would only enable it for ELFv2,
and while powerpc64le-linux probably assumes TARGET_VSX unconditionally
(haven't
On 2/20/20 1:14 PM, GT wrote:
‐‐‐ Original Message ‐‐‐
On Wednesday, February 19, 2020 12:33 PM, Bill Schmidt
wrote:
The reason 'c' was added to the ABI is this mailing list discussion:
https://sourceware.org/ml/libc-alpha/2019-11/msg00765.html
As long as 'b' specifies that the VSX
On 2/14/20 4:09 PM, Jakub Jelinek wrote:
On Fri, Feb 14, 2020 at 10:02:39PM +, GT wrote:
Function rs6000_simd_clone_adjust, even though it's body is empty,
cannot simply be removed. I tried it. It resulted in ICE. In my
view, leaving it empty is preferable to modifying other files
On 2/19/20 1:10 PM, GT wrote:
‐‐‐ Original Message ‐‐‐
On Wednesday, February 19, 2020 12:33 PM, Bill Schmidt
wrote:
The reason 'c' was added to the ABI is this mailing list discussion:
https://sourceware.org/ml/libc-alpha/2019-11/msg00765.html
As long as 'b' specifies that the VSX
Sorry I missed this discussion until now, I have been out of the office
much of the last week.
On 2/16/20 2:10 PM, GT wrote:
‐‐‐ Original Message ‐‐‐
On Friday, February 14, 2020 5:09 PM, Jakub Jelinek ja...@redhat.com wrote:
On Fri, Feb 14, 2020 at 10:02:39PM +, GT wrote:
On 2/10/20 9:24 PM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 10, 2020 at 01:45:42PM -0500, Michael Meissner wrote:
This patch renames the PowerPC internal switch -mprefixed-addr to be
-mprefixed.
If you use -mpcrel, you must be using the 64-bit ELF v2 ABI, and the code model
must be medium.
Hi,
PR93570 reports that the documentation shows __builtin_mtfsf to return a double,
but that is incorrect. The return signature should be void. Corrected herein.
Built on powerpc64le-unknown-linux-gnu and verified correct PDF output.
Committed
as obvious.
Thanks!
Bill
2020-02-06 Bill
On 2/5/20 6:30 AM, Segher Boessenkool wrote:
Hi!
On Wed, Feb 05, 2020 at 08:57:16AM +0100, Richard Biener wrote:
On Tue, Feb 4, 2020 at 6:40 PM Segher Boessenkool
wrote:
On Mon, Feb 03, 2020 at 08:26:01PM -0600, Bill Schmidt wrote:
My intent is to make adding new built-in functions
On 2/4/20 4:36 PM, Segher Boessenkool wrote:
On Tue, Feb 04, 2020 at 03:10:32PM -0600, Bill Schmidt wrote:
I really don't think using the new acronym "bif" helps; built-in
functions already are often called "builtins" (or "intrinsics", which is
problematic itself
On 2/4/20 12:27 PM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 03, 2020 at 08:26:02PM -0600, Bill Schmidt wrote:
Includes header documentation and initial set of include directives.
Please use full sentences in commit messages.
OK.
+/* This program generates built-in function
2020-02-03 Bill Schmidt
* config.gcc (powerpc-*-*-*): Add rs6000-bif.o to extra_objs.
* config/rs6000/t-rs6000 (rs6000-genbif.o): New target.
(rbtree.o): Likewise.
(rs6000-genbif): Likewise.
(rs6000-bif.c): Likewise.
(rs6000-bif.o): Likewise
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (write_defines_file): Implement.
---
gcc/config/rs6000/rs6000-genbif.c | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-genbif.c
b/gcc/config/rs6000/rs6000-genbif.c
index 7bb7d2b24a4..0bcd035060d
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (complete_vector_type): New
function.
(complete_base_type): New function.
(construct_fntype_id): New function.
(parse_bif_entry): Call construct_fntype_id.
(parse_ovld_entry): Likewise
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (typemap): New struct.
(TYPE_MAP_SIZE): New defined constant.
(type_map): New filescope variable.
(write_fntype): New callback function.
(map_token_to_type_node): New function
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (write_autogenerated_header): New
function.
(write_bif_enum): New callback function.
(write_ovld_enum): New callback function.
(write_decls): New function.
(write_extern_fntype): New
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (ovld_stanza): New struct.
(MAXOVLDSTANZAS): New defined constant.
(ovld_stanzas): New filescope variable.
(curr_ovld_stanza): Likewise.
(MAXOVLDS): New defined constant.
(ovlddata): New
2020-02-03 Bill Schmidt
* config/rs6000/rbtree.c: New file.
* config/rs6000/rbtree.h: New file.
---
gcc/config/rs6000/rbtree.c | 233 +
gcc/config/rs6000/rbtree.h | 51
2 files changed, 284 insertions(+)
create mode 100644 gcc
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (MAXBIFSTANZAS): New defined
constant.
(bif_stanzas): New filescope variable.
(curr_bif_stanza): Likewise.
(fnkinds): New enum.
(typelist): New struct.
(attrinfo): New struct
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (void_status): New enum.
(basetype): Likewise.
(restriction): Likewise.
(typeinfo): New struct.
(match_basetype): New function.
(match_const_restriction): New function.
(match_type
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (rbtree.h): New include.
(num_bif_stanzas): New filescope variable.
(num_bifs): Likewise.
(num_ovld_stanzas): Likewise.
(num_ovlds): Likewise.
(exit_codes): Add more enum values
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (MININT): New defined constant.
(exit_codes): New enum.
(consume_whitespace): New function.
(advance_line): New function.
(safe_inc_pos): New function.
(match_identifier): New function
this as I move through the transition.
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-bif.def: New file.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
Annotate some deprecated and bogus entries.
* config/rs6000/rs6000-overload.def: New file.
---
gcc
Includes header documentation and initial set of include directives.
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c: New file.
---
gcc/config/rs6000/rs6000-genbif.c | 124 ++
1 file changed, 124 insertions(+)
create mode 100644 gcc/config/rs6000
of the patches may still be a bit large. Please
let me know if you'd like me to break any of them up.
Thanks in advance for the review!
Bill Schmidt (14):
Initial create of rs6000-genbif.c.
Add stubs for input files. These will grow much larger.
Add file support and functions for diagnostic
2020-02-03 Bill Schmidt
* config/rs6000/rs6000-genbif.c (bif_file): New filescope
variable.
(ovld_file): Likewise.
(header_file): Likewise.
(init_file): Likewise.
(defines_file): Likewise.
(pgm_path): Likewise.
(bif_path
On 1/31/20 9:42 AM, Segher Boessenkool wrote:
Hi Bill,
Thanks a lot for looking at this! :-)
On Fri, Jan 31, 2020 at 08:49:21AM -0600, Bill Schmidt wrote:
+(define_register_constraint "wa"
"rs6000_constraints[RS6000_CONSTRAINT_wa]"
+ "A VSX register (VSR), @c
On 1/30/20 6:17 PM, Segher Boessenkool wrote:
This is my current work-in-progress version. There still are rough
edges, and not much is done for the output modifiers yet, but it should
be in much better shape wrt the user manual now. The internals manual
also is a bit better I think.
I apologize, I sent this to the wrong mailing list, this had meant to be
internal. But thank you very much for the information! It appears we
have some adjustments to make.
Thanks!
Bill
On 1/19/20 8:46 AM, H.J. Lu wrote:
On Sun, Jan 19, 2020 at 6:33 AM Bill Schmidt wrote:
Question
Question: Is the new gcc git repository at gcc.gnu.org/git/gcc.git
using the same location as the earlier git mirror did? I'm curious
whether our repository on pike is still syncing with the new master, or
whether we need to make some adjustments before we next rebase pu
against master.
Hi!
I can't approve this, but for what it's worth it looks fine to me.
Bill
On 12/11/19 6:31 AM, Kewen.Lin wrote:
Hi,
We found that the vectorization cost modeling on scalar COND_EXPR is a bit off
on rs6000. One typical case is 548.exchange2_r, -Ofast -mcpu=power9 -mrecip
Hi,
I noticed this function should have been made static in the recent separation of
rs6000-call.c from rs6000.c. Bootstrapped and tested on powerpc64le-linux-gnu,
committed.
Thanks!
Bill
Make rs6000_invalid_builtin static.
2019-12-02 Bill Schmidt
* config/rs6000/rs6000-call.c
this on P8 BE, but clearly not.
Tested on powerpc64-unknown-linux-gnu, committed as obvious. Will backport
soon.
Thanks,
Bill
2019-10-15 Bill Schmidt
PR target/92093
* gcc.target/powerpc/pr91275.c: Fix type and endian issues.
Index: gcc/testsuite/gcc.target/powerpc/pr91275.c
otstrapped and tested on powerpc64le-unknown-linux-gnu. Is this okay
for trunk, and for backport to all active branches after an appropriate
waiting period?
Thanks,
Bill
[gcc]
2019-09-30 Bill Schmidt
* config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Don't swap
vpmsumd.
[gcc
On 9/26/19 12:00 PM, Segher Boessenkool wrote:
Hi Will,
On Thu, Sep 26, 2019 at 10:40:29AM -0500, will schmidt wrote:
Update our (rs6000) vector load built-ins with the PURE attribute. These
were previously given the MEM attribute, which meant that redundant loads
surrounding the built-in
On 9/19/19 1:34 PM, Segher Boessenkool wrote:
Hi!
On Tue, Sep 17, 2019 at 09:45:54AM +0200, Richard Biener wrote:
The following fixes an old vectorizer issue with realignment support
(thus only powerpc is affected) and BB vectorization. The realignment
token is set up from the wrong
On 8/14/19 5:06 PM, Michael Meissner wrote:
> This patch adds prefixed memory support to all offsettable instructions.
>
> Unlike previous versions of the patch, this patch combines all of the
> modifications for addressing to one patch. Previously, I had 3 separate
> patches (one for PADDI, one
Hi Mike, just a couple points from me...
On 8/15/19 4:19 PM, Michael Meissner wrote:
> Index: gcc/config/rs6000/rs6000.c
> ===
> --- gcc/config/rs6000/rs6000.c(revision 274172)
> +++ gcc/config/rs6000/rs6000.c
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