Re: [patch] Add new -gmlt option for min. debug info with line tables (issue4440072)

On Tue, 2011-05-03 at 16:24 -0400, Jason Merrill wrote: That makes sense to me; it seems appropriate for -g1 to have information that makes a backtrace more informative, but not information for interactive debugging. Jim, do you have an opinion? I'm not aware of any significant use of -g1.

Re: [AArch64][PR65375] Fix RTX cost for vector SET

Resending, now that I've figured out how to make gmail send text email instead of html. Almost, what we want at the moment is COSTS_N_INSNS (1) + extra_cost-vect.alu This won't work, because extra_cost-vect.alu is COSTS_N_INSNS (1), which means the total is COSTS_N_INSNS (2). The

[wwwdocs] Update my association in steering committee list

I have checked in this change. Validated as XHTML 1.0 Transitional. Jim Index: htdocs/steering.html === RCS file: /cvs/gcc/wwwdocs/htdocs/steering.html,v retrieving revision 1.39 diff -r1.39 steering.html 41c41 liJim Wilson

gcc make clean fixes

/ChangeLog (revision 222394) +++ ada/ChangeLog (working copy) @@ -1,3 +1,8 @@ +2015-04-23 Jim Wilson jim.wil...@linaro.org + + * gcc-interface/Makefile-lan.in (ada.mostlyclean): Remove gnatbind + and gnat1. + 2015-04-13 Eric Botcazou ebotca...@adacore.com * gnatvsn.ads (Library_Version): Bump to 6

update docs for --enable-languages

language if bootstrapping. And lto is a boot language if --enable-lto which is the default. Jim Index: ChangeLog === --- ChangeLog (revision 222491) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2015-04-27 Jim Wilson jim.wil

Re: gcc make clean fixes

On Mon, Apr 27, 2015 at 12:30 PM, Jeff Law l...@redhat.com wrote: Looks good to me. Please install if you haven't already done so. Thanks, I checked in the patch. I'm not maintainer of anything currently, so I'm assuming all of my patches need to be approved before check in. I'm pretty rusty,

Re: [Bug target/66015] New: align directives not propagated after __attribute__ ((__optimize__ (O2)))

On Tue, 2015-05-05 at 14:19 +0200, Christian Bruel wrote: I don't the environment to run the testsuite for ia64. would you mind giving it a try and verify that it fixes the issue ? I don't have ia64 hardware anymore. The GCC compile farm advertises ia64 hardware

[PATCH, doc] fix match-and-simplify API doc errors

-in ternary function case with four tree args is missing. Jim 2015-05-07 Jim Wilson jim.wil...@linaro.org * doc/match-and-simplify.texi (GIMPLE API): Add missing fourth tree arg to last gimple_simplify declaration. Add missing gimple_build declaration for built-in function case with four tree args

[PATCH, ARM, doc] add missing -mtune options

I noticed that the list of -mtune options in the arm-cores.def file didn't match the list in the doc/invoke.texi file. There are 3 cores missing: generic-armv7-a, cortex-a17, and cortex-a17.cortex-a7. This patch adds the missing cores to the docs. Jim 2015-05-07 Jim Wilson jim.wil

Re: update docs for --enable-languages

ping https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01690.html Jim On Mon, Apr 27, 2015 at 5:09 PM, Jim Wilson jim.wil...@linaro.org wrote: I noticed this while working on my mostlyclean patch. The list of languages in the docs for --enable-languages is incomplete. It is missing jit and lto

[PATCH] move check-gcc parallelize value into C front end

to be the only testsuite target that hasn't already been parallelized. This also looks like an oversight, but I haven't tested a patch for that yet. Jim gcc/ 2015-05-17 Jim Wilson jim.wil...@linaro.org * Makefile.in (check_gcc_parallelize): Delete. (lang_checks_parallelized): Update comment. gcc/c 2015

[PATCH, AARCH64] improve long double 0.0 support

patterns. I plan to submit a patch to fix them after this one is accepted. Jim 2015-06-03 Jim Wilson jim.wil...@linaro.org * config/aarch64/aarch64.c (aarch64_valid_floating_const): Move aarch64_float_const_zero_rtx_p check before TFmode check. * config/aarch64/aarch64.md (movtf): Don't call

Re: [PATCH, AARCH64] make stdarg functions work with +nofp

On Tue, Jun 2, 2015 at 3:45 AM, James Greenhalgh james.greenha...@arm.com wrote: On Tue, Jun 02, 2015 at 11:38:29AM +0100, Kyrill Tkachov wrote: Hi James, Jim, On 02/06/15 10:42, James Greenhalgh wrote: On Sat, May 23, 2015 at 12:24:00AM +0100, Jim Wilson wrote: The compiler currently ICEs

[PATCH, AARCH64] improve float/double 0.0 support

with a default languages make bootstrap and make check.. I see an additional 8 passes, and no other change in the testsuite results. Jim gcc/ 2015-06-19 Jim Wilson jim.wil...@linaro.org * config/aarch64/aarch64.md (movmode:GPF): Don't call force_reg if op1 is an fp zero. (movsf_aarch64): Change

Re: [PATCH, AARCH64] make stdarg functions work with +nofp

On Tue, Jun 16, 2015 at 1:46 AM, James Greenhalgh james.greenha...@arm.com wrote: I'm happy for this to be backported. Thanks. Applied. I think Grub probably wants to change if they want to be safe, from what I've read it looks like they are hoping to use something like a standard printf

[PATCH, AARCH64] movi type attribute confusion

is still waiting review, but the overlap is trivial to resolve so this should not be a problem. Jim 2015-06-12 Jim Wilson jim.wil...@linaro.org * config/aarch64/aarch64.md (movmode_aarch64): Change alternative 2 to use neon_move instead of mov_imm. (movdi_aarch64): Change alternative 14

Re: [PATCH, AARCH64] improve long double 0.0 support

On 06/03/2015 05:35 PM, Jim Wilson wrote: I noticed that poor code is emitted for a long double 0.0. ping https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00370.html Jim

Re: C++ PATCH to change default dialect to C++14

that. Trying it now, I see that my build gets past the point that it failed, so this does appear to work. I won't be able to finish a proper test until tomorrow, but for now this patch seems to work. Jim 2015-07-01 Jim Wilson jim.wil...@linaro.org * graphite-blocking.c (HAVE_isl): Include

Re: C++ PATCH to change default dialect to C++14

On 07/01/2015 11:26 AM, Jason Merrill wrote: I've been threatening to do this for a couple of months, and now that the regressions are under control I think it's time. This patch changes the default C++ dialect to C++14. Tested x86_64-pc-linux-gnu, applying to trunk. This causes a build

Re: C++ PATCH to change default dialect to C++14

On 07/01/2015 11:17 PM, Jim Wilson wrote: On Wed, Jul 1, 2015 at 10:21 PM, Jason Merrill ja...@redhat.com wrote: This document also says that A workaround until libraries get updated is to include cstddef or stddef.h before any headers from that library. Can you try modifying the graphite

Re: C++ PATCH to change default dialect to C++14

On Thu, Jul 2, 2015 at 6:08 AM, Richard Biener richard.guent...@gmail.com wrote: On Thu, Jul 2, 2015 at 3:05 PM, Richard Biener richard.guent...@gmail.com wrote: Yeah, I _think_ the fix is to move the isl includes below the system.h include. I tried this, and got a conflict for pretty much

[PATCH, AARCH64] make stdarg functions work with +nofp

. The testsuite already has multiple stdarg tests, so there is no need for another one. I tested this by verifying I get the same results for some simple testcasess with and without the patch, with and without using -mgeneral-regs-only and -mcpu=cortex-a53+nofp. 2015-05-22 Jim Wilson jim.wil...@linaro.org

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 7, 2015 at 8:07 AM, Jeff Law l...@redhat.com wrote: On 06/29/2015 07:15 PM, Jim Wilson wrote: So if these copies require a conversion, then isn't it fundamentally wrong to have a PHI node which copies between them? That would seem to implicate the eipa_sra pass as needing

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Thu, Jul 2, 2015 at 2:07 AM, Richard Earnshaw richard.earns...@foss.arm.com wrote: Not quite, ARM state still has more flexible addressing modes for unsigned byte loads than for signed byte loads. It's even worse with thumb1 where some signed loads have no single-register addressing mode

[PATCH, ARM] stop changing signedness in PROMOTE_MODE

/ 2015-06-29 Jim Wilson jim.wil...@linaro.org PR target/65932 * config/arm/arm.h (PROMOTE_MODE): Don't set UNSIGNEDP for QImode and HImode. gcc/testsuite/ 2015-06-29 Jim Wilson jim.wil...@linaro.org PR target/65932 * gcc.target/arm/wmul-1.c (mac): Change a and b to int pointers. Cast

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 14, 2015 at 9:13 AM, Richard Earnshaw richard.earns...@foss.arm.com wrote: We went through this a couple of weeks back. The backend documentation for PROMOTE_MODE says: I disagree that this is a fully resolved issue. I see clear problems with how the ARM port uses PROMOTE_MODE.

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Wed, Jul 15, 2015 at 6:04 AM, Michael Matz m...@suse.de wrote: Hi, On Tue, 14 Jul 2015, Jim Wilson wrote: Now that we do have the problem, we can't fix it without an ARM port ABI change, which is undesirable, so we may have to fix it with a MI change. What's the ABI implication

[PATCH] [ARM] neon-testgen.ml typo

knows ocaml will have to fix this. Meanwhile, the patch to fix the typo should still be OK, as this is a separate problem. Jim 2015-10-29 Jim Wilson <jim.wil...@linaro.org> * config/arm/neon-testgen.ml: Fix comment typo. Index: config/arm/neon-test

[PATCH] [C] fix for ICE with -g

problem may no longer be necessary. I haven't looked at that. Jim Index: gcc/c/ChangeLog === --- gcc/c/ChangeLog (revision 229395) +++ gcc/c/ChangeLog (working copy) @@ -1,3 +1,9 @@ +2015-10-26 Jim Wilson <jim.wil...@linaro.

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

ot already done. This was tested with a arm-eabi cross compiler build configured --with-multilib-list=aprofile, and then using ./xgcc -B./ -mcpu=X --print-libgcc to verify that processor names map to the correct libgcc multilib. Jim 2015-11-12 Jim Wilson <jim.wil...@linaro.org> * gcc/

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

On Fri, Nov 13, 2015 at 9:02 AM, Kyrill Tkachov wrote: > Sorry to chime in late on this, but while you're at it could > you please add an xgene1 entry? Yes, I just realized that xgene1 is missing too, I rushed the patch a little too much. I will revise it to add xgene1

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

Revised patch with the also missing xgene1 part added. Jim 2015-11-13 Jim Wilson <jim.wil...@linaro.org> * gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add lines for exynos-m1 and qdf24xx and xgene1 to match -march=armv8-a. Index: gcc/config/arm/t-ap

[PATCH] [ARM/Aarch64] add initial Qualcomm support

) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,13 @@ +2015-11-10 Jim Wilson <jim.wil...@linaro.org> + + * config/aarch64/aarch64-cores.def (qdf24xx): New. + * config/aarch64/aarch64-tune.md: Regenerated. + * config/arm/arm-cores.def (qdf24xx): New. + * config/arm/arm-tables.opt, config/arm/arm-t

Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support

On Wed, Nov 11, 2015 at 10:34 AM, Jim Wilson <jim.wil...@linaro.org> wrote: > I had to disable the cortex-a57 fma steering pass in the aarch64 port > while testing the patch. A bootstrap for aarch64 configured > --with-cpu=cortex-a57 gives multiple ICEs while building the s

Re: [PATCH] PR67305, tighten neon_vector_mem_operand on eliminable registers

On 11/04/2015 01:45 AM, Jiong Wang wrote: > So as Jim Wilson commented on the bugzilla, instead of "return !strict", > we need to only do the check if strict be true, and only does rejection > which means return FALSE, for all other cases, we need to go through > those n

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Wed, Jul 8, 2015 at 3:54 PM, Jeff Law l...@redhat.com wrote: On 07/07/2015 10:29 AM, Jim Wilson wrote: This is critically important as various parts of the compiler will take a degenerate PHI node and propagate the RHS of the PHI into the uses of the LHS of the PHI -- without doing any

Re: [PATCH, ARM] stop changing signedness in PROMOTE_MODE

On Tue, Jul 7, 2015 at 2:35 PM, Richard Biener richard.guent...@gmail.com wrote: On July 7, 2015 6:29:21 PM GMT+02:00, Jim Wilson jim.wil...@linaro.org wrote: signed sub-word locals. Thus to detect the need for a conversion, you have to have the decls, and we don't have them here

Re: [4/7] Use correct promoted mode sign for result of GIMPLE_CALL

On 09/08/2015 08:39 AM, Jeff Law wrote: > Is this another instance of the PROMOTE_MODE issue that was raised by > Jim Wilson a couple months ago? It looks like a closely related problem. The one I am looking at has confusion with a function arg and a local variable as they have differen

Re: [ping] pending patches

On 12/01/2015 11:58 PM, Eric Botcazou wrote: > IA-64 (stack checking improvement): > https://gcc.gnu.org/ml/gcc-patches/2015-11/msg01604.html OK. Jim

Re: [ARM][PR69194] Fix ICE in in extract_insn

Here is a smaller simpler testcase. Only the first four args get passed in regs, so the fifth one has address equal to the virtual incoming args reg which triggers the failure. typedef __simd128_float32_t float32x4_t; float32x4_t sub (float32x4_t a, float32x4_t b, float32x4_t c, float32x4_t d,

[PATCH] fix vectorizer performance problem on cygwin hosted cross compiler

no regressions. I've also done a SPEC CPU2000 run with and without the patch on aarch64-linux, there is no performance change. And I've verified it by building linpack for aarch64-linux with cygwin hosted cross compiler, x86_64 hosted cross compiler, and an aarch64 native compiler. Jim 2015-11-19 Jim

Re: [RFC][ARM][PR67714] signed char is zero-extended instead of sign-extended

On Tue, Jan 12, 2016 at 5:40 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > The info is in here > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65932 > See the comments on gcc.target/arm/wmul-[123].c which no longer > generate smulbb etc instructions, which are 16x16=32 expa

Re: [RFC][ARM][PR67714] signed char is zero-extended instead of sign-extended

On Mon, Jan 11, 2016 at 10:22 PM, kugan wrote: > When promote_function_mode and promote_ssa_mode changes the sign > differently, following is the cause for the problem in PR67714. > This is similar to PR65932 where sign change in PROMOTE_MODE causes problem >

Re: [RFC][ARM][PR67714] signed char is zero-extended instead of sign-extended

On Tue, Jan 12, 2016 at 5:10 PM, Kugan wrote: > Yes, making PROMOTE_MODE to work the same way as in > promote_function_mode in arm will fix this. Can you please point me to > the test cases that are regressing so that I can also start looking at them. The info

Re: [PATCH][wwwdocs][AArch64] Mention -mcpu=qdf24xx support for GCC 6

On Thu, Jun 9, 2016 at 1:43 AM, Kyrill Tkachov wrote: > On 03/06/16 21:32, Evandro Menezes wrote: >> Shouldn't this read "The Qualcomm QDF24xx processors are now supported via >> the"? >> > I used Jim's suggestion at >

[PATCH, AARCH64] add qdf24xx tuning structure

This adds a tuning structure for qdf24xx. This was tested with an aarch64-linux bootstrap and a make check, with no regressions. I also tested it with an x86_64-linux C make check to verify that I didn't break the testsuite for non aarch64 targets. I had to change one testcase because it

Re: [PATCH][AArch64] Enable -frename-registers at -O2 and higher

On Tue, May 31, 2016 at 2:56 AM, James Greenhalgh wrote: > As you're proposing to have this on by default, I'd like to give a chance > to hear whether there is consensus as to this being the right choice for > the thunderx, xgene1, exynos-m1 and qdf24xx subtargets. I

Re: RFC [1/2] divmod transform

On Mon, May 30, 2016 at 12:45 AM, Richard Biener wrote: > Joseph - do you know sth about why there's not a full set of divmod > libfuncs in libgcc? Because udivmoddi4 isn't a libfunc, it is a helper function for the div and mov libfuncs. Since we can compute the signed div

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On Mon, Jun 13, 2016 at 1:53 AM, James Greenhalgh <james.greenha...@arm.com> wrote: > On Fri, Jun 10, 2016 at 03:48:38PM -0700, Jim Wilson wrote: >> This adds a tuning structure for qdf24xx. This was tested with an > Have you seen my recent patch for Cortex-A57 that

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On Mon, Jun 13, 2016 at 3:01 AM, Kyrill Tkachov <kyrylo.tkac...@foss.arm.com> wrote: > Hi Jim, > > On 10/06/16 23:48, Jim Wilson wrote: >> >> This adds a tuning structure for qdf24xx. This was tested with an >> aarch64-linux bootstrap and a make check, with

[PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

=== --- ChangeLog (revision 234867) +++ ChangeLog (working copy) @@ -1,3 +1,12 @@ +2016-04-11 Jim Wilson <jim.wil...@linaro.org> + + Partial backport from trunk r228017. + 2015-09-22 Jason Merrill <ja...@redhat.com> + + PR c++/70613 + * doc/invoke.texi (-

Re: [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On 04/18/2016 01:12 PM, Jim Wilson wrote: On 04/11/2016 01:41 PM, Jim Wilson wrote: Here is a patch to correct the -fabi-version docs on the GCC 5 branch. https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html ping^2 Jim

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

On Thu, Apr 21, 2016 at 1:15 AM, Kyrill Tkachov wrote: > Jim, you added support for the qdf24xx identifier to -mcpu and -mtune. > Could you please suggest an appropriate entry to describe it? > I think the same format as the Cortex-A35 entry in this patch would be >

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

On Wed, Apr 27, 2016 at 3:33 AM, Kyrill Tkachov wrote: > Thanks, I've incorporated your and James' feedback. > Since James ok'd the content of the patch from an AArch64 perspective > I'll commit this later today if I receive no further feedback. There is no paragraph

Re: [PATCH][AArch64] Improve aarch64_case_values_threshold setting

On Mon, May 16, 2016 at 4:30 AM, James Greenhalgh wrote: > As this change will change code generation for all cores (except > Exynos-M1), I'd like to hear from those with more detailed knowledge of > ThunderX, X-Gene and qdf24xx before I take this patch. It looks like a

Re: PING^5 [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

This is my fifth ping. I just need someone to rubber stamp it so I can check it in. Maybe it would be easier if I volunteered to be a doc maintainer so I can self approve it? Jim On Mon, May 9, 2016 at 4:21 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > On Mon, May 2, 2016 at 12:1

[PATCH] misc minor doc fixes

Deletes text claiming that major version changes are rare, and fixes two misspellings of signaling. Tested with make info and make dvi. Jim 2016-05-16 Jim Wilson <jim.wil...@linaro.org> * doc/cpp.texi (__GNUC__): Major version changes are no longer rare. * doc/invoke.texi (-mna

[PATCH, ARM] use vmov.i64 to load 0 into FP reg if neon enabled

For this simple testcase double sub (void) { return 0.0; } Without the attached patch, an ARM compiler with neon support enabled, gives vldr.64 d0, .L2 With the attached patch, an ARM compiler with neon enabled, gives vmov.i64 d0, #0@ float which is faster and smaller, as there is no

Re: [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On Mon, Apr 25, 2016 at 11:47 AM, Bernd Schmidt wrote: Here is a patch to correct the -fabi-version docs on the GCC 5 branch. >>> https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html ping^3 I put an explanation of the patch history for gcc-5 in the PR

Re: [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On 04/11/2016 01:41 PM, Jim Wilson wrote: Here is a patch to correct the -fabi-version docs on the GCC 5 branch. Ping https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html Jim

PING^4 [PATCH, GCC 5] PR 70613, -fabi-version docs don't match implementation

On Mon, May 2, 2016 at 12:13 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Here is a patch to correct the -fabi-version docs on the GCC 5 branch. > https://gcc.gnu.org/ml/gcc-patches/2016-04/msg00480.html Maybe I didn't put enough info in the email the first 3 times? You can see

Re: [PATCH, ARM] use vmov.i64 to load 0 into FP reg if neon enabled

On Fri, May 6, 2016 at 7:29 AM, Kyrill Tkachov wrote: > Since you're modifying the both the ARM and Thumb2 pattern > can you please do two bootstrap and tests, one with --with-mode=arm > and one with --with-mode=thumb. > Ok after adding the assert mentioned above,

Re: [PATCH/AARCH64] Improve ThunderX code generation slightly with load/store pair

On 08/05/2016 12:18 AM, Andrew Pinski wrote: This patch disables the forming of the load/store pairs for SImode if we are tuning for ThunderX. I used the tuning flags route so it can be overridden if needed later on or if someone else wants to use the same method for their core. + if (mode

[PATCH] loop distribution bug fix

distributions. There is no measurable performance gain from the bug fix on the CPU2006 run time though I plan to spend some more time looking at this code to see if I can find other improvements. OK? Jim 2016-11-09 Jim Wilson <jim.wil...@linaro.org> * tree-loop-distribu

Re: [RFC] Possible folding opportunities for string built-ins

On 10/12/2016 08:55 AM, Joseph Myers wrote: On Wed, 12 Oct 2016, Martin Liška wrote: Last question is whether one can aggressively fold strcasecmp in a host compiler? Or are there any situations where results depends on locale? There are the usual issues with Turkish locales having the

Re: [PATCH] loop distribution bug fix

On Thu, Nov 10, 2016 at 2:53 AM, Richard Biener wrote: > The biggest "lack" of loop distribution is the ability to undo CSE so for I hadn't noticed this problem yet. I will have to take a look. > Then of course the cost model is purely modeled for STREAM (reduce the

[PATCH] fix aarch64/combine bootstrap miscompare

disabled in some cases. I haven't had a chance to look at this in detail yet. The patch was preapproved by Jeff and has been checked in. Jim 2017-03-17 Jim Wilson <jim.wil...@linaro.org> * combine.c (try_combine): Delete redundant i1 test. Call prev_nonnote_nondebug_insn i

Re: [RFC][PATCH][AArch64] Improve generic branch cost

On Tue, Mar 14, 2017 at 2:37 AM, James Greenhalgh wrote: > I'd like to hear comments from the Exynos-M1, Falkor and > xgene-1 subtarget contributors, particularly as these targets use > generic_branch_costs for their subtarget-sepcific tuning. It may be that > your patch

Re: [PATCH][AArch64] Enable AES fusion with -mcpu=generic

On Thu, Mar 16, 2017 at 11:01 AM, Andrew Pinski wrote: > On Thu, Mar 16, 2017 at 10:22 AM, Wilco Dijkstra > wrote: >> Many supported cores implement fusion of AES instructions. When fusion >> happens it can give a significant performance gain. If

Re: [PATCH][AArch64] Enable AUTOPREFETCHER_WEAK with -mcpu=generic

On Wed, Apr 5, 2017 at 5:38 AM, Wilco Dijkstra wrote: > Many supported cores use the AUTOPREFETCHER_WEAK setting which tries > to order loads and stores to improve streaming performance. Since significant > gains were reported in http://patchwork.ozlabs.org/patch/534469/

[PATCH] handling address mode changes inside extract_bit_field

This is a proposed patch for the bug 79794 which I just submitted. This isn't a regression, so this can wait for after the gcc 7 branch if necessary. The problem here is that a reg+offset MEM target is passed to extract_bit_field with a vector register source. On aarch64, we have an instruction

[PATCH, AArch64] Add falkor pipeline description.

This adds a pipeline description for the Qualcomm Falkor core. This was tested with a bootstrap and make check. There were no regressions. This gives about 0.5% performance gain on SPEC CPU2006 on our internal tree, which has a few other patches that aren't in the FSF tree yet. OK? Jim

Re: [PATCH] skip patchable_function_entry tests on ia64

On Fri, 2017-08-11 at 12:34 +0200, Torsten Duwe wrote: > gcc/testsuite/ChangeLog > 2017-08-11  Torsten Duwe   > > * c-c++-common/patchable_function_entry-default.c: Skip test on > ia64. > * c-c++-common/patchable_function_entry-decl.c: Likewise. > *

[PATCH] scheduler bug fix for AArch64 insn fusing SCHED_GROUP usage

queued. Since sched group insns always sort to the top of the list of insns to schedule, all sched group insns still get scheduled together as before. This has been tested with an Aarch64 bootstrap and make check. OK? Jim 2017-07-13 Jim Wilson <jim.wil...@linaro.org> PR rtl-optimization

Re: [PATCH, AArch64] Add RDMA support to Falkor.

Ping. Jim On Thu, Jun 29, 2017 at 1:53 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Falkor is an ARMV8-A part, but also includes the RDMA extension from > ARMV8.1-A. > I'd like to enable support for the RDMA instructions when -mcpu=falkor is > used, > and also ma

Re: [PATCH] Make __FUNCTION__ a mergeable string and do not generate symbol entry.

On Fri, Jul 14, 2017 at 1:35 AM, Martin Liška wrote: > May I ask Jim to test the patch? > Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. I started an aarch64 bootstrap to test. My fast machine is busy with work tasks, so I have to use a slower

Re: [PATCH] Make __FUNCTION__ a mergeable string and do not generate symbol entry.

On Fri, Jul 14, 2017 at 12:59 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > On Fri, Jul 14, 2017 at 1:35 AM, Martin Liška <mli...@suse.cz> wrote: >> May I ask Jim to test the patch? >> Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. > &g

Re: [PATCH] Kill TYPE_METHODS debug 1/9

On 07/14/2017 09:48 AM, Nathan Sidwell wrote: This changes dbxout and dwarf2out. Oh, the patch series survived a bootstrap on x86_64-linux. Changes to the debug info files requires a gdb make check with and without the patch to check for regressions. Since you are changing both dbxout

Re: Deprecate DBX/stabs?

On Fri, Jul 21, 2017 at 12:44 PM, Iain Sandoe wrote: > It ought to be already, in fact anything (powerpc*/x86/x86-64) >= Darwin9 (OS > X 10.5) ought to be defaulting to DWARF already, will check that sometime. Yes, they do default to dwarf2. The comments say pre-darwin9

Re: [PATCH] scheduler bug fix for AArch64 insn fusing SCHED_GROUP usage

Ping. https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00779.html On Thu, Jul 13, 2017 at 3:00 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > The AArch64 port uses SCHED_GROUP to mark instructions that get fused > at issue time, to ensure that they will be issued togeth

Re: [PATCH] Kill TYPE_METHODS 0/9

build, and checked in under the obvious rule. Jim 2017-07-25 Jim Wilson <jim.wil...@linaro.org> gcc/ PR bootstrap/81521 * config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS. Index: gcc/config/i386/winnt

Re: [PATCH] Kill TYPE_METHODS 0/9

build, and checked in under the obvious rule. Jim 2017-07-25 Jim Wilson <jim.wil...@linaro.org> gcc/ PR bootstrap/81521 * config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS. Index: gcc/config/i386/winnt

[PATCH] Delete files unused since openbsd 2 & 3 support was dropped.

Trevor Saunders deleted the x86 openbsd 2 & 3 support here. https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01368.html With that change, there are now 3 unused files that he missed. I noticed the gstabs.h file while looking at debugging info related files, and then did a consistency check and

Re: [PATCH 00/17] RFC: New source-location representation; Language Server Protocol

On 07/24/2017 01:04 PM, David Malcolm wrote: * The LSP implementation is a just a proof-of-concept, to further motivate capturing the extra data. Turning it into a "proper" LSP server implementation would be a *lot* more work, and I'm unlikely to actually do that (but maybe someone on

Re: [PATCH] dwarf2out.c patch for AIX

On 07/22/2017 08:29 PM, David Edelsohn wrote: This patch mirrors the earlier patch to copy debug_section_label into dl_section_ref and append the adjustment when necessary. With this patch, GDB is able to report correct macro information. Bootstrapped on powerpc-ibm-aix7.2.0.0 Debug related

Re: [PATCH, AArch64] Add RDMA support to Falkor.

Ping^2 On Tue, Jul 11, 2017 at 1:49 PM, Jim Wilson <jim.wil...@linaro.org> wrote: > Ping. > > Jim > > On Thu, Jun 29, 2017 at 1:53 PM, Jim Wilson <jim.wil...@linaro.org> wrote: >> Falkor is an ARMV8-A part, but also includes the RDMA extension from >> A

Re: [PATCH] Kill TYPE_METHODS debug 1/9

On Thu, Jul 20, 2017 at 2:00 PM, Nathan Sidwell wrote: > With this patch the gdb stabs test results are still awful, but they are > unchanged awfulness. Yes, the stabs support for C++ is poor. That is one of the reasons why almost everyone has switched to dwarf2. I wasn't sure

Re: Deprecate DBX/stabs?

On Fri, Jul 21, 2017 at 7:15 AM, David Edelsohn wrote: > AIX still uses DBX as the primary debugging format. AIX supports > DWARF but the AIX toolchain does not fully interoperate with DWARF > generated by GCC. We could still deprecate DBX_DEBUG while leaving XCOFF_DEBUG

[PATCH] Add RDMA support to Falkor.

Falkor is an ARMV8-A part, but also includes the RDMA extension from ARMV8.1-A. I'd like to enable support for the RDMA instructions when -mcpu=falkor is used, and also make the RDMA intrisics available. To do that, I need to add rdma as an architecture extension, and modify a few things to use

[PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

Early steppings had aarch32 support, current steppings don't, so the aarch32 support for falkor/qdf24xx needs to be dropped. This mostly involves removing falkor/qdf24xx references from the arm port. The qdf24xx_extra_costs structure moves from the arm port to the aarch64 port. This was tested

Re: [PATCH] handling address mode changes inside extract_bit_field

On Fri, May 12, 2017 at 7:01 PM, Martin Sebor wrote: > Explicitly passing the additional argument at all the call sites > can be mitigated by giving the new alt_rtl argument a default > value of NULL in the declarations of the extract_bit_field functions. I keep forgetting

Re: [PATCH] handling address mode changes inside extract_bit_field

On Thu, May 4, 2017 at 7:24 PM, Jeff Law <l...@redhat.com> wrote: > On 03/01/2017 03:06 PM, Jim Wilson wrote: > This seems fine to me. A testcase to add to the gcc.target testsuite would > be useful, but I don't think it's strictly necessary. Thanks for the review. It was 2

Re: Record equivalences for spill registers

On Sun, May 7, 2017 at 11:47 PM, Andrew Pinski wrote: > On Sun, May 7, 2017 at 11:37 PM, Richard Sandiford > wrote: >> Really sorry for the breakage. I'd forgotten that this depended on: >> >>

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Mon, Jun 12, 2017 at 3:40 AM, James Greenhalgh wrote: > In both the original patch, and the backport, you're modifying the > AArch64 options here. I'd expect the edits to be to the AArch32 options > (these start somewhere around line 15,000). Yes, I screwed this up.

[PATCH, libgfortran] proposed fix for SPEC CPU2017 621.wrf_s failures

As mentioned in bug 81195, I see openmp related failures due to a lack of locking of the newunit_stack and newunit_tos variables. The code locks when pushing onto the stack, but does not lock when popping from the stack. This can cause multiple threads to pop the same structure, which then

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists) wrote: > OK. does this need to go in the gcc-8 changes file? Falkor hasn't shipped yet. I'm dropping features that only existed in preproduction NDA hardware, so there isn't anything end user visible, and hence

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Wed, May 24, 2017 at 8:17 AM, Richard Earnshaw (lists) <richard.earns...@arm.com> wrote: > On 24/05/17 15:18, Jim Wilson wrote: >> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists) >> <richard.earns...@arm.com> wrote: >>> OK. does this need to go in

Re: [PATCH] handling address mode changes inside extract_bit_field

I've got a testcase to add for this patch. Sorry about the delay, I took some time off to deal with a medical problem. This was tested with and without the extract_bit_field patch. The testcase fails without the patch and works with the patch. Jim gcc/testsuite/ PR middle-end/79794 *

Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx

On Thu, May 25, 2017 at 2:25 AM, Richard Earnshaw (lists) wrote: > Having pondered this over night, I think the lowest risk thing to do, > provided it applies cleanly to the gcc-7 branch, is just commit the > entire patch on the branch and be done with it. The risk from

Re: Record equivalences for spill registers

On 05/05/2017 12:23 AM, Richard Sandiford wrote: 2017-05-05 Richard Sandiford gcc/ * lra-constraints.c (lra_copy_reg_equiv): New function. (split_reg): Use it to copy equivalence information from the original register to the spill

  1   2   3   4   5   >