[PATCH,WWWDOCS] MIPS changes for GCC 5.0

Hi Catherine, I've made a first pass at writing up the MIPS changes for GCC 5.0. Could you take a read and see what needs some more work? Thanks, Matthew Index: htdocs/gcc-5/changes.html

RE: [PATCH][4.9] PR 64569 - Backport support for MIPS binutils 2.25

Hi Jakub, I haven't done a backport to a release branch before. Could you tell me who needs to approve this change, it only affects MIPS? Thanks, Matthew -Original Message- From: Matthew Fortune Sent: 26 January 2015 16:30 To: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org) Cc

RE: [PATCH v2][MIPS] fix CRT_CALL_STATIC_FUNCTION macro

[mailto:petar.jovano...@rt-rk.com] Sent: 05 February 2015 19:28 To: gcc-patches@gcc.gnu.org; 'Maciej W. Rozycki'; Matthew Fortune Subject: [PATCH v2][MIPS] fix CRT_CALL_STATIC_FUNCTION macro v2: - add ChangeLog entry - use DLA instead of LA for n64 PTAL. Thanks. Regards, Petar --- ChangeLog

RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0

the same phrasing used where similar points are being made. I also added a comment about link compatibility for FP64. Updated text is at the end. Thanks, Matthew Thanks, Catherine -Original Message- From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] Sent: Wednesday

RE: [PATCH v2][MIPS] fix CRT_CALL_STATIC_FUNCTION macro

Maciej W. Rozycki ma...@linux-mips.org writes: On Thu, 5 Feb 2015, Matthew Fortune wrote: I'm OK with this change but I'd like Catherine to comment before committing. It seems a shame to duplicate the block of code but it is probably just as ugly to define a macro for the la/dla

RE: [PATCH v2][MIPS] fix CRT_CALL_STATIC_FUNCTION macro

Mike Stump mikest...@comcast.net writes: On Feb 6, 2015, at 4:23 AM, Maciej W. Rozycki ma...@linux-mips.org wrote: This consideration made me realise I've had a patch outstanding for some 10 years to convert all the `BAL x' instructions there to `BLTZAL $0, x'. This has always been a

RE: [MIPS] Update the ZC constraint for MIPSR6 and use it

Moore, Catherine catherine_mo...@mentor.com writes Hi Matthew, -Original Message- From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] Sent: Tuesday, January 06, 2015 7:43 AM To: Moore, Catherine Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org) Subject: [MIPS

RE: [PATCH] Allow MIPS call-saved-{4-6}.c tests to correctly run for micromips

Richard Sandiford rdsandif...@googlemail.com writes: Maciej W. Rozycki ma...@linux-mips.org writes: On Wed, 14 Jan 2015, Richard Sandiford wrote: I think we just have to accept that there are so many possible combinations that we can't test everything that's potentially relevant. I think

RE: [MIPS] Update the ZC constraint for MIPSR6 and use it

Moore, Catherine catherine_mo...@mentor.com writes: -Original Message- From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] Sent: Wednesday, January 14, 2015 2:54 PM To: Moore, Catherine Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org) Subject: RE: [MIPS] Update

RE: [PATCH, RFC] LRA subreg handling

Jeff Law l...@redhat.com writes: On 01/15/15 03:13, Robert Suchanek wrote: Robert, can you look at reload.c::reload_inner_reg_of_subreg and verify that the comment just before its return statement is effectively the situation you're in. There are certainly cases where a SUBREG needs to

RE: [RFC, PATCH][LRA, MIPS] ICE: in decompose_normal_address, at rtlanal.c:5817

OK. The MIPS and Sparc ports are probably going to hit this the hardest. So you've got a vested interest in dealing with any fallout :-) jeff That's fine. The MIPS port has been widely tested and I cross tested it on sparc-linux-gnu target so hopefully there won't any fallout.

RE: [RFC, PATCH][LRA, MIPS] ICE: in decompose_normal_address, at rtlanal.c:5817

On 2015.01.16 at 14:56 +0100, Markus Trippelsdorf wrote: On 2015.01.14 at 17:10 +, Robert Suchanek wrote: + u = v; + r = b | a[4]; + return e; + There is a missing } in the testcase. Fixed in r219740 as obvious. Thanks Markus. Sorry about that, I must have broken it

RE: [PATCH,MIPS] Only pass floating-point options to the assembler then

Moore, Catherine catherine_mo...@mentor.com writes: -Original Message- From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] Sent: Monday, January 19, 2015 5:54 PM To: Moore, Catherine Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org) Subject: RE: [PATCH,MIPS] Only

RE: [PATCH,MIPS] Only pass floating-point options to the assembler then

Hi Catherine, The new behaviour of the GCC driver passing floating point options like -msoft-float to the assembler is essential for the new o32 ABI extensions but is a change in behaviour. In particular GCC 5 used with binutils 2.24 would require a user to fix any hand-crafted code that

[PATCH,wwwdocs] Add news entry for MIPS Release 6 - committed

I committed the following patch to wwwdocs having received approval from Gerald. Thanks, Matthew Index: htdocs/index.html === RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v retrieving revision 1.953 diff -r1.953 index.html 54a55,59

RE: [MIPS] fix CRT_CALL_STATIC_FUNCTION macro

This is a follow-up to a change [1] in glibc. It fixes the issue [2] when jal can not reach a target in different region. It has been tested with DejaGnu for mips32/o32, mips64/n32 and mips64/n64. Let me know what you think. So to confirm, the issue is non-pic crt calling an init routine

RE: [PATCH] Allow MIPS call-saved-{4-6}.c tests to correctly run for micromips

/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6b73d31..1285633 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2015-01-15 Andrew Bennett andrew.benn...@imgtec.com + Matthew Fortune matthew.fort...@imgtec.com + + * gcc.target/mips/call-saved

[PATCH,committed] Ensure options incompatible with micromips imply -mno-micromips

@@ -1,3 +1,9 @@ +2015-01-15 Matthew Fortune matthew.fort...@imgtec.com + + * gcc.target/mips/mips.exp (mips-dg-options): -mips3d requires + -mno-micromips. MIPS32R1 and below require -mno-micromips. + -march=loongson* and -march=octeon* require -mno-micromips. + 2015-01-15

RE: [PATCH][4.9] PR 64569 - Backport support for MIPS binutils 2.25

Ping. Please could you advise if I can approve MIPS changes to release branches of if I need you/someone else to do so? Thanks, Matthew -Original Message- From: Matthew Fortune Sent: 07 February 2015 08:22 To: ja...@redhat.com Cc: Moore, Catherine (catherine_mo...@mentor.com); 'gcc

RE: [PATCH RFA MIPS] Prohibit vector modes in accumulators

Richard Sandiford rdsandif...@googlemail.com writes: Matthew Fortune matthew.fort...@imgtec.com writes: 2015-01-23 Robert Suchanek robert.sucha...@imgtec.com * config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit accumulators for all vector modes. This seems like

RE: [PATCH, RFC] LRA subreg handling

Richard Sandiford rdsandif...@googlemail.com writes: Jeff Law l...@redhat.com writes: On 01/15/15 03:13, Robert Suchanek wrote: Robert, can you look at reload.c::reload_inner_reg_of_subreg and verify that the comment just before its return statement is effectively the situation you're in.

[MIPS] Re-enable ABI-ISA inference

The R6 patch introduced MIPS_ISA_LEVEL_SPEC into DRIVER_SELF_SPECS for all configurations. One part of MIPS_ISA_LEVEL_SPEC is however incompatible with those configurations which infer an ISA from an ABI without specifically setting the default ISAs using --with-arch-[32|64]. I.e. a generic

[MIPS] Update the ZC constraint for MIPSR6 and use it

Update the ZC constraint for MIPSR6 to allow it to be used as the memory operand for implementations of atomic operations. Also switch the internal implementation of atomic operations to use ZC instead of ZR. This fix accurately describes the memory constraints for the LL and SC instructions.

RE: [RFC, PATCH][LRA, MIPS] ICE: in decompose_normal_address, at rtlanal.c:5817

Richard Sandiford rdsandif...@googlemail.com writes: Jeff Law l...@redhat.com writes: On 01/09/15 04:32, Robert Suchanek wrote: Hi Steven/Vladimir, It's hard to say what the correct fix should be, but it sounds like the address you get after the substitutions should be simplified

RE: [RFC, PATCH][LRA, MIPS] ICE: in decompose_normal_address, at rtlanal.c:5817

Richard Sandiford rdsandif...@googlemail.com writes: Matthew Fortune matthew.fort...@imgtec.com writes: Richard Sandiford rdsandif...@googlemail.com writes: Jeff Law l...@redhat.com writes: On 01/09/15 04:32, Robert Suchanek wrote: Hi Steven/Vladimir, It's hard to say what

[PATCH,MIPS] Add support for the R6 LSA and DLSA instructions

This patch adds support for the R6 [D]LSA instructions. The support has been structured to allow MSA (when implemented) to turn on the same instructions as they are also added by the MSA ASE. I have continued to use the idea of 'ghost' options in the testsuite to indicate what features are

[PATCH,MIPS] Only pass floating-point options to the assembler then

The new behaviour of the GCC driver passing floating point options like -msoft-float to the assembler is essential for the new o32 ABI extensions but is a change in behaviour. In particular GCC 5 used with binutils 2.24 would require a user to fix any hand-crafted code that made use of

[PATCH][4.9] PR 64569 - Backport support for MIPS binutils 2.25

This is a minimal backport of features added to GCC 5 to enable use of binutils 2.25 with GCC 4.9 for MIPS soft-float builds. Further details in the PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64569 The commits which are being backported are listed below (the last one is posted but not

RE: [MIPS] Re-enable ABI-ISA inference

Moore, Catherine catherine_mo...@mentor.com writes: gcc/ * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Only infer an ISA level from an ARCH; do not inject the default. (MIPS_DEFAULT_ISA_LEVEL_SPEC): New macro split out from MIPS_ISA_LEVEL_SPEC.

RE: [PATCH] Allow MIPS call-saved-{4-6}.c tests to correctly run for micromips

Richard Sandiford rdsandif...@googlemail.com writes: Maciej W. Rozycki ma...@linux-mips.org writes: On Tue, 13 Jan 2015, Andrew Bennett wrote: The call-saved-{4-6}.c tests in the mips testsuite fail for micromips. The reason is that micromips uses the swm and lwm instructions to

RE: [RFC, PATCH][LRA, MIPS] ICE: in decompose_normal_address, at rtlanal.c:5817

Robert Suchanek robert.sucha...@imgtec.com writes: gcc/ * simplify-rtx.c (simplify_replace_fn_rtx): Simplify (lo_sum (high x) (const (plus x offset))) to (const (plus x offset)). The fix appears valid to me. Just some comments on the test case.

[PATCH,MIPS] Remove all excess parallel constructs

I found while checking ToT test status... define_insn implicitly wraps the pattern in a parallel if there are multiple instructions. Several MIPS patterns have an explicit parallel which is mostly handled correctly but the code in 'gen_insn' does not manage to locate the clobbers inside an

RE: [Patch, MIPS] Fix PR 58158 - ICE on MIPS Loongson

Thanks for looking through and catching this. I had conflicting thoughts on whether the new condition should reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we take it that FP_CONDMOVE is the only way to get an integer conditional move based on an FP condition then that's fine.

RE: [Patch, MIPS] Fix PR 58158 - ICE on MIPS Loongson

Steve Ellcey steve.ell...@imgtec.com writes: On Mon, 2015-03-02 at 15:54 -0800, Matthew Fortune wrote: Thanks for looking through and catching this. I had conflicting thoughts on whether the new condition should reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we take

RE: [PATCH][4.9] PR 64569 - Backport support for MIPS binutils 2.25

Jakub Jelinek ja...@redhat.com writes: On Tue, Feb 17, 2015 at 08:10:37PM +, Matthew Fortune wrote: Ping. Please could you advise if I can approve MIPS changes to release branches of if I need you/someone else to do so? Any maintainer or reviewer can approve changes to the release

RE: [PATCH 6/13] mips musl support

Rich Felker dal...@libc.org writes: On Tue, Apr 21, 2015 at 01:58:02PM +, Matthew Fortune wrote: Szabolcs Nagy szabolcs.n...@arm.com writes: Set up dynamic linker name for mips. gcc/Changelog: 2015-04-16 Gregor Richards gregor.richa...@uwaterloo.ca * config/mips

RE: [PATCH 6/13] mips musl support

Szabolcs Nagy szabolcs.n...@arm.com writes: Set up dynamic linker name for mips. gcc/Changelog: 2015-04-16 Gregor Richards gregor.richa...@uwaterloo.ca * config/mips/linux.h (MUSL_DYNAMIC_LINKER): Define. I understand that mips musl is o32 only currently is that correct? There

RE: [Patch, MIPS] Minor cleanup in mips.md

2015-04-23 Steve Ellcey sell...@imgtec.com * config/mips/mips.md: (*madd4mode) Remove accum_in attribute. (*madd3mode): Ditto. (*msub4mode): Ditto. (*msub3mode): Ditto. (*nmadd4mode): Ditto. (*nmadd3mode): Ditto. (*nmadd4mode_fastmath): Ditto.

RE: [PATCH][MIPS] Enable load-load/store-store bonding

Sameera Deshpande sameera.deshpa...@imgtec.com writes: Gentle reminder! Thanks Sameera. Just a couple of comments inline below and a question for Catherine at the end. - Thanks and regards, Sameera D. On Monday 30 March 2015 04:58 PM, sameera wrote: Hi! Sorry for delay in sending

RE: [PATCH] PR 62173, re-shuffle insns for RTL loop invariant hoisting

Hi Matthew, 2015-04-21 15:24 GMT+01:00 Jiong Wang jiong.w...@arm.com: 2015-04-21 Jiong Wang jiong.w...@arm.com gcc/ * loop-invariant.c (find_defs): Enable DF_DU_CHAIN build. (vfp_const_iv): New hash table. (expensive_addr_check_p): New boolean.

RE: [Patch, MIPS] Change mips4 default processor to r10K

Steve Ellcey sell...@imgtec.com writes: This patch changes the default processor for mips4 from the r8000 to the r1. There are several reasons for this change, the main one being the difference in the r8000 madd instruction and the rest of the mips4 family. The r8000 has a fused madd

RE: [PATCH 6/13] mips musl support

H.J. Lu hjl.to...@gmail.com writes: On Mon, Apr 27, 2015 at 7:40 AM, Szabolcs Nagy szabolcs.n...@arm.com wrote: On 21/04/15 15:59, Matthew Fortune wrote: Rich Felker dal...@libc.org writes: On Tue, Apr 21, 2015 at 01:58:02PM +, Matthew Fortune wrote: There does however appear

RE: [PATCH 6/13] mips musl support

Szabolcs Nagy szabolcs.n...@arm.com writes: On 08/05/15 15:25, Matthew Fortune wrote: H.J. Lu hjl.to...@gmail.com writes: On Mon, Apr 27, 2015 at 7:40 AM, Szabolcs Nagy szabolcs.n...@arm.com wrote: On 21/04/15 15:59, Matthew Fortune wrote: Rich Felker dal...@libc.org writes

RE: [PATCH][MIPS] Enable load-load/store-store bonding

Hi Sameera, Sameera Deshpande sameera.deshpa...@imgtec.com writes: Changelog: gcc/ * config/mips/mips.md (JOIN_MODE): New mode iterator. (join2_load_StoreJOIN_MODE:mode): New pattern. (join2_loadhi): Likewise. (define_peehole2): Add peephole2 patterns to

RE: [PATCH 6/13] mips musl support

Jeff Law l...@redhat.com writes: On 05/08/2015 10:50 AM, Joseph Myers wrote: Note that however the dynamic linker does properly need to save and restore call-clobbered registers used for argument passing (because of IFUNCs, user-provided malloc, audit hooks etc. that might affect them

RE: [RFC]: Remove Mem/address type assumption in combiner

Jeff Law l...@redhat.com writes: On 05/11/2015 01:46 PM, Jeff Law wrote: On 05/11/2015 01:44 PM, Steve Ellcey wrote: On Mon, 2015-05-11 at 13:22 -0500, Segher Boessenkool wrote: Hi Steve, On Mon, May 11, 2015 at 10:50:02AM -0700, Steve Ellcey wrote: This patch broke a number of MIPS

RE: [RFC]: Remove Mem/address type assumption in combiner

Segher Boessenkool seg...@kernel.crashing.org writes: On Mon, May 11, 2015 at 08:16:41PM +, Matthew Fortune wrote: Does this patch effectively change the canonicalization rules? The following Still exists in md.texi: @item Within address computations (i.e., inside @code{mem

RE: [PATCH, MIPS]: Fix internal compiler error: in check_bool_attrs, at recog.c:2218 for micromips attribute

This patch fixes an internal compiler error when micromips/nomicromips attributes are used. The problem here was that the cached boolean attributes for the current target did not agree with the uncached attributes throwing an assertion error. It appears that saving and restoring the

RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0

Gerald Pfeifer ger...@pfeifer.com writes: On Thu, 5 Feb 2015, Matthew Fortune wrote: Thanks Catherine. Good call to remove the markup while reviewing. I've done one more pass on this to have the same phrasing used where similar points are being made. I also added a comment about link

RE: [PATCH, MIPS]: Fix internal compiler error: in check_bool_attrs, at recog.c:2218 for micromips attribute

We could add -mflip-micromips complementing -mflip-mips16 and use that for testing too. Chances are it'd reveal further issues. Looking at how -mflip-mips16 has been implemented it does not appear to me adding -mflip-micromips would be a lot of effort. I'm in favour of adding such a

RE: [Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Robert Suchanek robert.sucha...@imgtec.com writes: diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index c3755f5..976f844 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -19415,6 +19415,21 @@ mips_lra_p (void) { return mips_lra_flag; } + +/*

RE: [Patch, MIPS] Modify sysroot layout for mips-mti-* and mips-img-*

Steve Ellcey steve.ell...@imgtec.com writes: As follow-up to this patch, I forgot to include a testsuite patch to two mips specific tests that fail with the new layout. These tests are loongson specific and have includes of system headers in them. The way mips.exp in

RE: [Patch, MIPS] Enable fp-contract on MIPS and update -mfused-madd

Steve Ellcey steve.ell...@imgtec.com writes: On Wed, 2015-06-17 at 19:44 +0100, Richard Sandiford wrote: FWIW, to be specific, I think we're talking about every check except the last two in mips.md: and the one mips-ps-3d.md: In particular, the two checks in mips.c should go.

RE: [Patch, MIPS] Modify sysroot layout for mips-mti-* and mips-img-*

Hi Steve, Having worked on the new layout I of course am happy with it. I think it makes the cross compiled sysroots much easier to use for installing on a target as well as making the library paths match for cross compiled and native. A couple of minor things... diff --git

RE: [Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Hi Robert, diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index c3755f5..3c8ac30 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -19415,6 +19415,17 @@ mips_lra_p (void) { return mips_lra_flag; } + +/* Implement

RE: [PATCH] Fix mips-{mti,img}-linux-gnu boot-strap

Bernd Edlinger bernd.edlin...@hotmail.de writes: Hi,brbrthis patch fixes a regression that was triggered by commit r225260.brSee pr66747 for details.brbrIs it OK for trunk?brbrbrThanksbrBernd.br Thanks Bernd. I was just reviewing this PR. I think it will probably be safer to move the fix

RE: [PATCH] Fix mips-{mti,img}-linux-gnu boot-strap

Bernd Edlinger bernd.edlin...@hotmail.de writes: On Sat, 4 Jul 2015 09:04:41, Richard Sandiford wrote: The final return here would also mishandle SEQUENCE PATTERNs. The idea was that this function would only see real instructions, so I think instead the FOR_EACH_SUBINSN should be here:

RE: [Patch, MIPS] Enable fp-contract on MIPS and update -mfused-madd

Maciej W. Rozycki ma...@linux-mips.org writes: Richard, please have a look at my question below in a reference to your previous statement. On Thu, 18 Jun 2015, Steve Ellcey wrote: OK, I checked in the prequel patch and here is a new copy of the original patch based off of that (and with

RE: PING^3: [PATCH]: New configure options that make the compiler use -fPIE and -pie as default option

The change for MIPS looks fine by visual inspection and I've built both a default pie and default no-pie compiler. The default pie won't build glibc but I am pretty sure it is not down to this patch. I haven't had time to look into why it won't build though, something related to selecting the CRT

RE: [PATCH] MIPS: Update stack-1.c testcase to match micromips jraddiusp instruction.

Andrew Bennett andrew.benn...@imgtec.com writes: The stack-1.c testcase fails when being compiled for micromips with the -O0 optimization level. The reason is the testcase is expecting the following sequence at the end of the function: addiu $sp,$sp,16 jrc $31 But

RE: [Patch, MIPS] MIPS specific optimization for o32 ABI

Hi Steve, Overall, I don't think these optimizations are ready to include. In principle the idea looks good but it is done at the wrong point in the compiler in my opinion. The biggest concern I have is that the analysis should be possible at (or prior to) the point where the prologue/epilogue

RE: [PATCH, MIPS] Enable load/store bonding for I6400

gcc/ * config/mips/mips.h (ENABLE_LD_ST_PAIRS): Enable load/store pairs for I6400. Sorry, I missed this one. OK to commit. Thanks, Matthew

RE: [PATCH][MIPS] Fix register renaming in the interrupt handlers

I'd like to give Catherine chance to review this, I notice a couple of formatting nits in the test case: Robert Suchanek robert.sucha...@imgtec.com writes: a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c new file mode 100644

[MIPS,PATCH,committed] Fix mips.exp logic when disabling features removed in R6

When switching up from an older ISA to MIPSR6 some features need to be disabled. The support for this added in rev r225813 missed the fact that both the $isa and $isa_rev variables are referenced in this code so both must get redefined to their (potentially) new values. Without this patch a number

RE: [Patch, MIPS] MIPS specific optimization for o32 ABI

Steve Ellcey steve.ell...@imgtec.com writes: On Thu, 2015-08-13 at 02:14 -0700, Matthew Fortune wrote: Hi Steve, Overall, I don't think these optimizations are ready to include. In principle the idea looks good but it is done at the wrong point in the compiler in my opinion

RE: [PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Richard Sandiford rdsandif...@googlemail.com writes: Robert Suchanek robert.sucha...@imgtec.com writes: The patch below disables generation of the branch likely instructions for -Os but only for generic architecture. The branch likely may result in some code size reduction but the cost

RE: [PATCH, MIPS] Remove W32 and W64 pseudo-processors

Robert Suchanek robert.sucha...@imgtec.com writes: gcc/ * config/mips/mips.c (mips_rtx_cost_data): Remove costs for W32 and W64 pseudo-processors. * config/mips/mips.md (processor): Remove w32 and w64. OK, thanks. Matthew

[PATCH, MIPS] Compact branch support for MIPS32R6/MIPS64R6

A full range of 'compact' branch instructions were introduced to MIPS as part of Release 6. The compact term is used to identify the fact that these do not have a delay slot. http://imgtec.com/mips/architectures/mips64/ The one subtlety of compact branches is that while they do not have a delay

RE: [PATCH] MIPS: Prevent the p5600-bonding.c test from being run for the n32 and 64 ABIs

Andrew Bennett andrew.benn...@imgtec.com writes: diff --git a/gcc/testsuite/gcc.target/mips/p5600-bonding.c b/gcc/testsuite/gcc.target/mips/p5600-bonding.c index 0890ffa..20c26ca 100644 --- a/gcc/testsuite/gcc.target/mips/p5600-bonding.c +++ b/gcc/testsuite/gcc.target/mips/p5600-bonding.c @@

RE: [PATCH, MIPS] Fix restoration of hi/lo in MIPS64R2 interrupt handlers

Robert Suchanek robert.sucha...@imgtec.com writes: Hi Robert, The patch is OK, but will you please name the test something other than the date? OK. I'll change it to interrupt_handler-5.c, add a comment and commit after approval for the new interrupt handler options. I believe this

RE: [PATCH, MIPS] Scheduling for M51xx core family

Richard Sandiford rdsandif...@googlemail.com writes: Robert Suchanek robert.sucha...@imgtec.com writes: @@ -771,7 +771,8 @@ struct mips_cpu_info { /* Infer a -mnan=2008 setting from a -mips argument. */ #define MIPS_ISA_NAN2008_SPEC \ - %{mnan*:;mips32r6|mips64r6:-mnan=2008} +

RE: [PATCH, MIPS] Scheduling for M51xx core family

Robert Suchanek robert.sucha...@imgtec.com writes. 2015-07-16 Prachi Godbole prachi.godb...@imgtec.com gcc/ * config/mips/m5100.md: New file. * config/mips/mips-cpus.def (m5100, m5101): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c

RE: [PATCH, MIPS] I6400 scheduling

Robert Suchanek robert.sucha...@imgtec.com writes: 2015-07-16 Prachi Godbole prachi.godb...@imgtec.com gcc/ * config/mips/i6400.md: New file. * config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400. (mips64r6): Likewise. (i6400): Define. *

RE: [RFA] Compact EH Patch

> This patch implements a more compact format for exception handling data. > Although I don't > have recent numbers for the amount of compression achieved, an earlier > measurement showed > a 30% reduction in the size of EH data for libstdc++. > > A design document detailing the new format is

RE: [PATCH, mips]: Use ROUND_UP and ROUND_DOWN macros

Uros Bizjak writes: > Fairly trivial patch that introduces no functional changes. > > * config/mips/mips.h (MIPS_STACK_ALIGN): Implement using > ROUND_UP macro. > * config/mips/mips.c (mips_setup_incoming_varargs): Use > ROUND_DOWN to calculate off. >

RE: [PATCH, MIPS] Frame header optimization for MIPS O32 ABI

Moore, Catherine writes: > The patch itself looks good, but the tests that you added need a little more > work. > > I tested with the mips-sde-elf-lite configuration and I'm seeing failures for > many > options. The main failure mode seems to be that the stack is

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Next batch of comments. This set covers the rest of mips-msa.md. >+++ b/gcc/config/mips/mips-msa.md >+(define_expand "vec_perm" >+ [(match_operand:MSA 0 "register_operand") >+ (match_operand:MSA 1 "register_operand") >+ (match_operand:MSA 2 "register_operand") >+

RE: [PATCH] MIPS: Correctly update the isa and arch_test_option_p variables after the arch dependency handling code in mips.exp

Andrew Bennett andrew.benn...@imgtec.com writes: I have noticed that in the mips.exp dg-option handling code the isa and arch_test_option_p variables are not updated after the pre-arch to arch dependency handling. This means that if this code changes the architecture the post-arch dependency

RE: [Patch, MIPS] Fix SYSROOT_SUFFIX_SPEC for mips-mti-linux-gnu

2015-07-09 Steve Ellcey sell...@imgtec.com * config/mips/mti-linux.h (MIPS_SYSVERSION_SPEC): Update to handle mips[32|64]r3 and mips[32|64]r5. OK, thanks. Matthew

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, I'm taking small steps at this review. I did the first few files as below. mips-msa.md is next so don't expect the it quickly. I might do that in pieces too. No need to post an updated patch until I'm all the way through but I'd appreciate an explicit ok/done to each point or

RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.

Moore, Catherine catherine_mo...@mentor.com writes: The recent changes to the MIPS GCC Linux sysroot (https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01014.html) have meant that the include directory is now not global and is provided only for each multi-lib configuration. This means that

RE: [PATCH, MIPS] Compact branch support for MIPS32R6/MIPS64R6

Moore, Catherine <catherine_mo...@mentor.com> writes: > Hi Matthew: > > > -Original Message- > > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] > > Sent: Monday, August 17, 2015 6:47 PM > > To: Moore, Catherine; 'gcc-patches@gcc.gnu.org' (

RE: [PATCH] [MIPS] Fix wrong instruction in the delay slot

Robert Suchanek > IMO, the fix is to recognize the empty basic block that has a code_label > followed by a barrier (ignoring notes and debug_insns), forbid going > beyond the barrier if the empty block is found in > skip_consecutive_labels () and

RE: [PATCH, MIPS] Frame header optimization for MIPS O32 ABI

Steve Ellcey writes: > Here is an update of my MIPS frame header optimization patch. This is > actually only one part of the patch but I would like to get this approved > and checked in before proceeding with the second half. > > The O32 ABI on MIPS requires that

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Next batch of comments for this patch. I've covered mips-msa.md up to the copy patterns and one supporting function from mips.c. >+++ b/gcc/config/mips/mips-msa.md >+;; The attribute gives half modes for vector modes. >+(define_mode_attr VHMODE >+ [(V8HI "V16QI") >+ (V4SI "V8HI")

RE: [PATCH 2/4] [MIPS] Add pipeline description for MSA

> gcc/ChangeLog: > > * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic) > (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, > i6400_fpu_store) > (i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l) > (i6400_fpu_mult): New cpu units. >

RE: [PATCH] Fix undefined behaviour in mips port

Jeff Law writes: > Another instance of left shifting a negative value. Fixed in an obvious > way. Verified all the mips configurations in config-list.mk build now > using a trunk compiler. > > Installed on the trunk, Thanks Jeff. Matthew

RE: [PATCH] MIPS/GCC/doc: Reorder `-mcompact-branches='

Maciej Rozycki writes: > Move the `-mcompact-branches=' option out of the middle of a block of > floating-point options. The option is not related to FP in any way. > Place it immediately below other branch instruction selection options. > > gcc/ > *

RE: [Patch, MIPS] Remove definition of TARGET_PROMOTE_PROTOTYPES

Steve Ellcey writes: > On Tue, 2015-11-10 at 15:57 -0800, Steve Ellcey wrote: > > 2015-11-10 Steve Ellcey > > > > * config/mips/mips.c (mips_promote_function_mode): New function. > > (TARGET_PROMOTE_FUNCTION_MODE): Define as above function.

RE: [PATHCH] Disable inline asm for in-tree mpfr (PR69134)

Bernd Edlinger writes: > an in-tree mpfr build enables inline asm code, which makes the mips-bootstrap > fail, > because at least mpfr 2.4.2 uses the "=h" constraint but in > config/mips/constraints.md > we find: "Formerly the @code{hi} register. This constraint is

RE: [PATCH] Fix pr69012 ICE on building libgfortran for mips

Bernd Edlinger writes: > Hi, > > On 30.12.2015 15:31, Richard Sandiford wrote: > > I think the problem is deeper than that though. The instructions that > > are triggering the ICE are only generated by the prologue, so this > > means that we're trying to lay out the

RE: [PATCH][MIPS] Reorder function types

Robert Suchanek writes: > gcc/ > * config/mips/mips-ftypes.def: Sort to lexicographical order. The patch is fine. I don't know what we can/should commit at this stage. Catherine: Any idea what is acceptable? I'd think this kind of small change to be OK and make

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Robert, Thanks for the update and detailed comments. There are a couple of things which I think still need addressing based solely on your comments but generally the changes seem to have simplified things which is nice to see. I haven't read the patch again yet and given the changes it looks

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

Hi Robert, Do you have an updated version of this patch? It no longer applies cleanly. Thanks, Matthew > -Original Message- > From: Robert Suchanek > Sent: 05 January 2016 16:17 > To: catherine_mo...@mentor.com; Matthew Fortune > Cc: gcc-patches@gcc.gnu.org > Subje

RE: [PATCH][MIPS] Migrate reduction optabs in mips-ps-3d.md

Alan Lawrence writes: > On 07/01/16 12:47, Alan Lawrence wrote: > > Here's an updated version, also covering the min/max patterns I missed > before. > > I've now managed to do some testing with a stage 1 compiler, by > > compiling all tests in gcc.dg/vect at -O2

[PATCH] Fix FFI return type for closures in the java interpreter

Hi, I've identified a latent bug in the java interpreter that affects MIPS n32 and n64 ABIs both little and big endian and, I presume, any 64-bit big endian target with int as 32-bit. A full description is in my original post: https://gcc.gnu.org/ml/java-patches/2016-q2/msg00020.html Patch

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

ent: 10 August 2015 13:15 > > To: catherine_mo...@mentor.com; Matthew Fortune > > Cc: gcc-patches@gcc.gnu.org > > Subject: [PATCH 3/4] Add support to run auto-vectorization tests for > > multiple > > effective targets > > > > Hi, > > > > Th

RE: Remove -fshort-double (PR60410)

Jeff Law writes: > On 02/05/2016 12:31 PM, Bernd Schmidt wrote: > > This patch fixes PR60410 by removing -fshort-double. Nick earlier > > propsed a fix for the crash, but Richard B suggested removing the option > > entirely, and I'd agree with that. It's a pointless ABI-changing

RE: [Patch, MIPS] Patch for PR 68400, a mips16 bug

Richard Sandiford writes: > "Steve Ellcey " writes: > > Here is a patch for PR6400. The problem is that and_operands_ok was > > checking > > one operand to see if it was a memory_operand but MIPS16 addressing is more > > restrictive than what the

RE: [Patch, MIPS] Patch for PR 68273 (user aligned variable arguments)

Steve Ellcey writes: > Here is a new patch for PR 68273. The original problem with gsoap has > been fixed by changing GCC to not create overly-aligned variables in > the SRA pass but the MIPS specific problem of how user-aligned variables > are passed to functions remains. >

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