Re: [PATCH][AArch64] Canonicalize Cortex core tunings

On 29/06/16 18:03, Wilco Dijkstra wrote: > This patch sets the branch cost to the same most optimal setting for all > Cortex cores, > reducing codesize and improving performance due to using more CSEL > instructions. > Set the autoprefetcher model in Cortex-A72 to weak like the others. Enable

Re: [PATCH][AArch64] Fix some scan-assembler tests for -mabi=ilp32

On 29/06/16 11:47, James Greenhalgh wrote: > On Wed, Jun 29, 2016 at 11:40:13AM +0100, Kyrill Tkachov wrote: >> Hi all, >> >> I notice these scan-assembler tests fail when testing -mabi=ilp32 because the >> 64-bit operation that they expect doesn't happen on the 32-bit long types in >> that

Re: [PATCH][AArch64] Fix some scan-assembler tests for -mabi=ilp32

On 29/06/16 11:40, Kyrill Tkachov wrote: > Hi all, > > I notice these scan-assembler tests fail when testing -mabi=ilp32 > because the 64-bit operation that they > expect doesn't happen on the 32-bit long types in that configuration. > > The easy fix is to change the 'long' types to be 'long

Re: [AArch64] ARMv8.2 command line and feature macros support

On 29/06/16 09:43, James Greenhalgh wrote: > On Mon, Jun 27, 2016 at 03:58:00PM +0100, Jiong Wang wrote: >> On 07/06/16 09:46, Jiong Wang wrote: >>> 2016-06-07 Matthew Wahab >>>Jiong Wang >>> >>>* config/aarch64/aarch64-arches.def:

Re: [PATCH][ARM] Fix gcc.target/arm/builtin-bswap16-1.c

On 03/06/16 09:30, Kyrill Tkachov wrote: > Hi all, > > The test gcc.target/arm/builtin-bswap16-1.c refuses to compile when > testing a toolchain configured with > --with-mode=thumb --with-float=hard and an architecture that supports > Thumb2. > This is because the test explicitly sets the -march

Re: [AArch64] Give some new costs for Cortex-A53 floating-point operations

On 20/06/16 14:57, James Greenhalgh wrote: > > Hi, > > As recently done for Cortex-A57 [1], this patch rebases the floating-point > cost table for Cortex-A53 to be relative to the cost of a floating-point move. > I wrote a little more on the justification for doing this in the other patch, > but

Re: [Patch AArch64] Add some more missing intrinsics

On 13/06/16 17:31, James Greenhalgh wrote: > > Hi, > > Inspired by Jiong's recent work, here are some more missing intrinsics, > and a smoke test for each of them. > > This patch covers: > > vcvt_n_f64_s64 > vcvt_n_f64_u64 > vcvt_n_s64_f64 > vcvt_n_u64_f64 > vcvt_f64_s64 >

Re: [Patch AArch64] Fixup to fcvt patterns added in r237200

On 10/06/16 13:29, James Greenhalgh wrote: > > Hi, > > My autotester picked up some issues with the vcvt{ds}_n_* intrinsics > added in r237200. > > The iterators in this pattern do not resolve, as they have not been > explicitly tied to the mode iterator (rather than the code iterator) > used

Re: [AArch64] Give some new costs for Cortex-A57 floating-point operations

On 03/06/16 09:35, James Greenhalgh wrote: > > Hi, > > This patch rebases the floating-point cost table for Cortex-A57 to be > relative to the cost of a floating-point move. This in response to this > feedback from Richard Sandiford [2] on Ramana's patch to calls.c [1] from > 2014: > > I

Re: [PATCH][ARM] Add mode to probe_stack set operands

On 03/05/16 12:27, Kyrill Tkachov wrote: > Hi all, > > When building the arm backend genrecog complains that the probe_stack > set expression > doesn't specify any modes. This patch adds the SI mode annotation and > fixes the warning > > Bootstrapped and tested on arm-none-linux-gnueabihf. > >

Re: [PATCH][ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsls-imm Thumb2 peepholes

On 11/04/16 14:27, Kyrill Tkachov wrote: > > On 08/04/16 10:30, Richard Earnshaw (lists) wrote: >> On 07/04/16 15:51, Kyrill Tkachov wrote: >>> Hi all, >>> >>> In this wrong-code PR we have a Thumb2 peephole transforming: >>> tst

Re: [Patch AArch64 0/3] Fix PR70133

On 06/04/16 11:10, James Greenhalgh wrote: > Hi, > > This patch set fixes PR70133, which is a bug in the way we handle extension > strings after using -march or -mcpu=native. In investigating this, I found > other bugs in the way we communicate architceture intention between the > compiler and

Re: [PATCH][ARM][RFC] PR target/65578 Fix gcc.dg/torture/stackalign/builtin-apply-4.c for single-precision fpus

On 09/02/16 17:21, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR the builtin-apply-4.c test fails with -flto but > only when targeting an fpu > with only single-precision capabilities. > > bar is a function returing a double. For non-LTO compilation the caller > of bar reads the

Re: [PATCH][ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsls-imm Thumb2 peepholes

On 07/04/16 15:51, Kyrill Tkachov wrote: > Hi all, > > In this wrong-code PR we have a Thumb2 peephole transforming: > tstr3, #2 > bne.L3 > beq.L6 > > into: > lslsr3, r3, #30 // LSLS is shorter than TST in Thumb2 > bmi.L3 > beq.L6 > > that is,

Re: [PATCH][ARM] Add deprecation warning on pre-v4t architecture revisions

On 01/03/16 16:17, Kyrill Tkachov wrote: > Hi all, > > For GCC 6 we want to deprecate architecture revisions prior to ARMv4T. > This patch implements this by documenting the deprecation in invoke.texi > and adding > a warning whenever the user specifies an -march or -mcpu option that > selects

Re: [AArch64] Disable pcrelative_literal_loads with fix-cortex-a53-843419

On 14/03/16 15:34, Christophe Lyon wrote: > On 10 March 2016 at 14:24, James Greenhalgh wrote: >> On Thu, Mar 10, 2016 at 01:37:50PM +0100, Christophe Lyon wrote: >>> On 10 March 2016 at 12:43, James Greenhalgh >>> wrote: On Tue, Jan 26,

Re: [PATCH][ARM] PR target/70008

hat's something like: register_operand (op) || (TARGET_ARM && arm_immediate_operand (op)) R. > On 02/29/2016 08:29 AM, Richard Earnshaw (lists) wrote: >> On 29/02/16 11:21, Michael Collison wrote: >>> >>> On 2/29/2016 4:06 AM, Kyrill Tkachov wrote: >>>>

Re: [PATCH][ARM] PR target/70014

On 01/03/16 17:33, Michael Collison wrote: > This patches addresses PR 70014, where the predicates and operand do not > match and could cause problems with the register allocator. Tested > successfully on > > arm-none-linux-gnueabi > arm-none-linux-gnuabihf > armeb-none-linux-gnuabihf >

Re: [PATCH] Fix PR69951

On 01/03/16 10:49, Richard Biener wrote: > On Tue, 1 Mar 2016, Ramana Radhakrishnan wrote: > >> >> >> On 01/03/16 09:54, Richard Biener wrote: >>> On Tue, 1 Mar 2016, James Greenhalgh wrote: >>> On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote: > On Mon, 29 Feb 2016, James

Re: [PATCH][ARM] PR target/70008

On 29/02/16 11:21, Michael Collison wrote: > > > On 2/29/2016 4:06 AM, Kyrill Tkachov wrote: >> Hi Michael, >> >> On 29/02/16 04:47, Michael Collison wrote: >>> This patches address PR 70008, where a reverse subtract with carry >>> instruction can be generated in thumb2 mode. It was tested with

Re: [PATCH][ARM][wwwdocs] Mention Cortex-A32 and Cortex-A35 support in changes.html for GCC 6

On 26/02/16 14:25, Kyrill Tkachov wrote: > Hi all, > > This patch adds a note to changes.html about the added support for > Cortex-A32 and Cortex-A35. > > Ok to commit? > OK. R. > Thanks, > Kyrill > > wwwdocs-a32-a35.patch > > > Index: htdocs/gcc-6/changes.html >

Re: [WWWDocs] Deprecate support for non-thumb ARM devices

On 24/02/16 13:59, Richard Earnshaw (lists) wrote: > After discussion with the ARM port maintainers we have decided that now > is probably the right time to deprecate support for versions of the ARM > Architecture prior to ARMv4t. This will allow us to clean up some of > the cod

Re: [WWWDocs] Deprecate support for non-thumb ARM devices

On 25/02/16 14:15, David Brown wrote: > On 25/02/16 14:32, Stefan Ring wrote: >> On Thu, Feb 25, 2016 at 10:20 AM, Richard Earnshaw (lists) >> <richard.earns...@arm.com> wrote: >>> The point is to permit the compiler to use interworking compatible >>> seq

Re: [WWWDocs] Deprecate support for non-thumb ARM devices

On 25/02/16 13:32, Stefan Ring wrote: > On Thu, Feb 25, 2016 at 10:20 AM, Richard Earnshaw (lists) > <richard.earns...@arm.com> wrote: >> The point is to permit the compiler to use interworking compatible >> sequences of code when generating ARM code, not to force us

Re: [WWWDocs] Deprecate support for non-thumb ARM devices

On 24/02/16 17:38, Joseph Myers wrote: > On Wed, 24 Feb 2016, Richard Earnshaw (lists) wrote: > >> After discussion with the ARM port maintainers we have decided that now >> is probably the right time to deprecate support for versions of the ARM >> Architecture prior to

[WWWDocs] Deprecate support for non-thumb ARM devices

After discussion with the ARM port maintainers we have decided that now is probably the right time to deprecate support for versions of the ARM Architecture prior to ARMv4t. This will allow us to clean up some of the code base going forwards by being able to assume: - Presence of half-word data

Re: [PATCH][ARM] Add initial support for the Cortex-A32

On 24/02/16 10:49, Kyrill Tkachov wrote: > Hi all, > > This patch adds initial support for the Cortex-A32 core. > It is an ARMv8-A core and this patch enables the -mcpu=cortex-a32 and > -mtune=cortex-a32 options. > > The initial tunings are set to the same parameters as for Cortex-A35. > >

Re: [PATCH ARM] RFC: PR69770 -mlong-calls does not affect calls to __gnu_mcount_nc generated by -pg

On 12/02/16 14:56, Charles Baylis wrote: > When compiling with -mlong-calls and -pg, calls to the __gnu_mcount_nc > function are not generated as long calls. > > This is encountered when building an allyesconfig Linux kernel because > the Linux build system generates very large sections by

Re: [PATCH] Fix aarch64 bootstrap (pr69416)

On 22/01/16 17:07, Richard Henderson wrote: > The bare CONST_INT inside the CCmode IF_THEN_ELSE is causing combine to > make incorrect simplifications. At this stage it feels safer to wrap > the CONST_INT inside of an UNSPEC than make more generic changes to > combine. > > But we should

Re: [aarch64] Fix target/69176

> +(define_constraint "Upl" > + "A constraint that matches two uses of add instructions." That's not a particularly helpful description for external users of the compiler. I think that either needs to be sufficiently precise that people who understand the ISA but not the guts of GCC can use it,

Re: [trans-mem, aa64, arm, ppc, s390] Fixing PR68964

On 12/01/16 16:53, Richard Henderson wrote: > The problem in this PR is that we never got around to flushing out the vector > support for transactions for anything but x86. My goal here is to make this > as > generic as possible, so that it should Just Work with existing vector support > in the

Re: [4.9][PR69082]Backport "[PATCH][ARM]Tighten the conditions for arm_movw, arm_movt"

On 12/01/16 15:31, Renlin Li wrote: > Hi all, > > Here I backport r227129 to branch 4.9 to fix exactly the same issue > reported in PR69082. > It's been already committed on trunk and backportted to branch 5. > > > I have quoted the original message for the explanation. > The patch applies to

Re: [trans-mem, aa64, arm, ppc, s390] Fixing PR68964

On 12/01/16 17:16, Richard Earnshaw (lists) wrote: > On 12/01/16 16:53, Richard Henderson wrote: >> The problem in this PR is that we never got around to flushing out the vector >> support for transactions for anything but x86. My goal here is to make this >> as >&

Re: [PATCH] Fix PR68707

On 08/01/16 11:45, Richard Biener wrote: > On Fri, 8 Jan 2016, Alan Lawrence wrote: > >> Here's an alternative patch, using the hunk from >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68707#c16, which 'improves' >> (heh, >> we think) on the previous by allowing SLP to proceed where the loads

Re: [PATCH, testsuite] Fix g++.dg/pr67989.C test failure when running with -march or -mcpu

On 07/01/16 09:15, Kyrill Tkachov wrote: > > On 07/01/16 07:34, Thomas Preud'homme wrote: >> On Tuesday, January 05, 2016 10:47:38 AM Kyrill Tkachov wrote: >>> Hi Thomas, >> Hi Kyrill, >> diff --git a/gcc/testsuite/g++.dg/pr67989.C b/gcc/testsuite/g++.dg/pr67989.C index

Re: [patch] ARM FreeBSD fix bootstrap

On 05/01/16 21:03, Andreas Tobler wrote: > On 05.01.16 11:32, Richard Earnshaw (lists) wrote: >> On 23/12/15 19:28, Andreas Tobler wrote: > >>> 2015-12-23 Andreas Tobler <andre...@gcc.gnu.org> >>> >>> * config/arm

Re: [patch] ARM FreeBSD fix bootstrap

On 23/12/15 19:28, Andreas Tobler wrote: > On 23.12.15 11:22, Richard Earnshaw (lists) wrote: >> On 22/12/15 19:53, Andreas Tobler wrote: >>> Hi all, >>> >>> the commit for PR68617 broke boostrap on armv6*-*-freebsd*. >>> >>> We st

Re: [PATCH, testsuite] Fix g++.dg/pr67989.C test failure when running with -march or -mcpu

On 05/01/16 10:47, Kyrill Tkachov wrote: > Hi Thomas, > > On 05/01/16 07:37, Thomas Preud'homme wrote: >> Hi, >> >> g++.dg/pr67989.C passes -march=armv4t to gcc when compiling which >> fails if >> RUNTESTFLAGS passes -mcpu or -march with a different value. This patch >> adds a >> dg-skip-if

Re: [patch] ARM FreeBSD fix bootstrap

On 22/12/15 19:53, Andreas Tobler wrote: > Hi all, > > the commit for PR68617 broke boostrap on armv6*-*-freebsd*. > > We still have unaligned_access = 0 on armv6 here on FreeBSD. > > The commit from the above PR overrides my SUBTARGET_OVERRIDE_OPTIONS I > called in arm_option_override. And it

Re: [ARM] Fix ICE on Ada code with -mbig-endian -mhard-float

On 21/12/15 16:24, Eric Botcazou wrote: > Hi, > > the attached Ada testcase triggers an ICE with -mbig-endian -mhard-float: > > eric@polaris:~/build/gcc/arm-linux-gnueabi> gcc/xgcc -Bgcc -S p.adb -I > gcc/ada/rts -mbig-endian -mhard-float > +===GNAT BUG

Re: [Patch testsuite] Skip gcc.dg/ifcvt-4.c for targets on which it may not work

On 21/12/15 19:38, Jeff Law wrote: > On 12/18/2015 02:55 AM, James Greenhalgh wrote: >> This is a multi-part message in MIME format. >> --2.2.0.1.gd394abb.dirty >> Content-Type: text/plain; charset=UTF-8; format=fixed >> Content-Transfer-Encoding: 8bit >> >> >> Hi, >> >> PR68232 is a

Re: [PATCH/AARCH64] Fix -mcpu/arch=native support for LSE

On 11/12/15 19:54, Andrew Pinski wrote: > Hi, > The Linux kernel calls lse as atomics in /proc/cpuinfo. We should > change aarch64-option-extensions.def to take that into account. > > OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions > and tested with -mcpu=native on

Re: [PATCH 2/4][AArch64] Increase the loop peeling limit

On 15/12/15 23:34, Evandro Menezes wrote: > On 12/14/2015 05:26 AM, James Greenhalgh wrote: >> On Thu, Dec 03, 2015 at 03:07:43PM -0600, Evandro Menezes wrote: >>> On 11/20/2015 05:53 AM, James Greenhalgh wrote: On Thu, Nov 19, 2015 at 04:04:41PM -0600, Evandro Menezes wrote: > On

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