Re: [PATCH V2] RISC-V: Support highest-number regno overlap for widen ternary

LGTM. Regards Robin

Re: [PATCH] RISC-V: Fix incorrect LCM delete bug [VSETVL PASS]

The non-test parts are OK IMHO. Regards Robin

Re: [PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines

LGTM, thanks. Regards Robin

Re: [PATCH V3 2/4] RISC-V: Add vector related pipelines

Thanks, that looks better IMHO. > +;; Copyright (C) 2011-2024 Free Software Foundation, Inc. > +;; Contributed by Andrew Waterman (and...@sifive.com). > +;; Based on MIPS target for GNU compiler. You might want to change that, as well as the date. While at it you can also fix the broken date in

Re: [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling

> Use default cost model scheduling on these test cases. All these tests > introduce scan dump failures with -mtune generic-ooo. Since the vector > cost models are the same across all three tunes, some of the tests > in PR113249 will be fixed with this patch series. This is OK, thanks. > 39

Re: [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation

>/* If we ever encounter an insn without an insn reservation, trip > an assert so we can find and fix this problem. */ > -#if 0 > + if (! insn_has_dfa_reservation_p (insn)) { > +print_rtl(stderr, insn); > +fprintf(stderr, "%d", get_attr_type (insn)); > + } >gcc_assert

Re: [PATCH V4 2/4] RISC-V: Add vector related pipelines

LGTM, thanks. Regards Robin

Re: [PATCH] RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS

> +static bool > +vsetvl_pre_insn_p (rtx_insn *rinsn) > +{ > + return recog_memoized (rinsn) >= 0 > + && get_attr_type (rinsn) == TYPE_VSETVL_PRE; > +} Indent looks off on my screen. Can you check? Apart from that LGTM (no need for v2 of course). Regards Robin

Re: [PATCH] RISC-V: Fix regressions due to 86de9b66480b710202a2898cf513db105d8c432f

Hi Juzhe, in principle this seems ok to me but I wonder about: > We shouldn't worry about subreg:...VL_REGNUM since it's impossible > that we can have such situation, I think we allow this in legitimize_move for situations like (subreg:SI (reg:V4QI)). That was not added for correctness but

Re: [PATCH] RISC-V: Fix VSETLV PASS compile-time issue

LGTM. Regards Robin

[PATCH] match: Fix vcond into conditional op folding [PR113607].

Hi, in PR113607 we see an invalid fold of _429 = .COND_SHL (mask_patt_205.47_276, vect_cst__262, vect_cst__262, { 0, ... }); vect_prephitmp_129.51_282 = _429; vect_iftmp.55_287 = VEC_COND_EXPR ; to Applying pattern match.pd:9607, gimple-match-10.cc:3817 gimple_simplified to

Re: [PATCH] RISC-V: Support scheduling for sifive p600 series

> + NULL, /* vector cost */ > +}; Does the P600 series include a vector unit? From what I found on the web it looks like it. If so I would suggest specifying at least the default (generic) vector cost model here. We fall back to the default one for

[PATCH] genopinit: Split init_all_optabs [PR113575]

Hi, init_all_optabs initializes > 1 patterns for riscv targets. This leads to pathological situations in dataflow analysis (which can occur with many adjacent stores). To alleviate this this patch makes genopinit split the init_all_optabs function into several init_optabs_xx functions that

Re: [PATCH] RISC-V: Fix regressions due to 86de9b66480b710202a2898cf513db105d8c432f

> No, we didn't undo the optimization. > > We just disallow move pattern for (set (reg) (VL_REGNUM)). Ah, what I referred to was the opposite direction. We allow (subreg:V8QI (reg:DI ...)) which is not touched by this patch. Then it is OK. Regards Robin

Re: [PATCH] RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x

LGTM. Regards Robin

Re: [PATCH V3 2/4] RISC-V: Add vector related pipelines

> I think removing the is_inorder attribute should be ok. I added it > because I wanted to avoid having two matching insn reservations > defined since matching solely on the type attribute should also match > on all subsets as well (i.e. if eventually we add an insn reservation > checking for type

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

> Looks wrong. Recover back. When we demote we use two elements where there was one before. Therefore the vector needs to be able to hold twice as many elements. We adjust vl correctly but the mode is not here. Regards Robin

Re: [PATCH] RISC-V: Support trailing vec_init optimization

Hi Juzhe, thanks, LGTM as it is just a refinement of what we already have. Regards Robin

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

On 11/15/23 15:29, 钟居哲 wrote: > Could you show me the example ? > > It's used by handling SEW = 64 on RV32. I don't know why this patch touch > this code. Use gather_load_run-1.c with the 64-bit index patterns disabled on rv32. We insert (mem:DI (reg:SI)) into a vector so use the SEW = 64

Re: [PATCH] RISC-V Regression: Remove scalable compile option

LGTM. Regards Robin

Re: [BUG FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

LGTM. I prefer that over the iterator. Regards Robin

[PATCH] RISC-V: testsuite: Do not set default arch for RVV.

Hi, as per recent discussion and in order to fix inconsistencies between spike and qemu this patch removes gcc_march and gcc_mabi arguments from the default CFLAGS in the testsuite invocation for some sub directories. Juzhe reported that this helps for him. Regards Robin

[PATCH] RISC-V: testsuite: Add rv64 requirement for bug-9 and bug-14.

Hi, this adds an effective target requirement to compile the tests. Since we disabled 64-bit indices on rv32 targets those tests should be unsupported on rv32. Regards Robin gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/bug-14.C: Add dg-require-effective-target rv64.

[PATCH] RISC-V: testsuite: Fix popcount test.

Hi, since Jakub's recent middle-end changes we vectorize more popcount instances. This patch just adjusts the dump check. Going to commit as obvious once I have figured out why there is a dump difference between my local tester and on the server. Regards Robin gcc/testsuite/ChangeLog:

Re: [PATCH] RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice

Hi Juzhe, > csrra4,vlenb > csrra5,vlenb Totally unrelated to this patch but this looks odd. I don't remember if we had a patch for this already at some point. In general the idea for the patch is to use the largest vector element mode for the indices and compress several of

Re: [PATCH] vect: Use statement vectype for conditional mask.

> But note you can explicitly specify a vector type as well, there's an > overload for it, so we can fix the "invariant" case with the following > (OK if you can test this on relevant targets) > > diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc > index 3f59139cb01..936a3de9534 100644 >

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> So, going back to our testcases that reported errors with this, I > don't think we should explicitly specify -march and -mabi when > compiling a runnable program, but use the defaults (--with-arch). > Most of our current runnable testcases adhere to this convention, > except for the ones we

Re: [PATCH] vect: Use statement vectype for conditional mask.

> Yes, your version is also OK. The attached was bootstrapped and regtested on aarch64, x86 and regtested on riscv. Going to commit it later unless somebody objects. Regards Robin Subject: [PATCH] vect: Pass truth type to vect_get_vec_defs. For conditional operations the mask is loop

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

> OK. Make sense。 I'm wondering whether the VLA modes in the iterator are correct. Looks dubious to me but unsure, will need to create some tests before continuing. > LGTM as long as you remove  all > GET_MODE_BITSIZE (GET_MODE_INNER (mode)) <= GET_MODE_BITSIZE (Pmode) What's the problem with

Re: [PATCH] vect: Use statement vectype for conditional mask.

> For the fortran testcase we don't even run into this but hit an > internal def and assert on > > gcc_assert (STMT_VINFO_VEC_STMTS (def_stmt_info).length () == ncopies); > > I think this shows missing handling of .COND_* in the bool pattern recognition > as we get the 'bool' condition as

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

> It must be correct. We already have test (intrinsic codes) for it. Yeah, just noticed that myself. Anyway will do some more tests, maybe my initial VLS analysis was somehow flawed. > Condition should be put into iterators (Add a new iterator for > indexed load store). Ah, that's what you

Re: [PATCH] vect: Use statement vectype for conditional mask.

> No, you shouldn't place _7 != 0 inside the .COND_ADD but instead > have an extra pattern stmt producing that so > > patt_8 = _7 != 0; > patt_9 = .COND_ADD (patt_8, ...); > > that's probably still not enough, but I always quickly forget how > bool patterns work ... basically a comparison like

[PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Hi, this patch enhances the equality check for REG_EQUAL notes in the vsetvl pass. Currently, we assume that two such notes describe the same value when they have the same rtx representation. This is not true when either of the note's source operands is modified by an insn between the two

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

> Does this patch fixes exposed bugs in current tests? > Or could you add test for it ? Ah, yes forgot to mention. This fixes several tests when testing with -march=rv64gcv_zbb. Regards Robin

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> FAIL: gcc.target/riscv/rvv/autovec/slp-mask-run-1.c -O3 -ftree-vectorize > (test for excess errors) > FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c -std=c99 -O3 > -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for > excess errors) > FAIL:

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> xgcc: fatal error: Cannot find suitable multilib set for > '-march=rv32imafdcv_zicsr_zifencei_zfh_zfhmin_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b'/'-mabi=ilp32d'^M > compilation terminated.^M > compiler exited with status 1 > FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 10:38, juzhe.zh...@rivai.ai wrote: > For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout > the entire function, and could validly be replaced in all its > occurrences by @var{op}.  (``Validly'' here refers to the data flow of > the program; simple replacement may

Re: [PATCH V2] RISC-V: Optimize combine sequence by merge approach

Hi Juzhe, LGTM apart from: > + int64_t a = -1789089.23423; > + int64_t b = -8916156.45644; What's that? :) Doesn't really matter of course but please change to a proper integer. OK with that changed. Regards Robin

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 09:25, juzhe.zh...@rivai.ai wrote: > Also, like kito previous remind me: > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635326.html >   > > I think you should add a dedicated test which with specifying >

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> I'm going to configure with --with-arch=rv32gcv_zfh_zvfh --with-abi=ilp32d > to see if there is any difference. No change for me, how do you invoke the testsuite? I.e. Which target board? Regards Robin

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 10:30, juzhe.zh...@rivai.ai wrote: > I just checked definition of REG_EQUAL and REG_EQUIV. > > As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on > REG_EQUIV and skip REG_EQUAL. > Could you check whether it does fix your issues ? Yes it would fix the issues. I

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> Looks like your configure is --with-march=rv32gcv_zvfh, can you change to > --with-march=rv32gcv_zvfh_zfh? >From config.log: $ ../configure --prefix=/home/rdapp/projects/builds/gcc --target=riscv32-unknown-linux-gnu --disable-nls --disable-multilib --disable-bootstrap

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

> On 2023/11/13 18:22, juzhe.zh...@rivai.ai wrote: >> If there is a difference between them. I think we should fix riscv-common.cc. >> Since I think "zvfh_zfh" should not be different with "zfh_zvfh" > > It's possible. Let me debug it and see if there's a problem. I don't think it is different.

Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Hi Lehua, > Executing on host: > /work/home/lding/open-source/riscv-gnu-toolchain-push/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/build-gcc-newlib-stage2/gcc/xgcc > >

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

As per Jeff's remark I'm going to push the attached. Regards Robin Subject: [PATCH v4] RISC-V: vsetvl: Refine REG_EQUAL equality. This patch enhances the equality check for REG_EQUAL notes in the vsetvl pass by using the == operator instead of rtx_equal_p. With that, in situations like the

Re: [PATCH] RISC-V: testsuite: Fix popcount test.

Mhm, not so obvious after all. We vectorize 250 instances with rv32gcv, 229 with rv64gcv and 250 with rv64gcv_zbb. Will have another look tomorrow. Regards Robin

Re: [BUG FIX] RISC-V: Disallow COSNT_VECTOR for DI on RV32

Hi Juzhe, > This bug is exposed when testing on zvl512b RV32 system. > > The rootcause is RA reload DI CONST_VECTOR into vmv.v.x then it ICE. > > So disallow DI CONST_VECTOR on RV32. OK. Regards Robin

Re: [PATCH] RISC-V: testsuite: Add rv64 requirement for bug-9 and bug-14.

> /* { dg-do run { target { { {riscv_v} && {rv64} } } } } */ > > Seems you should remove rv64 here ? sicne I think it is redundant here. Going to commit with that removed. Regards Robin

Re: [PATCH] RISC-V: testsuite: Fix popcount test.

> Mhm, not so obvious after all. We vectorize 250 instances with > rv32gcv, 229 with rv64gcv and 250 with rv64gcv_zbb. Will have > another look tomorrow. The problem is that tree-vect-patterns is more restrictive than necessary and does not vectorize everything it could. Therefore I'm going to

[PATCH] vect: Allow reduc_index != 1 for COND_OPs.

Hi, in PR112406 Tamar found another problem with COND_OP reductions. I wrongly assumed that the reduction variable will always remain in operand 1, just as we create the COND_OP in ifcvt. But of course, addition being commutative, we are free to swap operand 1 and 2 and can end up with e.g.

[PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.

Hi, this removes the now-redundant vector_hw and zvfh_hw checks in the testsuite. Regards Robin gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Remove zvfh_hw. * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto. *

Re: [PATCH] vect: Allow reduc_index != 1 for COND_OPs.

>> Bootstrapped and regtested on aarch64 and regtested on riscv. x86 is >> still running. Just to confirm: x86 bootstrap and regtest unchanged. Going to commit it soon. Regards Robin

[PATCH] RISC-V/testsuite: Fix zvfh tests.

Hi, this fixes some zvfh test oversights as well as adds zfh to the target requirements. It's not strictly necessary to have zfh but it greatly simplifies test handling when we can just calculate the reference value instead of working around it. Regards Robin gcc/testsuite/ChangeLog:

Re: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.

> I don't get it. Why do we need remove them ?  It's just replaced by riscv_zvfh. I should probably edit the patch description and changelog entries to make it clearer. Regards Robin

Re: [PATCH] RISC-V: Fix permutation indice mode bug

LGTM. Regards Robin

Re: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].

> +/* { dg-final { scan-assembler-times "vmv\.v\.i\tv\[0-9\],0" 0 } } */ > > I think you should use "scan-assembler-not" Thanks, going to commit with that change. Regards Robin

Re: [PATCH] RISC-V: Add xfail test case for wv insn highest overlap

LGTM. Regards Robin

Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for vwcvt"

> (define_insn "@pred_vwsll_scalar" > - [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, > vd, vr, vd, vr, vd, vr, ?, ?") > + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr") Just noticed, not a problem of the revert but wasn't that wrong before without the

Re: State of risc-v port in the current merge, revert, rinse-repeat commotion

Thanks Vineet! > The dynamic icounts looks sane (vs. Apr 10 snapshot) except for a > regression in x264 which is likely independent of the chaos going on. > > Apr 10 | Apr 23  | >   109f1b28fc94  |  6f0a646dd2fc   | > +-+ > 276,584,692,883

[PATCH] RISC-V: Add testcase for PR114749.

Hi, this adds a test case for PR114749. Going to commit as obvious unless somebody complains. Regards Robin gcc/testsuite/ChangeLog: PR tree-optimization/114749 * gcc.target/riscv/rvv/autovec/pr114749.c: New test. --- .../gcc.target/riscv/rvv/autovec/pr114749.c | 15

[PATCH] RISC-V: Add VLS to mask vec_extract [PR114668].

Hi, this adds the missing VLS modes to the mask extract expanders. I found a dump scan difficult to create reliably so I just kept the PR's run test case. Regtested on rv64gcv. Regards Robin gcc/ChangeLog: PR target/114668 * config/riscv/autovec.md: Add VLS.

Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and xfail tests

Hi Pan, > The RVV register overlap requires both the dest, and src operands. > Thus the rigister filter in constraint cannot cover the fully sematics > of the vector register overlap. I'm not sure I'm following. Did we miss something that should have been covered? Like only an overlap on the

Re: [PATCH] internal-fn: Do not force vcond operand to reg.

> What happens if we simply remove all of the force_reg here? On x86 I bootstrapped and tested the attached without fallout (gcc188, so it's no avx512-native machine and therefore limited coverage). riscv regtest is unchanged. For aarch64 I would to rely on the pre-commit CI to pick it up (does

Re: [PATCH v1 3/3] RISC-V: Enable vectorizable early exit test

Hi Pan, > > @@ -4114,6 +4115,7 @@ proc check_effective_target_vect_early_break_hw { } { > || [check_effective_target_arm_v8_neon_hw] > || [check_sse4_hw_available] > || [istarget amdgcn-*-*] > + || [check_effective_target_riscv_v] > }}] > } I believe this should be

Re: [PATCH] internal-fn: Do not force vcond operand to reg.

> How does this make a difference in the end? I'd expect say forwprop to > fix things? In general we try to only add the masking "boilerplate" of our instructions at split time so fwprop, combine et al. can do their work uninhibited of it (and we don't need numerous (if_then_else ...

Re: [PATCH v1 2/3] RISC-V: Implement vectorizable early exit with vcond_mask_len

Hi Pan, thanks for working on this. In general the patch looks reasonable to me but I'd rather have some more comments about the high-level idea. E.g. cbranch is implemented like aarch64 by xor'ing the bitmasks and comparing the result against zero (so we branch based on mask equality). > +;;

[PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068].

Hi, this patch splits the vfw...wf pattern so we do not emit e.g. vfwadd.wf v0,v8,fa5,v0.t anymore. Regtested on rv64gcv_zvfh. Regards Robin gcc/ChangeLog: PR target/115068 * config/riscv/vector.md: Split vfw.wf pattern. gcc/testsuite/ChangeLog: *

Re: [PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068].

> I saw vwadd/vwsub.wx have same issue. Could you change them and add test too ? Yes, will do. At first I didn't manage to reproduce it because we seem to be lacking a combine-opt pattern for it. I'm going to post it separately. Regards Robin

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

Hi Demin, are you still going to continue with this? Regards Robin

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

> Can eqne pattern removal patches be committed firstly? Please first make sure you test with corner cases, NaNs in particular. I'm pretty sure we don't have any test cases for those. Regards Robin

[PATCH] internal-fn: Do not force vcond operand to reg.

Hi, this only forces the first comparison operator into a register if it is not already suitable. Bootstrap and regtest is running on x86 and aarch64, successful on p10. Regtested on riscv. gcc/ChangeLog: PR middle-end/113474 * internal-fn.cc (expand_vec_cond_mask_optab_fn):

[PATCH] RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].

Hi, three-operand instructions like vmacc are modeled with an implicit output reload when the output does not match one of the operands. For this we use vmv.v.v which is subject to length masking. In a situation where the current vl is less than the full vlenb and the fma's result value is used

[PATCH] vect: Do not peel epilogue for partial vectors [PR114196].

Hi, r14-7036-gcbf569486b2dec added an epilogue vectorization guard for early break but PR114196 shows that we also run into the problem without early break. Therefore remove early break from the conditions. gcc/ChangeLog: PR middle-end/114196 * tree-vect-loop-manip.cc

Re: [PATCH v2] RISC-V: Introduce option -mrvv-max-lmul for RVV autovec

LGTM as well. Regards Robin

Re: [PATCH] RISC-V: Introduce option -mrvv-autovec-max-lmul for RVV autovec

Should it really be called autovec-max-lmul? We also use TARGET_MAX_LMUL for builtins etc. Or are we just following LLVM's naming here? Isn't -mrvv-max-lmul sufficient? > PR target/112648 This PR is not really resolved or affected by the

Re: [PATCH] vect: Do not peel epilogue for partial vectors [PR114196].

Attached v2 combines the checks. Bootstrapped and regtested on x86 an power10, aarch64 still running. Regtested on riscv64. Regards Robin Subject: [PATCH v2] vect: Do not peel epilogue for partial vectors. r14-7036-gcbf569486b2dec added an epilogue vectorization guard for early break but

Re: [PATCH] vect: Do not peel epilogue for partial vectors [PR114196].

> r14-7036-gcbf569486b2dec added an epilogue vectorization guard for early > break but PR114196 shows that we also run into the problem without early > break. Therefore remove early break from the conditions. Forgot: Bootstrapped and regtested on x86, aarch64 and power10. Regtested on riscv64.

Re: [PATCH] RISC-V: Add initial cost handling for segment loads/stores.

> So where do we stand with this? Juzhe asked it to be rebased, but I > don't see a rebased version in my inbox and I don't see anything that > looks like this on the trunk. I missed this one and figured as we're pretty late in the cycle it can wait until GCC 15. Therefore let's call it

[PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].

Hi, for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or" two halves into one Pmode register. This patch disallows the optimization for inner_mode == Pmode and emits a simple broadcast

[PATCH] RISC-V: Add initial cost handling for segment loads/stores.

Hi, This has been sitting on my local tree - I've been wanting to post it for a while but somehow forgot. This patch makes segment loads and stores more expensive. It adds segment_load and segment_store cost fields to the common vector costs and adds handling to adjust_stmt_cost. In the future

Re: [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm

Hi Han, in addition to what Juzhe mentioned (and that late-combine is going to handle such cases) it should be noted that register pressure should not be the only consideration here. Many uarchs have a higher latency for register-file-crossing moves. At least without spilling the vv variant is

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

> 2. When I write if (a == 2) and if (2 == a), the results are > same > > 3. The vec_duplicate operand is the 5th operand in both cmp and > eqne patterns. I think they are equal. A comparison with a constant is always canonicalized to have the constant second, that's why you won't see

Re: [PATCH] RISC-V: Add initial cost handling for segment loads/stores.

> +  /* Segment load/store permute cost.  */ > +  const int segment_permute_2; > +  const int segment_permute_4; > +  const int segment_permute_8; > > Why do we only have 2/4/8, I think we should have 2/3/4/5/6/7/8 No idea why I posted that (wrong) version, I used it for some testing locally.

Re: [PATCH] RISC-V: Add initial cost handling for segment loads/stores.

> This patch looks odd to me. > I don't see memrefs in the trunk code. It's on top of the vle/vse offset handling patch from a while back that I haven't committed yet. > Also, I prefer list all cost in cost tune info for NF = 2 ~ 8 like ARM SVE > does: I don't mind having separate costs for

Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change

> I suggest specify -fno-schedule-insns to force tests assembler never > change for any scheduling model. We already do that and that's the point - as I mentioned before, no scheduling is worse than default scheduling here (for some definition of worse). The way to reduce the number of vsetvls

Re: [PATCH v2] DSE: Bugfix ICE after allow vector type in get_stored_val

On 2/29/24 02:38, Li, Pan2 wrote: >> So it's going to check if V2SF can be tied to DI and V4QI with SI. I >> suspect those are going to fail for RISC-V as those aren't tieable. > > Yes, you are right. Different REG_CLASS are not allowed to be tieable in > RISC-V. > > static bool >

Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

> I think it makes more sense to remove the whole > --param=riscv-autovec-preference since we should use > -fno-tree-vectorize instead of --param=riscv-autovec-preference=none > which is more reasonable compile option for users. > > --param is just a internal testing option that we added before,

Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change

On 2/24/24 00:10, Edwin Lu wrote: > Given the recent change with adding the scheduler pipeline descriptions, > many scan-dump failures emerged. Relax the expected assembler output > conditions on the affected tests to reduce noise. I'm not entirely sure yet about relaxing the scans like this.

Re: [PATCH] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

The patch is OK from the riscv side. generic-ooo includes fast unaligned access. Regards Robin

[PATCH] RISC-V: Introduce -mrvv-allow-misalign.

Hi, this patch changes the default from always enabling movmisalign to disabling it. It adds an option to override the default and adds generic-ooo to the uarchs that support misaligned vector access. It also adds a check_effective_target_riscv_v_misalign_ok to the testsuite which enables or

[PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

> We should have something in doc/invoke too, this one is going to be > tricky for users. We'll also have to define how this interacts with > the existing -mstrict-align. Addressed the rest in the attached v2 which also fixes tests. I'm really not sure about -mstrict-align. I would have hoped

[PATCH v3] RISC-V: Introduce -mvector-strict-align.

Attached is v3 with the discussed changes. It now has -mscalar-strict-align which is an alias to -mstrict-align as well as -mvector-strict-align. Testsuite shows no new regressions on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/riscv-opts.h

Re: [PATCH v3] RISC-V: Introduce -mvector-strict-align.

>> + /* By default, when -mno-vector-strict-align is not specified, do not >> allow >> + unaligned vector memory accesses except if -mtune's setting explicitly >> + allows it. */ >> + riscv_vector_unaligned_access_p = rvv_vector_strict_align == 0 || > > opts->x_rvv_vector_strict_align

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

> * -mstrict-align: Both scalar and vector misaligned accesses are > unsupported (-mrvv-allow-misalign doesn't matter). I'm not sure if > there's hardware there, but given we have systems that don't support > scalar misaligned accesses it seems reasonable to assume they'll also > not support

[PATCH] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

Hi, vwadd.wx and vwsub.wx have the same problem vfwadd.wf had. This patch splits the insn pattern in the same way vfwadd.wf was split. It also adds two patterns to recognize extended scalars. In practice those do not provide a lot of improvement over what we already have but in some instances

[PATCH] RISC-V: Use widening shift for scatter/gather if applicable.

Hi, with the zvbb extension we can emit a widening shift for scatter/gather index preparation in case we need to multiply by 2 and zero extend. The patch also adds vwsll to the mode_idx attribute and removes the mode from shift-count operand of the insn pattern. Regtested on rv64gcv_zvfh_zvbb.

[PATCH] RISC-V: Add vwsll combine helpers.

Hi, this patch enables the usage of vwsll in autovec context by adding the necessary combine patterns and tests. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/autovec-opt.md (*vwsll_zext1_): New pattern. (*vwsll_zext2_): Ditto.

[PATCH] RISC-V: Remove dead perm series code and document.

Hi, with the introduction of shuffle_series_patterns the explicit handler code for a perm series is dead. This patch removes it and also adds a function-level comment to shuffle_series_patterns. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/riscv-v.cc

[PATCH] RISC-V: Add vector popcount, clz, ctz.

Hi, this patch adds the zvbb vcpop, vclz and vctz to the autovec machinery as well as tests for them. It also changes several non-VLS iterators to V_VLS iterators for consistency. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (ctz2): New

[PATCH] RISC-V: Add vandn combine helper.

Hi, this patch adds a combine pattern for vandn as well as tests for it. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/autovec-opt.md (*vandn_): New pattern. * config/riscv/vector.md: Add vandn to mode_idx. gcc/testsuite/ChangeLog: *

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