Re: [PING^1][PATCH] rs6000: Change bitwise xor to inequality operator [PR106907]

Ping! please review. Thanks & Regards Jeevitha On 16/06/23 9:55 am, Peter Bergner wrote: > On 6/12/23 6:18 AM, P Jeevitha wrote: >> Bitwise xor performed on bool >> is similar to checking inequality. So changed to inequality >> operator (!=) instead of

[PATCH v2] rs6000: Change bitwise xor to an equality operator [PR106907]

. Additionally, comment indentation has been fixed. 2023-10-11 Jeevitha Palanisamy gcc/ PR target/106907 * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise xor to an equality and fix comment indentation. diff --git a/gcc/config/rs6000/rs6000.cc b

Re: [PING ^3][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! Please review On 13/11/23 8:38 pm, jeevitha wrote: > Ping! > > please review. > > Thanks & Regards > Jeevitha > > On 25/08/23 7:49 am, Peter Bergner wrote: >> On 8/24/23 12:35 PM, Michael Meissner wrote: >>> On Thu, Jul 20, 2023 at 10:05:28AM

[PING ^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! please review. Thanks & Regards Jeevitha On 25/08/23 7:49 am, Peter Bergner wrote: > On 8/24/23 12:35 PM, Michael Meissner wrote: >> On Thu, Jul 20, 2023 at 10:05:28AM +0530, jeevitha wrote: >>> gcc/ >>> PR target/110411 >>> * config/rs6000/

Re: [PATCH] rs6000: Disable PCREL for unsupported targets [PR111045]

On 11/11/23 5:21 am, Peter Bergner wrote: > Jeevitha, can you test this patch to see whether it fixes the testsuite > issue caused by your earlier patch that was approved, but not yet pushed? > That was the use GPR2 for register allocation, correct? Note, you'll need > to upda

Re: [PATCH V3] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di built-in [PR113950]

to proceed with the backport. Do you think the above change is acceptable, or should we also backport Segher's commit e0e3ce634818b83965b87512938490df4d57f81d, which caused the conflict?. There was no regression with both of these changes. Jeevitha.

[PING^1][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! I've incorporated all the suggested changes. Please review. Thanks & Regards Jeevitha On 21/03/24 6:21 pm, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > PTImode assists in generating even/odd registe

[PING^3][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]

Ping! please review. Thanks & Regards Jeevitha On 26/03/24 10:23 am, jeevitha wrote: > Ping! > > please review. > > Thanks & Regards > Jeevitha > > > On 26/02/24 11:13 am, jeevitha wrote: >> Hi All, >> >> The following patch has

[PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

created a tree node with dummy type to handle PTImode. We are not documenting this dummy type since users are not allowed to use this type externally. 2024-03-21 Jeevitha Palanisamy gcc/ PR target/110411 * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add

[PING^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! please review. Thanks & Regards Jeevitha On 23/02/24 3:04 pm, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > PTImode attribute assists in generating even/odd register pairs on 128 bits. > When the

[PING^1][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]

Ping! please review. Thanks & Regards Jeevitha On 26/02/24 11:13 am, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > PR110040 exposes an issue concerning moves from vector registers to GPRs. > There are tw

[PING^2][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]

Ping! please review. Thanks & Regards Jeevitha On 26/02/24 11:13 am, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > PR110040 exposes an issue concerning moves from vector registers to GPRs. > There are tw

[PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

a tree node with dummy type to handle PTImode. We are not documenting this dummy type since users are not allowed to use this type externally. 2024-02-23 Jeevitha Palanisamy gcc/ PR target/106895 * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields to hold

Re: [PATCH] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]

On 26/02/24 8:37 pm, Peter Bergner wrote: > On 2/26/24 4:49 AM, Kewen.Lin wrote: >> on 2024/2/26 14:18, jeevitha wrote: >>> Hi All, >>> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md >>> index 6111cc90eb7..e5688ff972a 100644 >>>

[PATCH V2] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]

in vsx_splat to splat_input_operand and corrected the assignment of op1 to operands[1]. These changes ensure that operand1 is stored in a register. 2024-02-26 Jeevitha Palanisamy gcc/ PR target/113950 * config/rs6000/vsx.md (vsx_splat_): Updated the predicates for second operand

Re: [PATCH] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]

can avoid to only test some fixed cpu type. >> >> If a simple "-O1 -vsx" is enough to expose the ICE on an unpacthed >> compiler and a PASS on a patched compiler, then I'm all for it. >> Jeevitha, can you try confirming that? Yes, Peter, I've confirmed that u

[PATCH] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]

to splat_input_operand, which will handle the operands appropriately. 2024-02-26 Jeevitha Palanisamy gcc/ PR target/113950 * config/rs6000/vsx.md (vsx_splat_): Updated the predicates for second operand. gcc/testsuite/ PR target/113950 * gcc.target/powerpc

[PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]

in storing the lower 64 bits. However, the instruction for copying the upper 64 bits is still emitted and is dead code. This patch adds a splitter that splits apart the two move instructions so that DCE can remove the dead code after splitting. 2024-02-26 Jeevitha Palanisamy gcc/ PR

[PATCH V3] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di built-in [PR113950]

an unrecognizable insn ICE. Even though the immediate value was forced into a register, it wasn't correctly assigned to the second operand. So corrected the assignment of op1 to operands[1]. 2024-02-29 Jeevitha Palanisamy gcc/ PR target/113950 * config/rs6000/vsx.md (vsx_splat_): Corrected

[PATCH] rs6000: Don't pass -many to the assembler [PR112868]

conditions to the assembler. 2024-05-15 Jeevitha Palanisamy gcc/ PR target/112868 * config/rs6000/rs6000.h (ASM_OPT_ANY): Removed Define. (ASM_CPU_SPEC): Remove ASM_OPT_ANY usage. diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 2cde2e329b0

Re: [PING^2][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! please review. Thanks & Regards Jeevitha On 17/04/24 2:44 pm, jeevitha wrote: > Ping! > > I've incorporated all the suggested changes. Please review. > > Thanks & Regards > Jeevitha > > On 21/03/24 6:21 pm, jeevitha wrote: >> Hi All, >>

Re: [PING^4][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]

Ping! please review. Thanks & Regards Jeevitha On 17/04/24 2:46 pm, jeevitha wrote: > Ping! > > please review. > > Thanks & Regards > Jeevitha > > On 26/03/24 10:23 am, jeevitha wrote: >> Ping! >> >> please review. >> >> Thanks

[PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

and movxo pattern to disallow these types of addresses, which assists LRA in resolving this issue. Furthermore, the mode size 16 check has been removed in vsx_quad_dform_memory_operand to allow OOmode and quad_address_p already handles less than size 16. 2023-07-19 Jeevitha Palanisamy gcc

[PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. When the user specifies PTImode as an attribute, it breaks. Created a tree node to handle PTImode types. PTImode attribute helps in generating even/odd register pairs on 128 bits. 2023-07-20 Jeevitha

[PING ^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]

Ping! please review. Thanks & Regards Jeevitha On 20/07/23 10:05 am, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > When the user specifies PTImode as an attribute, it breaks. Created > a tree node t

[PING^1][PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

Ping! please review. Thanks & Regards Jeevitha On 19/07/23 10:16 pm, jeevitha wrote: > Hi All, > > The following patch has been bootstrapped and regtested on powerpc64le-linux. > > There are no instructions that do traditional AltiVec addresses (i.e. > with the low fo

[PATCH] rs6000: Change bitwise xor to inequality operator [PR106907]

comment indentation 2023-06-12 Jeevitha Palanisamy gcc/ PR target/106907 * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise xor to inequality and fix comment indentation. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index

Re: [PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]

On 07/07/2023 A 12:11 am, Peter Bergner wrote: > I believe the untested patch below should also work, without having to scan > the (uncommonly used) options. Jeevitha, can you bootstrap and regtest the > patch below? Yeah Peter, Bootstrapped and regtested the below patch on powerpc6

[PATCH V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]

Jeevitha Palanisamy gcc/ PR target/PR110320 * config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change GPR2 to volatile and non-fixed register for PCREL. gcc/testsuite/ PR target/PR110320 * gcc.target/powerpc/pr110320-1.c: New testcase

[PATCH] rs6000: Don't ICE when generating vector pair load/store insns [PR110411]

ivec type address for OOmode and XOmode. 2023-07-05 Jeevitha Palanisamy gcc/ PR target/110411 * config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Avoid altivec address for OOmode and XOmde. gcc/testsuite/ PR target/110411 * gcc.target/powerpc/pr1104

[PATCH] MAINTAINERS: Add myself to write after approval

2023-05-30 Jeevitha Palanisamy ChangeLog: * MAINTAINERS (Write After Approval): Add myself. diff --git a/MAINTAINERS b/MAINTAINERS index 2dc51154446..4a7c963914b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -584,6 +584,7 @@ Patrick O'Neill

[PATCH] rs6000: Remove duplicate expression [PR106907]

PR106907 has few warnings spotted from cppcheck. In that addressing duplicate expression issue here. Here the same expression is used twice in logical AND(&&) operation which result in same result so removing that. 2023-06-05 Jeevitha Palanisamy gcc/ PR target/106907

Re: [PATCH] rs6000: Remove duplicate expression [PR106907]

Thanks for reviewing Segher. Will work on backports as well :). Jeevitha

[PATCH] Add parentheses to clarify precedence between operators [PR106907]

PR106907 has few warnings spotted from cppcheck. Inorder to clarify the order of precedence between operators added parentheses to explicitly group operations based on desired order of evaluation. 2023-06-07 Jeevitha Palanisamy gcc/ PR target/106907 * config/gcn/gcn.cc

[PATCH] rs6000: Remove redundant initialization [PR106907]

PR106907 has few warnings spotted from cppcheck. In that addressing redundant initialization issue. Here the initialized value of 'new_addr' was overwritten before it was read. Updated the source by removing the unnecessary initialization of 'new_addr'. 2023-06-07 Jeevitha Palanisamy gcc

[PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]

requesting TOC addressing, then the register r2 can be changed to volatile and non-fixed register. Changes in register preservation roles can be accomplished with the help of available target hooks (TARGET_CONDITIONAL_REGISTER_USAGE). 2023-06-23 Jeevitha Palanisamy gcc/ PR target/PR110320