[PATCH v2 4/16]middle-end: Add dissolve code for when SLP fails and non-SLP loop vectorization is to be tried.

Hi All, This adds the dissolve code to undo the patterns created by the pattern matcher in case SLP is to be aborted. As mentioned in the cover letter this has one issue in that the number of copies can needed can change depending on whether TWO_OPERATORS is needed or not. Because of this I

[PATCH v2 5/16]middle-end: Add shared machinery for matching patterns involving complex numbers.

Hi All, This patch adds shared machinery for detecting patterns having to do with complex number operations. The class ComplexPattern provides helpers for matching and ultimately undoing the permutation in the tree by rebuilding the graph. Bootstrapped Regtested on aarch64-none-linux-gnu and no

[PATCH v2 1/16]middle-end: Refactor refcnt to use SLP_TREE_REF_COUNT for consistency

Hi All, This is a small refactoring which introduces SLP_TREE_REF_COUNT and replaces the uses of refcnt with it. This for consistency between the other properties. A similar patch was pre-approved last year but since there are more use now I am sending it for review anyway. Bootstrapped

[PATCH v2 3/16]middle-end Add basic SLP pattern matching scaffolding.

Hi All, This patch adds the basic infrastructure for doing pattern matching on SLP trees. This is done immediately after the SLP tree creation because it can change the shape of the tree in radical ways and so we would like to do it before any analysis is performed on the tree. A new file

[PATCH v2 2/16]middle-end: Refactor and expose some vectorizer helper functions.

Hi All, This is a small refactoring which exposes some helper functions in the vectorizer so they can be used in other places. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * tree-vect-patterns.c (vect_mark_pattern_stmts):

[PATCH v2 0/16][RFC][AArch64/Arm/SVE/SVE2/MVE]middle-end Add support for SLP vectorization of complex number instructions.

Hi All, This patch series adds support for SLP vectorization of complex instructions [1]. These instructions exist only in their vector forms and require you to recognize two statements in parallel. Complex operations usually require a permute due to the fact that the real and imaginary

RE: [PATCH] ipa-inline: Improve growth accumulation for recursive calls

Hi Martin, > > can you please confirm that the difference between these two is all due to > the last option -fno-inline-functions-called-once ? Is LTo necessary? I.e., > can > you run the benchmark also built with the branch compiler and -mcpu=native > -Ofast -fomit-frame-pointer

RE: [PATCH] ipa-inline: Improve growth accumulation for recursive calls

Hi Martin, > -Original Message- > From: Martin Jambor > Sent: Tuesday, September 8, 2020 3:01 PM > To: Tamar Christina ; Richard Sandiford > ; luoxhu via Gcc-patches patc...@gcc.gnu.org> > Cc: seg...@kernel.crashing.org; luoxhu ; > wschm...@linux.ibm.com; li...@

RE: [PATCH] ipa-inline: Improve growth accumulation for recursive calls

Hi Martin, > Hi, > > On Thu, Aug 20 2020, Richard Sandiford wrote: > >> > >> > >> Really appreciate for your detailed explanation. BTW, My previous > >> patch for PGO build on exchange2 takes this similar method by setting > >> each cloned node to 1/10th of the frequency several month agao :) >

RE: Do not combine PRED_LOOP_GUARD and PRED_LOOP_GUARD_WITH_RECURSION

Hi Honza, > -Original Message- > From: Gcc-patches On Behalf Of Jan > Hubicka > Sent: Tuesday, August 11, 2020 11:04 AM > To: gcc-patches@gcc.gnu.org > Subject: Do not combine PRED_LOOP_GUARD and > PRED_LOOP_GUARD_WITH_RECURSION > > Hi, > this patch avoids both PRED_LOOP_GUARD and >

RE: [PATCH] AArch64: Fix hwasan failure in readline.

Hi Kyrill, > -Original Message- > From: Kyrylo Tkachov > Sent: Friday, July 31, 2020 8:47 AM > To: Tamar Christina ; gcc-patches@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; > Marcus Shawcroft ; Richard Sandiford > > Subject: RE: [PATCH] AArch64: Fix hwasan fail

[PATCH] AArch64: Fix hwasan failure in readline.

Hi All, My previous fix added an unchecked call to fgets in the new function readline. fgets can fail when there's an error reading the file in which case it returns NULL. It also returns NULL when the next character is EOF. The EOF case is already covered by the existing code but the error

Re: [PATCH 1/6] AArch64: Fix bugs in -mcpu=native detection.

, readline, find_field): New. (host_detect_local_cpu): Fix truncation issues. The 07/09/2020 18:31, Richard Sandiford wrote: > Tamar Christina writes: > > Hi Richard, > > > > Thanks for the review, > > > >> -Original Message- > >> From: R

RE: [PATCH 1/6] AArch64: Fix bugs in -mcpu=native detection.

Hi Richard, Thanks for the review, > -Original Message- > From: Richard Sandiford > Sent: Thursday, July 9, 2020 1:35 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw > ; Marcus Shawcroft > ; Kyrylo Tkachov > Subject: Re: [PATC

[PATCH 6/6] AArch64: Add test for -mcpu=native

Hi All, This adds some tests to the GCC testsuite for testing the -mcpu=native code. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/aarch64-cpunative.exp: New test.

[PATCH 5/6] Docs: Document environment setting directives for testsuite

Hi All, This document some of the existing DejaGnu directives to modify environment variables before test or compiler invocations. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * doc/sourcebuild.texi

[PATCH 4/6] Testsuite: Make it easier to debug environment setting functions

Hi All, This adds verbose output to dg-set-compiler-env-var and dg-set-target-env-var so you can actually see what they're setting when you add -v -v. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/testsuite/ChangeLog: *

[PATCH 3/6] Arm: Add GCC_CPUINFO override

Hi All, This adds an in intentionally undocumented environment variable GCC_CPUINFO which can be used to test -mcpu=native. Tests using these are added later on. Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/ChangeLog:

[PATCH 1/6] AArch64: Fix bugs in -mcpu=native detection.

Hi All, This patch fixes a couple of issues in AArch64's -mcpu=native processing: The buffer used to read the lines from /proc/cpuinfo is 128 bytes long. While this was enough in the past with the increase in architecture extensions it is no longer enough. It results in two bugs: 1) No

[PATCH 2/6] AArch64: Add GCC_CPUINFO override

Hi All, This adds an in intentionally undocumented environment variable GCC_CPUINFO which can be used to test -mcpu=native. Tests using this are added later on. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master, GCC 10, 9 and 8? Thanks, Tamar gcc/ChangeLog:

RE: PSA: Default C++ dialect is now C++17

> >> > > > > Just a small note that 510.parest_r SPEC 2017 benchmark can't be built > > now with default changed to -std=c++17. The spec config needs to be > adjusted. > > > > Martin > > And there one another failure in 520.omnetpp_r caused by run-time error: > Error during startup:

RE: [PATCH][RFC] __builtin_shuffle sometimes should produce zip1 rather than TBL (PR82199)

Adding AArch64 maintainers. > -Original Message- > From: Gcc-patches On Behalf Of Dmitrij > Pochepko > Sent: Thursday, June 11, 2020 12:22 PM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH][RFC] __builtin_shuffle sometimes should produce zip1 > rather than TBL (PR82199) > > The

RE: [PATCH][RFC] vector creation from two parts of two vectors produces TBL rather than ins (PR93720)

Adding AArch64 maintainers, Also Dmitrij the patch lacks a changelog. > -Original Message- > From: Gcc-patches On Behalf Of Dmitrij > Pochepko > Sent: Wednesday, June 17, 2020 10:09 AM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH][RFC] vector creation from two parts of two vectors >

RE: [PATCH] AArch64: Don't check for amdgcn-amdhsa at all on arm targets.

Hi Andrew, > > > > The amdgcn-amdhsa test seems to be running for all targets > > unconditionally while only really makes sense for certain targets. > > This patch adds an opt-out list and opts out arm targets. > > > > Regtested on aarch64-none-linux-gnu and no issues. > > > > Ok for master? > >

[PATCH] Testsuite: Mark check_effective_target_exceptions_enabled test as C++ test input.

Hi All, The test in check_effective_target_exceptions_enabled uses a C++ keyword `throw` and the test fails with a syntax error on any non-g++ test. I now tell the testsuite driver that this is a C++ input file so it runs it as such in all the drivers. Regtested on aarch64-none-linux-gnu and no

[PATCH] AArch64: Don't check for amdgcn-amdhsa at all on arm targets.

Hi All, The amdgcn-amdhsa test seems to be running for all targets unconditionally while only really makes sense for certain targets. This patch adds an opt-out list and opts out arm targets. Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar

RE: [IMPORTANT] ChangeLog related changes

Thanks both! Cheers, Tamar > -Original Message- > From: Martin Liška > Sent: Wednesday, June 10, 2020 2:41 PM > To: Tamar Christina ; Jonathan Wakely > > Cc: Jakub Jelinek ; g...@gcc.gnu.org; gcc-patches patc...@gcc.gnu.org> > Subject: Re: [IMPORTANT] C

RE: [IMPORTANT] ChangeLog related changes

Hi All, We've been wondering since we no longer list authors in the changelog (at least mklog doesn't generate it), How do we handle multi author patches nowadays? Tried searching for it on the website but couldn’t find anything. Thanks, Tamar > -Original Message- > From: Gcc-patches

Re: [PATCH] AArch64: Adjust costing of by element MUL to be the same as SAME3 MUL.

Hi Richard, The 06/09/2020 12:44, Richard Sandiford wrote: > Tamar Christina writes: > > Hi Richard, > > The 06/08/2020 16:42, Richard Sandiford wrote: > >> Tamar Christina writes: > >> > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/c

Re: [PATCH] AArch64: Adjust costing of by element MUL to be the same as SAME3 MUL.

Hi Richard, The 06/08/2020 16:42, Richard Sandiford wrote: > Tamar Christina writes: > > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > > index > > 97da60762390db81df9cffaf316b909cd1609130..9cc8da338125afa01bc9fb645f4112d2d7ef548c > >

RE: [PATCH PR95254] aarch64: gcc generate inefficient code with fixed sve vector length

Sending to list as well.. not sure why it was stripped from the reply all. > -Original Message- > From: Tamar Christina > Sent: Monday, June 8, 2020 3:25 PM > To: Jakub Jelinek ; Tobias Burnus > > Cc: Uros Bizjak ; nd > Subject: RE: [PATCH PR95254] aarch64: gcc gene

[PATCH] AArch64: Adjust costing of by element MUL to be the same as SAME3 MUL.

Hi All, The cost model is currently treating multiplication by element as being more expensive than 3 same multiplication. This means that if the value is on the SIMD side we add an unneeded DUP. If the value is on the genreg side we use the more expensive DUP instead of fmov. This patch

[PATCH][Committed][GCC][AArch64] Expand on comment of stack-clash and implicit probing through LR.

Hi All, This expands the comment on an assert we have in aarch64_layout_frame and points to an existing comment somewhere else that has a much longer explanation of what's going on. Committed under the GCC Obvious rule. Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.c

[PATCH][GCC][AArch64] opt: Fix options canonization for assembler

. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for trunk? and backport to GCC 8 and 9 after some stew. Thanks, Tamar gcc/ChangeLog: 2020-04-02 Tamar Christina PR target/94396 * common/config/aarch64/aarch64-common.c

Re: [PATCH][GCC][AArch64]: Break apart paradoxical subregs for VSTRUCT writes (PR target/94052)

Hi Richard, I have updated the patch, changelog is the same. bootstrapped and regtested on aarch64-none-linux-gnu and no issues. OK for gcc 9 and 8? Thanks, Tamar The 03/10/2020 11:49, Richard Sandiford wrote: > Tamar Christina writes: > > Hi All, > > > > This works ar

RE: [PATCH][GCC][AArch64]: Break apart paradoxical subregs for VSTRUCT writes (PR target/94052)

, dn, ct); +} +} // namespace +void bd::ba(const ay , const s &) { + bz(dm, bi, be, bg, bf, bh, bj, bk); +} +} // namespace an > -Original Message- > From: Tamar Christina > Sent: Monday, March 9, 2020 13:53 > To: gcc-patches@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; >

[PATCH][GCC][AArch64]: Break apart paradoxical subregs for VSTRUCT writes (PR target/94052)

-port to GCC 9 and GCC 8 after some stew? I will look into seeing if we can not generate these at all, but I'm not sure this is possible since the mid-end would need both the Mode and the Class to know that a pseudo will be assigned to multiple hardregs. Thanks, Tamar gcc/ChangeLog: 2020-03-09

RE: [PING][PATCH][GCC][ARM] Arm generates out of range conditional branches in Thumb2 (PR91816)

Hi Kyrill, Ok for backporting this patch to GCC 8 and GCC 9? Thanks, Tamar > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org > On Behalf Of Kyrill Tkachov > Sent: Thursday, January 30, 2020 14:55 > To: Stam Markianos-Wright ; gcc- > patc...@gcc.gnu.org > Cc: ni...@redhat.com;

RE: [PATCH] Fix bug in recursiveness check for function to be cloned (ipa/pr93707)

Hi Martin, > Honza, is it OK for trunk? Tamar, can you please double check it fixes > your problem with perlbench? > Thanks for working on this! Yes it does seem to fix the regression as well. Cheers, Tamar > Thanks, > > Martin > > > ipa-cp: Avoid wrongly gathering self-recursive edges (PR

RE: [GCC][PATCH][AArch64] ACLE intrinsics for BFCVTN, BFCVTN2 (AArch64 AdvSIMD) and BFCVT (AArch64 FP)

Hi Richard, > ..ffb5305e2e5ea1aadae07e82f > d8e > > d6f9f247c1a9 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-compil > > +++ e.c > > @@ -0,0 +1,48 @@ > > +/* { dg-do assemble { target { aarch64*-*-* } } } */ > > The

RE: [PATCH] Fix bug in recursiveness check for function to be cloned (ipa/pr93707)

Hi Feng, Thanks! The patch seems to work. Hopefully it gets reviewed soon so we can fix the two benchmarks  Thanks, Tamar > -Original Message- > From: Feng Xue OS > Sent: Thursday, February 13, 2020 05:40 > To: Tamar Christina ; Martin Jambor > ; Jan Hubick

RE: [PATCH V2] Generalized value pass-through for self-recursive function (ipa/pr93203)

Xue OS > Sent: Tuesday, February 11, 2020 13:11 > To: Tamar Christina ; Martin Jambor > ; Jan Hubicka ; gcc- > patc...@gcc.gnu.org > Cc: nd > Subject: Re: [PATCH V2] Generalized value pass-through for self-recursive > function (ipa/pr93203) > > Hi Tarmar, > > Since

RE: [PATCH V2] Generalized value pass-through for self-recursive function (ipa/pr93203)

Hi Feng, This patch (commit a0f6a8cb414b687f22c9011a894d5e8e398c4be0) is causing ICEs in the GCC and perlbench benchmark in Spec2017. during IPA pass: cp lto1: internal compiler error: in find_more_scalar_values_for_callers_subset, at ipa-cp.c:4709 0x1698187

Re: [PATCH][GCC][middle-end] Fix logical shift truncation (PR91838)

Hi Segher, The 01/31/2020 12:13, Segher Boessenkool wrote: > Hi! > > On Fri, Jan 31, 2020 at 10:12:08AM +0000, Tamar Christina wrote: > > This fixes a fall-out from a patch I had submitted two years ago which > > started > > allowing simplify-rtx to fold logi

[PATCH][GCC][middle-end] Fix logical shift truncation (PR91838)

(mode) - 1, but that's not a regression so punting it. Bootstrapped Regtested on aarch64-none-linux-gnu and x86_64-pc-linux-gnu with no issues. Ok for trunk? and backport to GCC 8 and 9 with some stew? Thanks, Tamar gcc/ChangeLog: 2020-01-31 Tamar Christina PR 91838 * si

RE: Make profile estimation more precise

ions but doesn't seem to be what you're referring to? Thanks, Tamar > -Original Message- > From: Jan Hubicka > Sent: Friday, January 17, 2020 19:21 > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd > Subject: Re: Make profile estimation more precise > > >

RE: [committed][GCC][PATCH][AArch64] Fix unused variable warning breaking bootstrap.

Hi Richard, > > > > 2020-01-18 Tamar Christina > > > > * config/aarch64/aarch64-sve-builtins-base.cc > (memory_vector_mode): > > Mark parameter unused. > > Thanks for the quick fix. > > Sorry for indulging a personal preference, but

[committed][GCC][PATCH][AArch64] Fix unused variable warning breaking bootstrap.

Hi All, This marks the parameter as unused so it doesn't cause a boostrap failure. Bootstrapped aarch64-none-linux-gnu. committed under the obvious rule. Thanks, Tamar gcc/ChangeLog: 2020-01-18 Tamar Christina * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode

RE: Make profile estimation more precise

Hi Honza, This change seems to have cost a 0.2% regression in SPEC2017 vs a codesize reduction of 0.02%. Only leela seems to have made any noticable difference at 2.64% codesize reduction. Is there anyway to keep the performance at -O3 where the codesize doesn't matter much? Thanks, Tamar

RE: [PATCH] Add Optimization for various IPA parameters.

Hi Xiong, > > It seems the parameters no longer do anything. i.e. -flto --param ipa-cp- > eval-threshold=1 --param ipa-cp-unit-growth=80 doesn't have any effect > anymore. > > Strange that you don't need -fno-inline to achieve the 30% performance > boost, I found that some specialized nodes are

RE: [RFC c-common PATCH] PR c++/40752 - useless -Wconversion with short +=.

Hi Jason, The commit Shorten right-shift again in C++. Back in SVN r131862 richi removed this code to fix PR 34235, but didn't remove the parallel code from the C front-end because the bug had previously been fixed in r44080. This patch copies the code from C again. * typeck.c

RE: [PATCH] Add Optimization for various IPA parameters.

Hi Martin, This change (r280099) is causing a major performance regression on exchange2 in SPEC2017 dropping the benchmark by more than 30%. It seems the parameters no longer do anything. i.e. -flto --param ipa-cp-eval-threshold=1 --param ipa-cp-unit-growth=80 doesn't have any effect anymore.

RE: [PATCH][GCC][SLP][testsuite] Turn off vect-epilogue-nomask for slp-rect-3

Regards, Tamar > > Disabling epilogue vect is of course OK if it simplifies things. > > > Regtested on arm-none-eabi and no issues. > > > > Ok for trunk? > > > Thanks, > > Tamar > > > > gcc/testsuite/ChangeLog: > > > > 2019-11-28 Tamar

[PATCH][GCC][SLP][testsuite] Turn off vect-epilogue-nomask for slp-rect-3

and no issues. Ok for trunk? Thanks, Tamar gcc/testsuite/ChangeLog: 2019-11-28 Tamar Christina * gcc.dg/vect/slp-reduc-3.c: Turn off epilogue-nomask. -- diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-3.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-3.c index 9c8124c9b5f289d0a2ed49d3c8ee626d0bf05862

RE: Ping: [PATCH V6] Extend IPA-CP to support arithmetically-computed value-passing on by-ref argument (PR ipa/91682)

Hi Honza, > > > > > > > I checked update_jump_functions_after_inlining(), and found one > > > suspicious place: > > > > > > > > for (i = 0; i < count; i++) > > > > { > > > > struct ipa_jump_func *dst = ipa_get_ith_jump_func (args, i); > > > > if (!top) > > > > { > > > >

RE: Ping: [PATCH V6] Extend IPA-CP to support arithmetically-computed value-passing on by-ref argument (PR ipa/91682)

Hi Honza, > > > I checked update_jump_functions_after_inlining(), and found one > suspicious place: > > > > for (i = 0; i < count; i++) > > { > > struct ipa_jump_func *dst = ipa_get_ith_jump_func (args, i); > > if (!top) > > { > > ipa_set_jf_unknown (dst); > >

Re: [committed] [testsuite] Fix fp-int-convert-timode-1.c testism.

Hi Joseph, > > Or do you want me to send them separately? > > I think it's best to fix the test now not to have the #ifdef, then if you > have execution failures those can be addressed separately. (If you want > to avoid the test FAILing before then, an XFAIL with a comment referencing > an

RE: [committed] [testsuite] Fix fp-int-convert-timode-1.c testism.

Hi Joseph, > FE_TONEAREST is the default rounding mode, so it would be better just to > remove the fesetround call and include and fenv effective-target > and -frounding-math option and let this test run for all configurations with > int128 support. > Hmm right, doing makes the execution of

[committed] [testsuite] Fix fp-int-convert-timode-1.c testism.

and aarch64_be-none-elf and no issues. Committed under the GCC obvious rules. gcc/testsuite/ChangeLog: 2019-11-21 Tamar Christina * gcc.dg/torture/fp-int-convert-timode-1.c: Add check for FE_TONEAREST. -- diff --git a/gcc/testsuite/gcc.dg/torture/fp-int-convert-timode-1.c b/gcc/testsuite/gcc.dg

RE: [GCC][PATCH][AArch64] Update hwcap string for fp16fml in aarch64-option-extensions.def

OK to backport to GCC 9? Thanks, Tamar > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org > On Behalf Of Kyrill Tkachov > Sent: Tuesday, September 24, 2019 14:32 > To: Stam Markianos-Wright ; gcc- > patc...@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; > James Greenhalgh ; Marcus

RE: [RFC][GCC][AArch64] Add minmax phi-reduction pattern

From: Richard Biener > Sent: Monday, November 18, 2019 11:24 > To: Joel Hutton > Cc: GCC Patches ; Tamar Christina > ; nd > Subject: Re: [RFC][GCC][AArch64] Add minmax phi-reduction pattern > > On Fri, 15 Nov 2019, Joel Hutton wrote: > > > Forgot to CC mai

[committed][middle-end][SLP] Initialize variable to fix bootstrap after r277784.

/ChangeLog: 2019-11-04 Tamar Christina * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Initialize rstmt. -- diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index 5549d053bf3cd102a4c4fcdc2e890c596927bd55..f4b445ac1ef9cff8280964dcc8937b3b74fe2a7c 100644 --- a/gcc/tree-vect

[PATCH][GCC][Arm][libsanitizer] Fix arm libsanitizer bootstrap failure

of the remaining fields should be the same. Bootstrapped arm-none-linux-gnueabihf and no issues. Ok for trunk? Thanks, Tamar libsanitizer/ChangeLog: 2019-10-22 Tamar Christina PR sanitizer/92154 * sanitizer_common/sanitizer_platform_limits_posix.cpp (defined): Exclude arm

RE: [PATCH 1/2][GCC][RFC][middle-end]: Add SLP pattern matcher.

Hi Richi, > -Original Message- > From: Richard Biener > Sent: Friday, October 11, 2019 8:02 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; o...@ucw.cz > Subject: Re: [PATCH 1/2][GCC][RFC][middle-end]: Add SLP pattern matcher. > > On Tue, 8 Oct 201

Re: [PATCH 1/2][GCC][RFC][middle-end]: Add SLP pattern matcher.

Hi Richi, Thanks for the review, I've added some comments inline. The 10/07/2019 12:15, Richard Biener wrote: > On Tue, 1 Oct 2019, Tamar Christina wrote: > > > Hi All, > > > > This adds a framework to allow pattern matchers to be written at based on > > the

[PATCH 2/2][GCC][RFC][middle-end]: Add complex number arithmetic patterns to SLP pattern matcher.

aarch64-none-linux-gnu with patterns on and no issues. no regression testing done yet but spec 2017 builds cleanly. Thanks, Tamar gcc/ChangeLog: 2019-10-01 Tamar Christina * tree-vect-slp.c (vect_split_slp_tree): New. (vect_merge_slp_tree): New.

[PATCH 1/2][GCC][RFC][middle-end]: Add SLP pattern matcher.

nks, Tamar gcc/ChangeLog: 2019-10-01 Tamar Christina * tree-vect-loop.c (vect_dissolve_slp_only_patterns): New. (vect_dissolve_slp_only_groups): Use macro. * tree-vect-patterns.c (vect_mark_pattern_stmts): Expose symbol. * tree-vect-slp.c (vect_free_slp_tree): A

RE: [PATCH] Add generic support for "noinit" attribute

Hi Christoph, The noinit testcase is currently failing on x86_64. Is the test supposed to be running there? Thanks, Tamar -Original Message- From: gcc-patches-ow...@gcc.gnu.org On Behalf Of Christophe Lyon Sent: Wednesday, August 14, 2019 2:18 PM To: Christophe Lyon ; Martin Sebor ;

Re: [GCC][middle-end] Add rules to strip away unneeded type casts in expressions (2nd patch)

Hi All, Here's an updated patch with the changes processed from the previous review. I've bootstrapped and regtested on aarch64-none-linux-gnu and x86_64-pc-linux-gnu and no issues. Ok for trunk? Thanks, Tamar The 07/02/2019 11:20, Richard Biener wrote: > On Tue, 2 Jul 2019, Tamar Christ

Re: [GCC][middle-end] Add rules to strip away unneeded type casts in expressions (2nd patch)

t all? > It's also not a 1:1 move since you are changing 'expr'. > > Thanks, > Richard. > > > > Thanks, > > > Tamar > > > > > > Concretely it makes both these cases behave the same > > > > > > float e = (float)a *

RE: [GCC][middle-end] Add rules to strip away unneeded type casts in expressions (2nd patch)

Adding some maintainers > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org On > Behalf Of Tamar Christina > Sent: Tuesday, June 25, 2019 09:31 > To: gcc-patches@gcc.gnu.org > Cc: nd > Subject: [GCC][middle-end] Add rules to strip away unneeded type casts

[GCC][middle-end] Add rules to strip away unneeded type casts in expressions (2nd patch)

Tamar gcc/ChangeLog: 2019-06-25 Tamar Christina * convert.c (convert_to_real_1): Move part of conversion code... * match.pd: ...To here. gcc/testsuite/ChangeLog: 2019-06-25 Tamar Christina * gcc.dg/type-convert-var.c: New test. -- diff --git a/gcc/convert.c b/gcc/conve

RE: [PATCH][GCC][AArch64] Make processing less fragile in config.gcc

Hi All, This is an update to the patch rebased to after the SVE2 options have been merged. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for trunk? Thanks, Tamar > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org > On Behalf Of Tamar Christi

[PATCH][GCC][AArch64] Make processing less fragile in config.gcc

above and makes the code a bit more readable. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for trunk? and for eventual backport? Thanks, Tamar gcc/ChangeLog: 2019-05-21 Tamar Christina PR target/89517 * config.gcc: Relax parsing

RE: [committed][PATCH][GCC][AArch64] Make test options_set_10.c not run on native

Oh dear. I hadn't noticed that at all. Thanks, Corrected it. gcc/testsuite/ChangeLog: 2019-03-04 Tamar Christina PR target/88530 * gcc.target/aarch64/options_set_10.c: Add native. > -Original Message- > From: Jakub Jelinek > Sent: Monday, March 4, 2

[committed][PATCH][GCC][AArch64] Make test options_set_10.c not run on native

obvious rules. Thanks, Tamar gcc/testsuite/ChangeLog: 2019-03-04 Tamar Christina PR target/88530 * gcc.target/aarch64/options_set_10.c: -- diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_10.c b/gcc/testsuite/gcc.target/aarch64/options_set_10.c index

RE: [PATCH][GCC][AArch64] Have empty HWCAPs string ignored during native feature detection

> -Original Message- > From: Jakub Jelinek > Sent: Monday, March 4, 2019 13:38 > To: Christophe Lyon > Cc: Tamar Christina ; James Greenhalgh > ; Kyrill Tkachov > ; gcc-patches@gcc.gnu.org; nd > ; Richard Earnshaw ; Marcus > Shawcroft > Subject: Re: [P

RE: [PATCH][GCC][AArch64] Have empty HWCAPs string ignored during native feature detection

Hi Christophe, > -Original Message- > From: Christophe Lyon > Sent: Monday, March 4, 2019 13:32 > To: Tamar Christina > Cc: James Greenhalgh ; Jakub Jelinek > ; Kyrill Tkachov ; gcc- > patc...@gcc.gnu.org; nd ; Richard Earnshaw > ; Marcus Shawcroft > > Sub

[PATCH][GCC][AArch64] Make every option in options.def one line (GCC-8).

? Thanks, Tamar gcc/ChangeLog: 2019-03-01 Tamar Christina PR target/89517 * config/aarch64/aarch64-option-extensions.def (fp, simd, crypto, fp16): Collapse line. -- diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option

[PATCH][GCC][AArch64] Make every option in options.def one line

in config.gcc. I will send that one out for GCC 10. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2019-03-01 Tamar Christina PR target/89517 * config/aarch64/aarch64-option-extensions.def (fp, simd, crypto, fp16

RE: [PATCH][GCC][AArch64] Have empty HWCAPs string ignored during native feature detection

Hi James, > -Original Message- > From: James Greenhalgh > Sent: Wednesday, February 27, 2019 17:22 > To: Tamar Christina > Cc: Jakub Jelinek ; Kyrill Tkachov > ; gcc-patches@gcc.gnu.org; nd > ; Richard Earnshaw ; Marcus > Shawcroft > Subject: Re: [PATCH][GCC]

RE: [PATCH][GCC][AArch64] Have empty HWCAPs string ignored during native feature detection

Ping. > -Original Message- > From: Tamar Christina > Sent: Thursday, February 7, 2019 10:43 > To: Tamar Christina ; Jakub Jelinek > > Cc: Kyrill Tkachov ; gcc-patches@gcc.gnu.org; > nd ; James Greenhalgh ; > Richard Earnshaw ; Marcus Shawcroft > > Sub

Re: [PATCH][GCC][AArch64] Fix command line options canonicalization version #2. (PR target/88530)

The 02/21/2019 22:34, James Greenhalgh wrote: > On Wed, Feb 20, 2019 at 08:00:38AM -0600, Tamar Christina wrote: > > Hi All, > > > > Commandline options on AArch64 don't get canonicalized into the smallest > > possible set before output to the assembler. This means th

[PATCH][GCC][AArch64] Fix command line options canonicalization version #2. (PR target/88530)

rmv8.2-a+crypto+sha2 => -march=armv8.2-a+crypto -march=armv8.2-a+sha2+aes => -march=armv8.2-a+crypto The remaining behaviors stay the same. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2019-02-20 Tamar Christina PR

[PATCH 1/2][GCC][AArch64] Update Armv8.4-a's FP16 FML intrinsics

ar gcc/ChangeLog: 2019-02-20 Tamar Christina * config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32, vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32, vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32, vfmlsl_lane_low_u32, vfmlal_laneq

[PATCH 2/2][GCC][Arm] Update Armv8.4-a's FP16 FML intrinsics

vfmlsl_laneq_high_f16): ... To this. * config/arm/neon.md: Update comments. gcc/testsuite/ChangeLog: 2019-02-20 Tamar Christina * gcc.target/arm/simd/fp16fml_high.c (test_vfmlal_high_u32, test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32): Rename

[Committed][PATCH][GCC][Arm] Remove alternative from neon_softfp_fp16 directive.

see a good way to solve this problem, really the feature tests should ideally contain the extra options the test adds too, but for this specific case it can be solved by always testing the fpu explicitly. Committed under the GCC obvious Thanks, Tamar gcc/testsuite/ChangeLog: 2019-02-15 Tamar

RE: [PATCH][GCC][Arm] Add HF modes to ANY iterators

neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee " which is why it passes locally. Forcing the -mfpu seems a bit wrong to me, so I guess the right solution is to remove the second alternative from the feature test and always explicitly test the fpu. I'll write up a patch. Th

RE: [Committed][PATCH][GCC][Arm] Fix test directive

Hi Christoph, > > On Thu, 14 Feb 2019 at 19:27, Tamar Christina > wrote: > > > > Hi All, > > > > This patch fixes a failing testcase due to a use of dg-options instead > > of dg-additional-options. > > > Makes sense. > It doesn't fail in any o

[Committed][PATCH][GCC][Arm] Fix test directive

Hi All, This patch fixes a failing testcase due to a use of dg-options instead of dg-additional-options. Committed under the GCC obvious Bootstrapped Regtested on arm-none-eabi and no issues. Ok for trunk? Thanks, Tamar gcc/testsuite/ChangeLog: 2019-02-14 Tamar Christina

Re: [PATCH][GCC][Arm] Add HF modes to ANY iterators

Christina PR target/88850 * config/arm/iterators.md (ANY64): Add V4HF. gcc/testsuite/ChangeLog: 2019-02-14 Tamar Christina PR target/88850 * gcc.target/arm/pr88850-2.c: New test. * lib/target-supports.exp

Re: [PATCH][GCC][Arm] Add HF modes to ANY iterators

The 02/13/2019 10:57, Kyrill Tkachov wrote: > Hi Tamar > > On 2/13/19 10:33 AM, Tamar Christina wrote: > > Hi All, > > > > The iterators ANY64 and ANY128 are used in various general split > > patterns and > > are supposed to contain any 64 bit and 128 b

[PATCH][GCC][Arm] Add HF modes to ANY iterators

. These are required by various split patterns that expect them to be there. Bootstrapped Regtested on aarch64-none-linux-gnu and issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2019-02-13 Tamar Christina PR target/88850 * config/arm/iterators.md (ANY64): Add V4HF

Re: [PATCH][GCC][AArch64] Allow any offset for SVE addressing modes before reload

for trunk? Thanks, Tamar gcc/ChangeLog: 2019-02-13 Tamar Christina PR target/88847 * config/aarch64/aarch64-sve.md (*pred_mov, pred_mov): Expose as @aarch64_pred_mov. * config/aarch64/aarch64.c (aarch64_classify_address): Use expand_insn which legitimizes oper

[PATCH][GCC][Arm] Update tests after register allocation changes. (PR/target 88560)

using integer loads and stores. Because of we also save on some mov.f16s that were being emitted before to move between the two. The aapcs cases now match the f32 cases in using floating point operations. Regtested on arm-none-eabi and no issues. Ok for trunk? Thanks, Tamar 2019-02-11 Tamar

[PATCH][GCC][AArch64] Allow any offset for SVE addressing modes before reload

address classifications. Bootstrapped on aarch64-none-linux-gnu and no issues. Regtested on aarch64-none-elf with SVE on and no issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2019-02-11 Tamar Christina PR target/88847 * config/aarch64/aarch64.c (aarch64_classify_address

[committed][PATCH][GCC][AArch64] Fix initializer for array so it's a C initializer instead of C++

Hi All, This fixes a missing = that would cause the array initializer to be a C++ initializer instead of a C one, causing a warning when building with pre-C++11 standards compiler. Committed under the GCC obvious rules. gcc/ChangeLog: 2019-02-07 Tamar Christina * config/aarch64

RE: [PATCH][GCC][AArch64] Have empty HWCAPs string ignored during native feature detection

in the existing code and to be slightly more efficient. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2019-02-07 Tamar Christina PR target/88530 * config/aarch64/aarch64-option-extensions.def: Document

RE: [PATCH][wwwdocs][Arm][AArch64] Update changes with new features and flags.

Hi Gerard, > > On Wed, 6 Feb 2019, Tamar Christina wrote: > > I've updated the patch with your suggested changes and have grouped > > the Arm and AArch64 targets a bit. > > Thanks, Tamar! > > > Ok for commit? > > Yes, I had meant to imply this in

Re: [PATCH][wwwdocs][Arm][AArch64] Update changes with new features and flags.

Hi Gerald, I've updated the patch with your suggested changes and have grouped the Arm and AArch64 targets a bit. Ok for commit? Thanks, Tamar The 01/31/2019 10:21, Ramana Radhakrishnan wrote: > > > On Thu, 31 Jan 2019, 10:09 Tamar Christina > mailto:tamar.christ...@arm.com&

<    5   6   7   8   9   10   11   12   13   14   >