Thanks for the duplicate ping. This is fine.
So this indeed solves the discrepancy between running SMS w/ and w/o debugging?
Please include a comment next to the code stating why it's important
not to create such deps.
You may also want to store the result of DEP_PRO (dep) in
src_something and use
Roman, Andrey,
Sorry for the delayed response.
It would indeed be good to have SMS apply to more loop patterns, still
within the realm of *countable* loops. SMS was originally designed to
handle doloops, with a specific pattern controlling the loop, easily
identified and separable from the
On Fri, Feb 3, 2012 at 8:07 PM, Jakub Jelinek ja...@redhat.com wrote:
Hi!
On some targets e.g. sms-7.c test fails, because fprintf is called
with %s format and NULL argument, GLIBC prints for that e.g.
SMS loop num: 1, file: (null), line: 0
but it isn't portable. print-rtl.c guards the
On Tue, Jan 10, 2012 at 12:31 PM, Revital1 Eres e...@il.ibm.com wrote:
Hello,
The patch below fixes ICE reported in PR51794.
It avoids creating DDG edges for register uses of class DF_REF_ARTIFICIAL
as
the latter does not have real instructions for them and thus calling
BLOCK_FOR_INSN
SMS changes are ok.
* common.opt (fmodulo-sched-reg-pressure, -fmodulo-sched-verbose):
New flags.
We should document what the different verbosity levels are, or
at-least their range.
Thanks,
Ayal.
On Tue, Jan 10, 2012 at 7:48 PM, Vladimir Makarov vmaka...@redhat.com wrote:
On
On Mon, Jan 2, 2012 at 3:30 PM, Richard Sandiford
rdsandif...@googlemail.com wrote:
Ayal Zaks ayal.z...@gmail.com writes:
+ for (i = 0; i ira_pressure_classes_num; i++)
+ {
+ enum reg_class pressure_class;
+
+ pressure_class = ira_pressure_classes[i
The attached patch prevents the creation of reg-moves for definitions
with MODE_CC and thus solves this ICE.
Currently testing and bootstrap on ppc64-redhat-linux, enabling SMS on
loops with SC 1.
OK for 4.7 once testing completes?
Yes, thanks for catching this. Shouldn't we prevent creating
On Mon, Dec 19, 2011 at 4:28 PM, Richard Sandiford
richard.sandif...@linaro.org wrote:
Hi Revital,
Revital Eres revital.e...@linaro.org writes:
The attached patch is a resubmission following comments made by Ayal
and Richard.
Tested and bootstrap with the other patches in the series on
sure, OK, thanks for catching this leak.
Ayal.
On Mon, Dec 12, 2011 at 8:25 AM, Revital Eres revital.e...@linaro.org wrote:
Hello,
OK for 3.7?
Sorry, I meant GCC 4.7.0...
Thanks,
Revital
These fixes to individual sms testcases are OK.
Thanks,
Ayal.
On Mon, Dec 5, 2011 at 3:07 PM, Revital Eres revital.e...@linaro.org wrote:
Hello,
Ping: http://gcc.gnu.org/ml/gcc-patches/2011-11/msg02444.html
Thanks,
Revital
On Mon, Nov 21, 2011 at 7:07 AM, Revital Eres revital.e...@linaro.org wrote:
Hello,
This patch support the estimation of register pressure in SMS.
Although GCC is in stage 3 I would appreciate comments on it.
Thanks to Richard and Ayal for discussing the implementation and their
insights.
On Fri, Sep 30, 2011 at 5:22 PM, Roman Zhuykov zhr...@ispras.ru wrote:
2011/7/21 zhr...@ispras.ru:
This patch should be applied only after pending patches by Revital.
Ping. New version is attached, it suits current trunk without
additional patches.
Thanks for the ping.
Also this related
On Mon, Oct 10, 2011 at 1:57 PM, Richard Sandiford
richard.sandif...@linaro.org wrote:
Ayal Zaks ayal.z...@gmail.com writes:
I agree it's natural to schedule moves for intra-iteration dependencies
in the normal get_sched_window way. But suppose we have a dependency:
A --(T,N,1)-- B
On Wed, Sep 28, 2011 at 4:49 PM, Richard Sandiford
richard.sandif...@linaro.org wrote:
Ayal Zaks ayal.z...@gmail.com writes:
+ /* The cyclic lifetime of move-new_reg starts and ends at move-def
+ (the instruction that defines move-old_reg).
So instruction I_REG_MOVE (new_reg=reg
On Wed, Sep 28, 2011 at 4:53 PM, Richard Sandiford
richard.sandif...@linaro.org wrote:
Ayal Zaks ayal.z...@gmail.com writes:
Only request is to document that the register moves are
placed/assigned-id's in a specific order.
I suppose this is the downside of splitting the patches up, sorry
On Fri, Sep 30, 2011 at 10:03 AM, Revital Eres revital.e...@linaro.org wrote:
Hello,
This
+ /* Skip instructions that do not set a register. */
+ if (set !REG_P (SET_DEST (set)))
+ continue;
is ok. Can you also prevent !set insns from having reg_moves? (To be updated
On Tue, Sep 27, 2011 at 10:47 AM, Revital Eres revital.e...@linaro.org wrote:
Hello,
This
+ /* Skip instructions that do not set a register. */
+ if (set !REG_P (SET_DEST (set)))
+ continue;
is ok. Can you also prevent !set insns from having reg_moves? (To be updated
On Tue, Sep 27, 2011 at 9:47 AM, Revital Eres revital.e...@linaro.org wrote:
Hello,
ok, so if we have an auto-inc'ing insn which defines (auto-inc's) an
addr register and another (say, result) register, we want to allow the
result register to have life ranges in excess of ii (by eliminating
OK for mainline?
Doh, hard to believe we never checked that an insn defines a register
before spitting out reg_moves for it ... nice catch.
This
+ /* Skip instructions that do not set a register. */
+ if (set !REG_P (SET_DEST (set)))
+ continue;
is ok. Can you also prevent
On Mon, Sep 26, 2011 at 7:31 AM, Revital Eres revital.e...@linaro.org wrote:
Hello,
This patch extends the implementation to support instructions with
REG_INC notes.
It addresses the comments from the previous submission:
http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01299.html.
ok, so if
richard.sandif...@linaro.org
Ayal Zaks ayal.z...@gmail.com writes:
Richard Sandiford richard.sandif...@linaro.org wrote on 30/08/2011
03:10:50 PM:
From: Richard Sandiford richard.sandif...@linaro.org
To: gcc-patches@gcc.gnu.org
Cc: Ayal Zaks/Haifa/IBM@IBMIL
Date: 30/08/2011 03:10 PM
Subject: [3
Richard Sandiford richard.sandif...@linaro.org wrote on 30/08/2011
03:29:26 PM:
From: Richard Sandiford richard.sandif...@linaro.org
To: gcc-patches@gcc.gnu.org
Cc: Ayal Zaks/Haifa/IBM@IBMIL
Date: 30/08/2011 03:29 PM
Subject: [4/4] Make SMS schedule register moves
This is the move
Richard Sandiford richard.sandif...@linaro.org wrote on 30/08/2011
03:10:50 PM:
From: Richard Sandiford richard.sandif...@linaro.org
To: gcc-patches@gcc.gnu.org
Cc: Ayal Zaks/Haifa/IBM@IBMIL
Date: 30/08/2011 03:10 PM
Subject: [3/4] SMS: Record moves in the partial schedule
This patch adds
2011/9/13 Richard Sandiford richard.sandif...@linaro.org
Ayal Zaks ayal.z...@gmail.com writes:
So instead of navigating directly from
ps_insn-ddg_node-node_sched_params, we now use indices and lookup
pointees in ddg_node and node_sched_params arrays. A bit of a
nuisance, but it's ok
Richard Sandiford richard.sandif...@linaro.org wrote on 30/08/2011
03:03:59 PM:
From: Richard Sandiford richard.sandif...@linaro.org
To: gcc-patches@gcc.gnu.org
Cc: Ayal Zaks/Haifa/IBM@IBMIL
Date: 30/08/2011 03:05 PM
Subject: [2/4] SMS: Use ids to represent ps_insns
Instructions
Resending; didn't seem to go through.
-- Forwarded message --
From: Ayal Zaks ayal.z...@gmail.com
Date: 2011/9/11
Subject: gcc-patches@gcc.gnu.org
To: Richard Sandiford richard.sandif...@linaro.org
Richard Sandiford richard.sandif...@linaro.org wrote on 30/08/2011
02:58:22 PM
Copying the lists..
-- Forwarded message --
From: Ayal Zaks ayal.z...@gmail.com
Date: 2011/9/11
Subject: Re: [PATCH, SMS] Minor misc. fixes
To: Revital Eres revital.e...@linaro.org
2011/9/8 Revital Eres revital.e...@linaro.org
Hello,
The attached patch contains minor
Ok, so this extends the infrastructure to support insns which set an
arbitrary number of registers, but currently specifically handles only
REG_INC situations (which set two registers). I'm not against
{0,1,infinity}, but wonder if this case really deserves the
complexity:
[PATCH, SMS 3/4] Optimize stage count
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01341.html
This patch for minimizing the stage count (which also refactors and
cleans up the code) is approved. Have some minor comments below,
followed by some thoughts for possible follow-up improvements.
[PATCH, SMS 4/4] Misc. fixes
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01342.html
Sure, this is fine.
(Sorry for all the previous '?'s..).
Thanks,
Ayal.
2011/7/20 Revital Eres revital.e...@linaro.org
Hello,
[PATCH, SMS 3/4] Optimize stage count
[PATCH, SMS] Fix calculation of issue_rate
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01344.html
This is ok (with the updated Changelog). Alternatively, we can have a
local variable for holding the issue_rate.
Ayal.
2011/7/20 Revital Eres revital.e...@linaro.org:
Hello,
[PATCH, SMS 3/4]
Revital Eres revital.e...@linaro.org wrote on 14/06/2011 09:27:32 AM:
From: Revital Eres revital.e...@linaro.org
To: Ayal Zaks/Haifa/IBM@IBMIL
Cc: gcc-patches@gcc.gnu.org, Patch Tracking patc...@linaro.org
Date: 14/06/2011 09:27 AM
Subject: Re: [PATCH, SMS 1/4] Fix calculation
Revital Eres revital.e...@linaro.org wrote on 13/06/2011 10:29:06 AM:
From: Revital Eres revital.e...@linaro.org
To: Ayal Zaks/Haifa/IBM@IBMIL
Cc: gcc-patches@gcc.gnu.org, Patch Tracking patc...@linaro.org
Date: 13/06/2011 10:29 AM
Subject: [PATCH, SMS] Fix violation of memory dependence
.
(add_node_to_ps): Update rows_length and call create_ps_insn
without passing row_rest_count.
[attachment patch_row_rest_count_17_5.txt deleted by Ayal
Zaks/Haifa/IBM]
Revital Eres revital.e...@linaro.org wrote on 19/05/2011 07:44:23 AM:
From: Revital Eres revital.e...@linaro.org
To: Ayal Zaks/Haifa/IBM@IBMIL
Cc: gcc-patches@gcc.gnu.org, Patch Tracking patc...@linaro.org
Date: 19/05/2011 07:44 AM
Subject: [PATCH, SMS 2/4] Move the creation of anti-dep edge
OK for mainline?
Yes, this is pretty obvious. (You don't have to change to
prev_nondebug_insn btw).
Ayal.
From: Revital Eres revital.e...@linaro.org
To: Ayal Zaks/Haifa/IBM@IBMIL
Cc: gcc-patches@gcc.gnu.org, Patch Tracking patc...@linaro.org
Date: 08/05/2011 07:37 AM
Subject
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