[committed] Add myself to write after approval
ChangeLog: * MAINTAINERS: Add myself. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 617133447f0..e89833fb83e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -373,6 +373,7 @@ Gabriel Charette Chandra Chavva Dehao Chen Fabien Ch??ne +Monk Chiang Cl??ment Chigot Harshit Chopra Tamar Christina -- 2.40.1
Re: [PATCH] RISC-V: Set require-effective-target rv64 for PR113742
Hi Edwin,
I think just replace to:
/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -march=rv64gc
-mtune=sifive-p600-series" } */
On Thu, Feb 15, 2024 at 7:43 PM Robin Dapp wrote:
> > Ah oops I glanced over the /* { dg-do compile } */part. It should be
> > fine to add '-march=rv64gc' instead then?
>
> Hmm it's a bit tricky. So generally -mcpu=sifive-p670 includes rv64
> but it does not override a previously specified -march=rv32 (that might
> have been added by the test harness or the test target). It looks
> like it does override a (build option and thus not directly specified
> when compiling) --with-arch=rv32.
>
> For now I'd stick with something like -march=rv64gc -mtune=sifive-p670
> (but please check if the original problem does occur with this).
> While you're at it you could delete the redundant '/' in the first
> line.
>
> In general it's a bit counterintuitive a test specifying a
> particular CPU (that supports several extensions) might have
> those overridden when e.g. testing on a rv32 target not supporting
> those. We also do not support cpu names in the march string
> so there is no nice way of overriding previously specified marchs.
>
> Kito: Any idea regarding this? I read in your commit message that
> mcpu has lower precedence than march. Right now that allows us to
> somewhat silently remove architecture options that are specified
> last on the command line.
>
> aarch64 warns in case something is in conflict, maybe we should do
> that as well?
>
> At least I find it a bit annoying that we don't have a way of
> saying:
> "This test always needs to be compiled with all arch features of
> cpu = ..." and rather need to specify -march=rv64gcv_z..._z...
>
> Without having this thought through, can't mcpu be of kind of
> similar precedence to march and we'd let the one specified last
> "win" in case of conflicts? Possibly with an exception for
> the 32/64 bit. Does LLVM not have this problem?
>
> Regards
> Robin
>
>
Re: [PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_AUIPC. [PR113742]
Hi Jeff, I don't have permission to commit, can you push it for me? If you look good to you. > Jeff Law 於 2024年2月14日 凌晨12:03 寫道： > > > >> On 2/4/24 20:20, Monk Chiang wrote: >> gcc/ChangeLog: >> PR target/113742 >> * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix >> recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI. >> gcc/testsuite/ChangeLog: >> * gcc.target/riscv/pr113742.c: New test. > I was going through the patchwork queue after the call today and it looks > like this didn't get pushed. So I took care of it. > > Thanks again, > Jeff
Re: [PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_AUIPC. [PR113742]
Hi Jeff, I don't have permission to commit, can you push it for me? If you look good to you. > Jeff Law 於 2024年2月14日 凌晨12:03 寫道： > > > >> On 2/4/24 20:20, Monk Chiang wrote: >> gcc/ChangeLog: >>PR target/113742 >>* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix >>recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI. >> gcc/testsuite/ChangeLog: >>* gcc.target/riscv/pr113742.c: New test. > I was going through the patchwork queue after the call today and it looks > like this didn't get pushed. So I took care of it. > > Thanks again, > Jeff
Re: [PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_AUIPC. [PR113742]
Yes, this test needs "--enable-checking=rtl" build. On Mon, Feb 5, 2024 at 11:28 AM Jeff Law wrote: > > > On 2/4/24 20:20, Monk Chiang wrote: > > gcc/ChangeLog: > > > > PR target/113742 > > * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix > > recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/pr113742.c: New test. > OK. Presumably this faulted during an --enable-checking=rtl build or > something similar? > > Jeff >
[PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_AUIPC. [PR113742]
gcc/ChangeLog:
PR target/113742
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113742.c: New test.
---
gcc/config/riscv/riscv.cc | 2 +-
gcc/testsuite/gcc.target/riscv/pr113742.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr113742.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 799d7919a4a..4100abc9dd1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8434,7 +8434,7 @@ riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
(lo_sum:DI (reg:DI rD) (const_int IMM12))) */
if (GET_CODE (SET_SRC (prev_set)) == UNSPEC
- && XINT (prev_set, 1) == UNSPEC_AUIPC
+ && XINT (SET_SRC (prev_set), 1) == UNSPEC_AUIPC
&& (GET_CODE (SET_SRC (curr_set)) == LO_SUM
|| (GET_CODE (SET_SRC (curr_set)) == PLUS
&& SMALL_OPERAND (INTVAL (XEXP (SET_SRC (curr_set), 1))
diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c
b/gcc/testsuite/gcc.target/riscv/pr113742.c
new file mode 100644
index 000..ab8934c2a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr113742.c
@@ -0,0 +1,4 @@
+//* { dg-do compile } */
+/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -mcpu=sifive-p670" } */
+
+void foo(void) {}
--
2.40.1
[PATCH 2/2] RISC-V: Add sifive-p450, sifive-p67 to -mcpu
gcc/ChangeLog:
* config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
* doc/invoke.texi (RISC-V Options): Add sifive-p450,
sifive-p670.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-sifive-p450.c: New test.
* gcc.target/riscv/mcpu-sifive-p670.c: New test.
---
gcc/config/riscv/riscv-cores.def | 9 +
gcc/doc/invoke.texi | 3 +-
.../gcc.target/riscv/mcpu-sifive-p450.c | 34
.../gcc.target/riscv/mcpu-sifive-p670.c | 40 +++
4 files changed, 85 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 0785e8f3fbd..57928bccdc8 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -76,6 +76,15 @@ RISCV_CORE("sifive-s76", "rv64imafdc",
"sifive-7-series")
RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b",
"sifive-7-series")
+RISCV_CORE("sifive-p450", "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_"
+ "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
+ "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs",
+ "sifive-p400-series")
+RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_"
+ "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
+ "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_"
+ "zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg",
+ "sifive-p600-series")
RISCV_CORE("thead-c906",
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f8645822ca4..71339b8b30f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30707,7 +30707,8 @@ by particular CPU name.
Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
@samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
@samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
-@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}.
+@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450},
+@samp{sifive-x670}.
@opindex mtune
@item -mtune=@var{processor-string}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
new file mode 100644
index 000..563041821e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=sifive-p450 -mabi=lp64d" } */
+/* SiFive p450 =>
rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs
*/
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_c)\
+ && defined(__riscv_za64rs) \
+ && defined(__riscv_zic64b) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_ziccamoa) \
+ && defined(__riscv_ziccif) \
+ && defined(__riscv_zicclsm) \
+ && defined(__riscv_ziccrse) \
+ && defined(__riscv_zicsr)\
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihintntl)\
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm)\
+ && defined(__riscv_zfhmin) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb) \
+ && defined(__riscv_zbs))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
new file mode 100644
index 000..8dfd490f440
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=sifive-p670 -mabi=lp64d" } */
+/* SiFive p670 =>
rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg
*/
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && (__riscv_flen == 64) \
[PATCH 1/2] RISC-V: Support scheduling for sifive p400 series
Add sifive p400 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p450-470.
gcc/ChangeLog:
* config/riscv/riscv.md: Include sifive-p400.md.
* config/riscv/sifive-p400.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add sifive_p400.
* config/riscv/riscv.cc (sifive_p400_tune_info): New.
* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
* doc/invoke.texi (RISC-V Options): Add sifive-p400-series
---
gcc/config/riscv/riscv-cores.def | 1 +
gcc/config/riscv/riscv-opts.h| 1 +
gcc/config/riscv/riscv.cc| 17 +++
gcc/config/riscv/riscv.h | 1 +
gcc/config/riscv/riscv.md| 3 +-
gcc/config/riscv/sifive-p400.md | 174 +++
gcc/doc/invoke.texi | 4 +-
7 files changed, 198 insertions(+), 3 deletions(-)
create mode 100644 gcc/config/riscv/sifive-p400.md
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index a07a79e2cb7..0785e8f3fbd 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
+RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25951665b13..4edddbadc37 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
enum riscv_microarchitecture_type {
generic,
sifive_7,
+ sifive_p400,
sifive_p600,
generic_ooo
};
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index cead76fe1a2..4b24e4b9a0a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info = {
NULL,/* vector cost */
};
+/* Costs to use when optimizing for Sifive p400 Series. */
+static const struct riscv_tune_param sifive_p400_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
+ 3, /* issue_rate */
+ 4, /* branch_cost */
+ 3, /* memory_cost */
+ 4, /* fmv_cost */
+ true,/*
slow_unaligned_access */
+ false, /* use_divmod_expansion */
+ RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
+ _vector_cost,/* vector cost */
+};
+
/* Costs to use when optimizing for Sifive p600 Series. */
static const struct riscv_tune_param sifive_p600_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index e0cb3ba08d4..669308cc96d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -898,6 +898,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
#define TARGET_SFB_ALU \
((riscv_microarchitecture == sifive_7) \
+ || (riscv_microarchitecture == sifive_p400) \
|| (riscv_microarchitecture == sifive_p600))
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2a164a03dbd..39b29795cd6 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -687,7 +687,7 @@
;; Microarchitectures we know how to tune for.
;; Keep this in sync with enum riscv_microarchitecture.
(define_attr "tune"
- "generic,sifive_7,sifive_p600,generic_ooo"
+ "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo"
(const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
;; Describe a user's asm statement.
@@ -3850,6 +3850,7 @@
(include "pic.md")
(include "generic.md")
(include "sifive-7.md")
+(include "sifive-p400.md")
(include "sifive-p600.md")
(include "thead.md")
(include "generic-ooo.md")
diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md
new file mode 100644
index 000..cc244d3c3e6
--- /dev/null
+++ b/gcc/config/riscv/sifive-p400.md
@@ -0,0 +1,174 @@
+;; Scheduling
[PATCH v2] RISC-V: Add minimal support for 7 new unprivileged extensions
The RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
These extensions don't add any new features but
describe existing features. So this patch only adds parsing.
Za64rs: Reservation set size of 64 bytes
Za128rs: Reservation set size of 128 bytes
Ziccif: Main memory supports instruction fetch with atomicity requirement
Ziccrse: Main memory supports forward progress on LR/SC sequences
Ziccamoa: Main memory supports all atomics in A
Zicclsm: Main memory supports misaligned loads/stores
Zic64b: Cache block size isf 64 bytes
gcc/ChangeLog:
* config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
* config/riscv/riscv.opt: New macro for 7 new unprivileged
extensions.
* doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/za-ext.c: New test.
* gcc.target/riscv/zi-ext.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 14
gcc/config/riscv/riscv.opt | 14
gcc/doc/invoke.texi | 28
gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++
gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +
5 files changed, 102 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6ac0422ac13..631ce8309a0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -247,6 +247,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -276,6 +278,11 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zic64b", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"ziccif", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0},
{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
{"zihpm", ISA_SPEC_CLASS_NONE, 2, 0},
@@ -1494,6 +1501,8 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
{"zicond", _options::x_riscv_zi_subext, MASK_ZICOND},
+ {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
+ {"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
{"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
@@ -1523,6 +1532,11 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
{"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
{"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
+ {"zic64b", _options::x_riscv_zicmo_subext, MASK_ZIC64B},
+ {"ziccamoa", _options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
+ {"ziccif", _options::x_riscv_zicmo_subext, MASK_ZICCIF},
+ {"zicclsm", _options::x_riscv_zicmo_subext, MASK_ZICCLSM},
+ {"ziccrse", _options::x_riscv_zicmo_subext, MASK_ZICCRSE},
{"zve32x", _options::x_target_flags, MASK_VECTOR},
{"zve32f", _options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index b6d8e9a3f74..f6ff70b2b30 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -225,11 +225,25 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
Mask(ZICOND) Var(riscv_zi_subext)
+Mask(ZIC64B) Var(riscv_zi_subext)
+
+Mask(ZICCAMOA)Var(riscv_zi_subext)
+
+Mask(ZICCIF) Var(riscv_zi_subext)
+
+Mask(ZICCLSM) Var(riscv_zi_subext)
+
+Mask(ZICCRSE) Var(riscv_zi_subext)
+
TargetVariable
int riscv_za_subext
Mask(ZAWRS) Var(riscv_za_subext)
+Mask(ZA64RS) Var(riscv_za_subext)
+
+Mask(ZA128RS) Var(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ca2c0e90452..09abd2aef31 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30262,6 +30262,14 @@ Supported extension are listed below:
@tab 1.0
@tab Integer conditional operations extension.
+@item za64rs
+@tab 1.0
+@tab Reservation set size of 64 bytes.
+
+@item za128rs
+@tab 1.0
+@tab Reservation set size of 128 bytes.
+
@item zawrs
@tab 1.0
@tab Wait-on-reservation-set extension.
@@ -30370,6 +30378,26 @@ Supported extension are listed below:
@tab 1.0
@tab Cache-block prefetch extension.
+@item zic64b
+@tab
[PATCH] RISC-V: Add minimal support for 7 new unprivileged extensions
The RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
These extensions don't add any new features but
describe existing features. So this patch only adds parsing.
Za64rs: Reservation set size of 64 bytes
Za128rs: Reservation set size of 128 bytes
Ziccif: Main memory supports instruction fetch with atomicity requirement
Ziccrse: Main memory supports forward progress on LR/SC sequences
Ziccamoa: Main memory supports all atomics in A
Zicclsm: Main memory supports misaligned loads/stores
Zic64b: Cache block size isf 64 bytes
gcc/ChangeLog:
* config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
* config/riscv/riscv.opt: New macro for 7 new unprivileged
extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/za-ext.c: New test.
* gcc.target/riscv/zi-ext.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 14
gcc/config/riscv/riscv.opt | 14
gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++
gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +
4 files changed, 74 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6ac0422ac13..631ce8309a0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -247,6 +247,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -276,6 +278,11 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zic64b", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"ziccif", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0},
{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
{"zihpm", ISA_SPEC_CLASS_NONE, 2, 0},
@@ -1494,6 +1501,8 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
{"zicond", _options::x_riscv_zi_subext, MASK_ZICOND},
+ {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
+ {"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
{"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
@@ -1523,6 +1532,11 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
{"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
{"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
+ {"zic64b", _options::x_riscv_zicmo_subext, MASK_ZIC64B},
+ {"ziccamoa", _options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
+ {"ziccif", _options::x_riscv_zicmo_subext, MASK_ZICCIF},
+ {"zicclsm", _options::x_riscv_zicmo_subext, MASK_ZICCLSM},
+ {"ziccrse", _options::x_riscv_zicmo_subext, MASK_ZICCRSE},
{"zve32x", _options::x_target_flags, MASK_VECTOR},
{"zve32f", _options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index b6d8e9a3f74..f6ff70b2b30 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -225,11 +225,25 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
Mask(ZICOND) Var(riscv_zi_subext)
+Mask(ZIC64B) Var(riscv_zi_subext)
+
+Mask(ZICCAMOA)Var(riscv_zi_subext)
+
+Mask(ZICCIF) Var(riscv_zi_subext)
+
+Mask(ZICCLSM) Var(riscv_zi_subext)
+
+Mask(ZICCRSE) Var(riscv_zi_subext)
+
TargetVariable
int riscv_za_subext
Mask(ZAWRS) Var(riscv_za_subext)
+Mask(ZA64RS) Var(riscv_za_subext)
+
+Mask(ZA128RS) Var(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
diff --git a/gcc/testsuite/gcc.target/riscv/za-ext.c
b/gcc/testsuite/gcc.target/riscv/za-ext.c
new file mode 100644
index 000..126da2fcadd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/za-ext.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_za64rs_za128rs" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_za64rs_za128rs" { target { rv32 } } } */
+
+#ifndef __riscv_za64rs
+#error "Feature macro for 'za64rs' not defined"
+#endif
+
+#ifndef __riscv_za128rs
+#error "Feature macro for 'za128rs' not defined"
+#endif
+
+int
+foo (int a)
+{
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/zi-ext.c
b/gcc/testsuite/gcc.target/riscv/zi-ext.c
new file mode 100644
index 000..65a7acb32af
--- /dev/null
+++
Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series
Hi Juzhe, The vector part is complicated, I will add it last. On Thu, Feb 1, 2024 at 11:08 AM juzhe.zh...@rivai.ai wrote: > Hi, Monk. > > This model doesn't include vector. Will you add vector pipeline in the > followup patches ? > > -- > juzhe.zh...@rivai.ai >
[PATCH v2] RISC-V: Support scheduling for sifive p600 series
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and include sifive-p600.md.
* config/riscv/generic-ooo.md: Update type attribute.
* config/riscv/sifive-7.md: Update type attribute.
* config/riscv/sifive-p600.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add sifive_p600.
* config/riscv/riscv.c (sifive_p600_tune_info): New.
* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
* doc/invoke.texi (RISC-V Options): Add sifive-p600-series
---
gcc/config/riscv/generic-ooo.md | 2 +-
gcc/config/riscv/generic.md | 2 +-
gcc/config/riscv/riscv-cores.def | 1 +
gcc/config/riscv/riscv-opts.h| 1 +
gcc/config/riscv/riscv.cc| 17 +++
gcc/config/riscv/riscv.h | 4 +-
gcc/config/riscv/riscv.md| 19 ++--
gcc/config/riscv/sifive-7.md | 2 +-
gcc/config/riscv/sifive-p600.md | 178 +++
gcc/doc/invoke.texi | 3 +-
10 files changed, 216 insertions(+), 13 deletions(-)
create mode 100644 gcc/config/riscv/sifive-p600.md
diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..a22f8a3e079 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -127,7 +127,7 @@
(define_insn_reservation "generic_ooo_fcvt" 3
(and (eq_attr "tune" "generic_ooo")
- (eq_attr "type" "fcvt"))
+ (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
"generic_ooo_issue,generic_ooo_fxu")
(define_insn_reservation "generic_ooo_fcmp" 2
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..3f0eaa2ea08 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -42,7 +42,7 @@
(define_insn_reservation "generic_xfer" 3
(and (eq_attr "tune" "generic")
- (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
+ (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
"alu")
(define_insn_reservation "generic_branch" 1
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index b30f4dfb08e..a07a79e2cb7 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
+RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1500f8811ef..25951665b13 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
enum riscv_microarchitecture_type {
generic,
sifive_7,
+ sifive_p600,
generic_ooo
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7b6111aa545..476533395b5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info = {
NULL,/* vector cost */
};
+/* Costs to use when optimizing for Sifive p600 Series. */
+static const struct riscv_tune_param sifive_p600_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
+ 4, /* issue_rate */
+ 4, /* branch_cost */
+ 3, /* memory_cost */
+ 4, /* fmv_cost */
+ true,/*
slow_unaligned_access */
+ false, /* use_divmod_expansion */
+ RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
+ _vector_cost,/* vector cost */
+};
+
/* Costs to use when optimizing for T-HEAD c906. */
static const struct riscv_tune_param thead_c906_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
diff --git a/gcc/config/riscv/riscv.h
Re: [PATCH] RISC-V: Support scheduling for sifive p600 series
Thanks, I will push a V2 patch, to fix the typo and add a vector cost model
for p600 series.
About block the div units, I decided to use your suggestion. The P600
series
divider is 4 bits per cycle. So blocking 3-5 cycles is enough.
On Thu, Feb 1, 2024 at 9:50 AM Edwin Lu wrote:
> I recently committed changes modifying the scheduling reservations. Some
> things may need to be retested with the newly enabled asserts.
>
> Edwin
>
> On 1/31/2024 1:40 AM, Monk Chiang wrote:
> > Add sifive p600 series scheduler module. For more information
> > see https://www.sifive.com/cores/performance-p650-670.
> > Add sifive-p650, sifive-p670 for mcpu option will come in separate
> patches.
> >
> > gcc/ChangeLog:
> > * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
> > attribute, and include sifive-p600.md.
> > * config/riscv/generic-ooo.md: Update type attribute.
> > * config/riscv/sifive-7.md: Update type attribute.
> > * config/riscv/sifive-p600.md: New file.
> > * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
> > * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
> > Add sifive_p600.
> > * config/riscv/riscv.c (sifive_p600_tune_info): New.
> > * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
> > * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
> > ---
> > gcc/config/riscv/generic-ooo.md | 2 +-
> > gcc/config/riscv/generic.md | 2 +-
> > gcc/config/riscv/riscv-cores.def | 1 +
> > gcc/config/riscv/riscv-opts.h| 1 +
> > gcc/config/riscv/riscv.cc| 17 +++
> > gcc/config/riscv/riscv.h | 4 +-
> > gcc/config/riscv/riscv.md| 19 ++--
> > gcc/config/riscv/sifive-7.md | 2 +-
> > gcc/config/riscv/sifive-p600.md | 174 +++
> > gcc/doc/invoke.texi | 3 +-
> > 10 files changed, 212 insertions(+), 13 deletions(-)
> > create mode 100644 gcc/config/riscv/sifive-p600.md
> >
> > diff --git a/gcc/config/riscv/generic-ooo.md
> b/gcc/config/riscv/generic-ooo.md
> > index 421a7bb929d..a22f8a3e079 100644
> > --- a/gcc/config/riscv/generic-ooo.md
> > +++ b/gcc/config/riscv/generic-ooo.md
> > @@ -127,7 +127,7 @@
> >
> > (define_insn_reservation "generic_ooo_fcvt" 3
> > (and (eq_attr "tune" "generic_ooo")
> > - (eq_attr "type" "fcvt"))
> > + (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
> > "generic_ooo_issue,generic_ooo_fxu")
> >
> > (define_insn_reservation "generic_ooo_fcmp" 2
> > diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
> > index b99ae345bb3..3f0eaa2ea08 100644
> > --- a/gcc/config/riscv/generic.md
> > +++ b/gcc/config/riscv/generic.md
> > @@ -42,7 +42,7 @@
> >
> > (define_insn_reservation "generic_xfer" 3
> > (and (eq_attr "tune" "generic")
> > - (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
> > + (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
> > "alu")
> >
> > (define_insn_reservation "generic_branch" 1
> > diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> > index b30f4dfb08e..a07a79e2cb7 100644
> > --- a/gcc/config/riscv/riscv-cores.def
> > +++ b/gcc/config/riscv/riscv-cores.def
> > @@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
> > RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
> > RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
> > RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
> > +RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
> > RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
> > RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
> > RISCV_TUNE("size", generic, optimize_size_tune_info)
> > diff --git a/gcc/config/riscv/riscv-opts.h
> b/gcc/config/riscv/riscv-opts.h
> > index 1500f8811ef..25951665b13 100644
> > --- a/gcc/config/riscv/riscv-opts.h
> > +++ b/gcc/config/riscv/riscv-opts.h
> > @@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
> > enum riscv_microarchitecture_type {
> > generic,
> > sifive_7,
> > + sifive_p600,
> > generic_ooo
> > };
> > extern enum riscv_m
[PATCH] RISC-V: Support scheduling for sifive p600 series
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and include sifive-p600.md.
* config/riscv/generic-ooo.md: Update type attribute.
* config/riscv/sifive-7.md: Update type attribute.
* config/riscv/sifive-p600.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add sifive_p600.
* config/riscv/riscv.c (sifive_p600_tune_info): New.
* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
* doc/invoke.texi (RISC-V Options): Add sifive-p600-series
---
gcc/config/riscv/generic-ooo.md | 2 +-
gcc/config/riscv/generic.md | 2 +-
gcc/config/riscv/riscv-cores.def | 1 +
gcc/config/riscv/riscv-opts.h| 1 +
gcc/config/riscv/riscv.cc| 17 +++
gcc/config/riscv/riscv.h | 4 +-
gcc/config/riscv/riscv.md| 19 ++--
gcc/config/riscv/sifive-7.md | 2 +-
gcc/config/riscv/sifive-p600.md | 174 +++
gcc/doc/invoke.texi | 3 +-
10 files changed, 212 insertions(+), 13 deletions(-)
create mode 100644 gcc/config/riscv/sifive-p600.md
diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..a22f8a3e079 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -127,7 +127,7 @@
(define_insn_reservation "generic_ooo_fcvt" 3
(and (eq_attr "tune" "generic_ooo")
- (eq_attr "type" "fcvt"))
+ (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
"generic_ooo_issue,generic_ooo_fxu")
(define_insn_reservation "generic_ooo_fcmp" 2
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..3f0eaa2ea08 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -42,7 +42,7 @@
(define_insn_reservation "generic_xfer" 3
(and (eq_attr "tune" "generic")
- (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
+ (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
"alu")
(define_insn_reservation "generic_branch" 1
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index b30f4dfb08e..a07a79e2cb7 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
+RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1500f8811ef..25951665b13 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
enum riscv_microarchitecture_type {
generic,
sifive_7,
+ sifive_p600,
generic_ooo
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7b6111aa545..92d6fd5cf47 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info = {
NULL,/* vector cost */
};
+/* Costs to use when optimizing for Sifive p600 Series. */
+static const struct riscv_tune_param sifive_p600_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
+ 4, /* issue_rate */
+ 4, /* branch_cost */
+ 3, /* memory_cost */
+ 4, /* fmv_cost */
+ true,/*
slow_unaligned_access */
+ false, /* use_divmod_expansion */
+ RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
+ NULL,/* vector cost */
+};
+
/* Costs to use when optimizing for T-HEAD c906. */
static const struct riscv_tune_param thead_c906_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
diff --git a/gcc/config/riscv/riscv.h
[PATCH v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095]
Since the match.pd transforms (zero_one == 0) ? y : z y,
into ((typeof(y))zero_one * z) y. Add splitters to recongize
this expression to generate SFB instructions.
gcc/ChangeLog:
PR target/113095
* config/riscv/sfb.md: New splitters to rewrite single bit
sign extension as the condition to SFB instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sfb.c: New test.
* gcc.target/riscv/pr113095.c: New test.
---
gcc/config/riscv/sfb.md | 32 +++
gcc/testsuite/gcc.target/riscv/pr113095.c | 21 +++
gcc/testsuite/gcc.target/riscv/sfb.c | 24 +
3 files changed, 77 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr113095.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sfb.c
diff --git a/gcc/config/riscv/sfb.md b/gcc/config/riscv/sfb.md
index 52af4b17d46..5a510fe9f09 100644
--- a/gcc/config/riscv/sfb.md
+++ b/gcc/config/riscv/sfb.md
@@ -35,3 +35,35 @@
[(set_attr "length" "8")
(set_attr "type" "sfb_alu")
(set_attr "mode" "")])
+
+;; Combine creates this form ((typeof(y))zero_one * z) y
+;; for SiFive short forward branches.
+
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_SFB_ALU"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup
2)))
+ (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0))
+ (match_dup 3)
+ (const_int 0)))])
+
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0))
+ (match_dup 3)
+ (const_int 0)))]
+{
+ operands[2] = GEN_INT (1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/pr113095.c
b/gcc/testsuite/gcc.target/riscv/pr113095.c
new file mode 100644
index 000..04321b58dc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr113095.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" {
target { rv32 } } } */
+/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -mtune=sifive-7-series" {target
{ rv64 } } } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned short __attribute__ ((noinline, noclone))
+foo (unsigned short x) {
+ if (x == 1)
+x ^= 0x4002;
+
+ return x;
+}
+
+int main () {
+ if (foo(1) != 0x4003)
+abort ();
+
+ exit(0);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sfb.c
b/gcc/testsuite/gcc.target/riscv/sfb.c
new file mode 100644
index 000..22f164051f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sfb.c
@@ -0,0 +1,24 @@
+//* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */
+
+int f1(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) == 0) ? y : z ^ y;
+}
+
+int f2(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) != 0) ? z ^ y : y;
+}
+
+int f3(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) == 0) ? y : z | y;
+}
+
+int f4(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) != 0) ? z | y : y;
+}
+/* { dg-final { scan-assembler-times "bne" 4 } } */
+/* { dg-final { scan-assembler-times "movcc" 4 } } */
--
2.40.1
Re: [PATCH v2] RISC-V: Add split pattern to generate SFB instructions. [PR113095]
Thank you for your help. I will update the test case.
I test on the Coremark and have 5% improvement on the SiFive CPU.
On Tue, Jan 23, 2024 at 12:24 PM Jeff Law wrote:
>
>
> On 1/21/24 23:12, Monk Chiang wrote:
> > Since the match.pd transforms (zero_one == 0) ? y : z y,
> > into ((typeof(y))zero_one * z) y. Add splitters to recongize
> > this expression to generate SFB instructions.
> >
> > gcc/ChangeLog:
> > PR target/113095
> > * config/riscv/sfb.md: New splitters to rewrite single bit
> > sign extension as the condition to SFB instructions.
> >
> > gcc/testsuite/ChangeLog:
> > * gcc.target/riscv/sfb.c: New test.
> > * gcc.target/riscv/pr113095.c: New test.
> So the 113095 test is going to fail to link on rv64 causing a testsuite
> failure. I would suggest it have these dg-options lines instead of the
> one you provided:
>
> /* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series"
> { target { rv32 } } } */
> /* { dg-options "-O2 -march=rv64gc -mabi=lp64d -mtune=sifive-7-series" {
> target { rv64 } } } */
>
>
> A similar change is not strictly needed for the new sfb.c test since it
> only does a compile (but not a link) test.
>
> You still didn't indicating what testing was done for this patch.
> Standard practice is to build the compiler and run the testsuite with
> and without your change and verify there are no regressions. Ideally
> new tests should pass as well.
>
> I made the change above locally to pr113095.c to fix those failures on
> rv64. So this is OK with the adjustment to the dg-options line in the
> new pr113095 test.
>
> Jeff
>
>
[PATCH v2] RISC-V: Add split pattern to generate SFB instructions. [PR113095]
Since the match.pd transforms (zero_one == 0) ? y : z y,
into ((typeof(y))zero_one * z) y. Add splitters to recongize
this expression to generate SFB instructions.
gcc/ChangeLog:
PR target/113095
* config/riscv/sfb.md: New splitters to rewrite single bit
sign extension as the condition to SFB instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sfb.c: New test.
* gcc.target/riscv/pr113095.c: New test.
---
gcc/config/riscv/sfb.md | 32 +++
gcc/testsuite/gcc.target/riscv/pr113095.c | 20 ++
gcc/testsuite/gcc.target/riscv/sfb.c | 24 +
3 files changed, 76 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr113095.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sfb.c
diff --git a/gcc/config/riscv/sfb.md b/gcc/config/riscv/sfb.md
index 8ab747142c8..bfd229e3d09 100644
--- a/gcc/config/riscv/sfb.md
+++ b/gcc/config/riscv/sfb.md
@@ -35,3 +35,35 @@
[(set_attr "length" "8")
(set_attr "type" "sfb_alu")
(set_attr "mode" "")])
+
+;; Combine creates this form ((typeof(y))zero_one * z) y
+;; for SiFive short forward branches.
+
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_SFB_ALU"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup
2)))
+ (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0))
+ (match_dup 3)
+ (const_int 0)))])
+
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0))
+ (match_dup 3)
+ (const_int 0)))]
+{
+ operands[2] = GEN_INT (1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/pr113095.c
b/gcc/testsuite/gcc.target/riscv/pr113095.c
new file mode 100644
index 000..50dd6be11c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr113095.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned short __attribute__ ((noinline, noclone))
+foo (unsigned short x) {
+ if (x == 1)
+x ^= 0x4002;
+
+ return x;
+}
+
+int main () {
+ if (foo(1) != 0x4003)
+abort ();
+
+ exit(0);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sfb.c
b/gcc/testsuite/gcc.target/riscv/sfb.c
new file mode 100644
index 000..22f164051f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sfb.c
@@ -0,0 +1,24 @@
+//* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */
+
+int f1(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) == 0) ? y : z ^ y;
+}
+
+int f2(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) != 0) ? z ^ y : y;
+}
+
+int f3(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) == 0) ? y : z | y;
+}
+
+int f4(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) != 0) ? z | y : y;
+}
+/* { dg-final { scan-assembler-times "bne" 4 } } */
+/* { dg-final { scan-assembler-times "movcc" 4 } } */
--
2.40.1
[PATCH] RISC-V: Add split pattern to generate SFB instructions. [PR113095]
Since the match.pd transforms (zero_one == 0) ? y : z y,
into ((typeof(y))zero_one * z) y. Add splitters to recongize
this expression to generate SFB instructions.
gcc/ChangeLog:
PR target/113095
* config/riscv/sfb.md: New splitters to rewrite single bit
sign extension as the condition to SFB instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sfb.c: New test.
---
gcc/config/riscv/sfb.md | 32
gcc/testsuite/gcc.target/riscv/sfb.c | 24 +
2 files changed, 56 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sfb.c
diff --git a/gcc/config/riscv/sfb.md b/gcc/config/riscv/sfb.md
index 8ab747142c8..520b12c22f9 100644
--- a/gcc/config/riscv/sfb.md
+++ b/gcc/config/riscv/sfb.md
@@ -35,3 +35,35 @@
[(set_attr "length" "8")
(set_attr "type" "sfb_alu")
(set_attr "mode" "")])
+
+;; Combine creates this form ((typeof(y))zero_one * z) y
+;; for SiFive short forward branches.
+
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_SFB_ALU"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup
2)))
+ (set (match_dup 0) (if_then_else:X (ne:X (match_dup 4) (const_int 0))
+ (match_dup 3)
+ (const_int 0)))])
+
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (if_then_else:X (ne:X (match_dup 4) (const_int 0))
+ (match_dup 3)
+ (const_int 0)))]
+{
+ operands[2] = GEN_INT (1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/sfb.c
b/gcc/testsuite/gcc.target/riscv/sfb.c
new file mode 100644
index 000..22f164051f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sfb.c
@@ -0,0 +1,24 @@
+//* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */
+
+int f1(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) == 0) ? y : z ^ y;
+}
+
+int f2(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) != 0) ? z ^ y : y;
+}
+
+int f3(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) == 0) ? y : z | y;
+}
+
+int f4(unsigned int x, unsigned int y, unsigned int z)
+{
+ return ((x & 1) != 0) ? z | y : y;
+}
+/* { dg-final { scan-assembler-times "bne" 4 } } */
+/* { dg-final { scan-assembler-times "movcc" 4 } } */
--
2.40.1
Re: [PATCH] match: Do not select to branchless expression when target has movcc pattern [PR113095]
Thanks for your advice!! I agree it should be fixed in the RISC-V backend when expansion. On Wed, Jan 17, 2024 at 10:37 PM Jeff Law wrote: > > > On 1/17/24 05:14, Richard Biener wrote: > > On Wed, 17 Jan 2024, Monk Chiang wrote: > > > >> This allows the backend to generate movcc instructions, if target > >> machine has movcc pattern. > >> > >> branchless-cond.c needs to be updated since some target machines have > >> conditional move instructions, and the experssion will not change to > >> branchless expression. > > > > While I agree this pattern should possibly be applied during RTL > > expansion or instruction selection on x86 which also has movcc > > the multiplication is cheaper. So I don't think this isn't the way to > go. > > > > I'd rather revert the change than trying to "fix" it this way? > WRT reverting -- the patch in question's sole purpose was to enable > branchless sequences for that very same code. Reverting would regress > performance on a variety of micro-architectures. IIUC, the issue is > that the SiFive part in question has a fusion which allows it to do the > branchy sequence cheaply. > > ISTM this really needs to be addressed during expansion and most likely > with a RISC-V target twiddle for the micro-archs which have > short-forward-branch optimizations. > > jeff >
[PATCH] match: Do not select to branchless expression when target has movcc pattern [PR113095]
This allows the backend to generate movcc instructions, if target
machine has movcc pattern.
branchless-cond.c needs to be updated since some target machines have
conditional move instructions, and the experssion will not change to
branchless expression.
gcc/ChangeLog:
PR target/113095
* match.pd (`(zero_one == 0) ? y : z y`,
`(zero_one != 0) ? z y : y`): Do not match to branchless
expression, if target machine has conditional move pattern.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/branchless-cond.c: Update testcase.
---
gcc/match.pd | 30 +--
.../gcc.dg/tree-ssa/branchless-cond.c | 6 ++--
2 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/gcc/match.pd b/gcc/match.pd
index e42ecaf9ec7..a1f90b1cd41 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -4231,7 +4231,20 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(if (INTEGRAL_TYPE_P (type)
&& TYPE_PRECISION (type) > 1
&& (INTEGRAL_TYPE_P (TREE_TYPE (@0
- (op (mult (convert:type @0) @2) @1
+ (with {
+ bool can_movecc_p = false;
+ if (can_conditionally_move_p (TYPE_MODE (type)))
+ can_movecc_p = true;
+
+ /* Some target only support word_mode for movcc pattern, if type can
+extend to word_mode then use conditional move. Even if there is a
+extend instruction, the cost is lower than branchless. */
+ if (can_extend_p (word_mode, TYPE_MODE (type), TYPE_UNSIGNED (type))
+ && can_conditionally_move_p (word_mode))
+ can_movecc_p = true;
+}
+(if (!can_movecc_p)
+ (op (mult (convert:type @0) @2) @1))
/* (zero_one != 0) ? z y : y -> ((typeof(y))zero_one * z) y */
(for op (bit_xor bit_ior plus)
@@ -4243,7 +4256,20 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(if (INTEGRAL_TYPE_P (type)
&& TYPE_PRECISION (type) > 1
&& (INTEGRAL_TYPE_P (TREE_TYPE (@0
- (op (mult (convert:type @0) @2) @1
+ (with {
+ bool can_movecc_p = false;
+ if (can_conditionally_move_p (TYPE_MODE (type)))
+ can_movecc_p = true;
+
+ /* Some target only support word_mode for movcc pattern, if type can
+extend to word_mode then use conditional move. Even if there is a
+extend instruction, the cost is lower than branchless. */
+ if (can_extend_p (word_mode, TYPE_MODE (type), TYPE_UNSIGNED (type))
+ && can_conditionally_move_p (word_mode))
+ can_movecc_p = true;
+}
+(if (!can_movecc_p)
+ (op (mult (convert:type @0) @2) @1))
/* ?: Value replacement. */
/* a == 0 ? b : b + a -> b + a */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/branchless-cond.c
b/gcc/testsuite/gcc.dg/tree-ssa/branchless-cond.c
index e063dc4bb5f..c002ed97364 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/branchless-cond.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/branchless-cond.c
@@ -21,6 +21,6 @@ int f4(unsigned int x, unsigned int y, unsigned int z)
return ((x & 1) != 0) ? z | y : y;
}
-/* { dg-final { scan-tree-dump-times " \\\*" 4 "optimized" } } */
-/* { dg-final { scan-tree-dump-times " & " 4 "optimized" } } */
-/* { dg-final { scan-tree-dump-not "if " "optimized" } } */
+/* { dg-final { scan-tree-dump-times " \\\*" 4 "optimized" { xfail {
"aarch64*-*-* alpha*-*-* bfin*-*-* epiphany-*-* i?86-*-* x86_64-*-* nds32*-*-*"
} } } } */
+/* { dg-final { scan-tree-dump-times " & " 4 "optimized" { xfail {
"aarch64*-*-* alpha*-*-* bfin*-*-* epiphany-*-* i?86-*-* x86_64-*-* nds32*-*-*"
} } } } */
+/* { dg-final { scan-tree-dump-not "if " "optimized" { xfail { "aarch64*-*-*
alpha*-*-* bfin*-*-* epiphany-*-* i?86-*-* x86_64-*-* nds32*-*-*" } } } } */
--
2.40.1
[PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand):
Add 'N' for print a non-temporal locality hints instruction.
* config/riscv/riscv.md (prefetch):
Add NTLH instruction for prefetch.r and prefetch.w.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/prefetch-zihintntl.c: New test.
---
gcc/config/riscv/riscv.cc | 22 +++
gcc/config/riscv/riscv.md | 10 ++---
.../gcc.target/riscv/prefetch-zihintntl.c | 20 +
3 files changed, 49 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 706c18416db..42f80088bab 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4532,6 +4532,7 @@ riscv_memmodel_needs_amo_release (enum memmodel model)
'A' Print the atomic operation suffix for memory model OP.
'I' Print the LR suffix for memory model OP.
'J' Print the SC suffix for memory model OP.
+ 'N' Print a non-temporal locality hints instruction.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
@@ -4718,6 +4719,27 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
}
+case 'N':
+ {
+ const char *ntl_hint = NULL;
+ switch (INTVAL (op))
+ {
+ case 0:
+ ntl_hint = "ntl.all";
+ break;
+ case 1:
+ ntl_hint = "ntl.pall";
+ break;
+ case 2:
+ ntl_hint = "ntl.p1";
+ break;
+ }
+
+ if (ntl_hint)
+ asm_fprintf (file, "%s\n\t", ntl_hint);
+ break;
+ }
+
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 7988026d129..3357c981b5d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3256,11 +3256,15 @@
{
switch (INTVAL (operands[1]))
{
-case 0: return "prefetch.r\t%a0";
-case 1: return "prefetch.w\t%a0";
+case 0: return TARGET_ZIHINTNTL ? "%N2prefetch.r\t%a0" : "prefetch.r\t%a0";
+case 1: return TARGET_ZIHINTNTL ? "%N2prefetch.w\t%a0" : "prefetch.w\t%a0";
default: gcc_unreachable ();
}
-})
+}
+ [(set (attr "length") (if_then_else (and (match_test "TARGET_ZIHINTNTL")
+ (match_test "INTVAL (operands[2]) !=
3"))
+ (const_string "8")
+ (const_string "4")))])
(define_insn "riscv_prefetchi_"
[(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
new file mode 100644
index 000..78a3afe6833
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
@@ -0,0 +1,20 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+/* { dg-final { scan-assembler-times "ntl.all" 2 } } */
+/* { dg-final { scan-assembler-times "ntl.pall" 2 } } */
+/* { dg-final { scan-assembler-times "ntl.p1" 2 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
--
2.40.1
[PATCH 1/2] RISC-V: Recognized zihintntl extensions
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zihintntl item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro.
(TARGET_ZIHINTNTL): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-22.c: New test.
* gcc.target/riscv/predef-28.c: New test.
---
gcc/common/config/riscv/riscv-common.cc| 4 ++
gcc/config/riscv/riscv-opts.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++
gcc/testsuite/gcc.target/riscv/predef-28.c | 47 ++
4 files changed, 58 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-28.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6091d8f281b..28c8f0c1489 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -206,6 +206,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1267,6 +1269,8 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zksh", _options::x_riscv_zk_subext, MASK_ZKSH},
{"zkt",_options::x_riscv_zk_subext, MASK_ZKT},
+ {"zihintntl", _options::x_riscv_zi_subext, MASK_ZIHINTNTL},
+
{"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
{"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
{"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cfcf608ea62..beee241aa1b 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -101,9 +101,11 @@ enum riscv_entity
#define MASK_ZICSR(1 << 0)
#define MASK_ZIFENCEI (1 << 1)
+#define MASK_ZIHINTNTL (1 << 2)
#define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
+#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
#define MASK_ZAWRS (1 << 0)
#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c
b/gcc/testsuite/gcc.target/riscv/arch-22.c
new file mode 100644
index 000..cdc18e13d0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-28.c
b/gcc/testsuite/gcc.target/riscv/predef-28.c
new file mode 100644
index 000..81fdad571e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-28.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_zihintntl)
+#error "__riscv_zihintntl"
+#endif
+
+ return 0;
+}
--
2.40.1
[PATCH] RISC-V: Remove unnecessary register class.
Avoid VL_REGS, VTYPE_REGS join register allocation.
gcc/ChangeLog:
* config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
* config/riscv/riscv.cc: Ditto.
---
gcc/config/riscv/riscv.cc | 8 +---
gcc/config/riscv/riscv.h | 6 --
2 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 209d9a53e7b..3b7804b7501 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -293,7 +293,7 @@ const enum reg_class
riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
FP_REGS, FP_REGS,FP_REGS,FP_REGS,
FP_REGS, FP_REGS,FP_REGS,FP_REGS,
FP_REGS, FP_REGS,FP_REGS,FP_REGS,
- FRAME_REGS, FRAME_REGS, VL_REGS,VTYPE_REGS,
+ FRAME_REGS, FRAME_REGS, NO_REGS,NO_REGS,
NO_REGS, NO_REGS,NO_REGS,NO_REGS,
NO_REGS, NO_REGS,NO_REGS,NO_REGS,
NO_REGS, NO_REGS,NO_REGS,NO_REGS,
@@ -5831,12 +5831,6 @@ riscv_class_max_nregs (reg_class_t rclass, machine_mode
mode)
if (reg_class_subset_p (rclass, V_REGS))
return riscv_hard_regno_nregs (V_REG_FIRST, mode);
- if (reg_class_subset_p (rclass, VL_REGS))
-return 1;
-
- if (reg_class_subset_p (rclass, VTYPE_REGS))
-return 1;
-
return 0;
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 0ab739bd6eb..02e1224c3cd 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -462,8 +462,6 @@ enum reg_class
GR_REGS, /* integer registers */
FP_REGS, /* floating-point registers */
FRAME_REGS, /* arg pointer and frame pointer */
- VL_REGS, /* vl register */
- VTYPE_REGS, /* vtype register */
VM_REGS, /* v0.t registers */
VD_REGS, /* vector registers except v0.t */
V_REGS, /* vector registers */
@@ -487,8 +485,6 @@ enum reg_class
"GR_REGS", \
"FP_REGS", \
"FRAME_REGS",
\
- "VL_REGS", \
- "VTYPE_REGS",
\
"VM_REGS", \
"VD_REGS", \
"V_REGS",\
@@ -514,8 +510,6 @@ enum reg_class
{ 0x, 0x, 0x, 0x }, /* GR_REGS */
\
{ 0x, 0x, 0x, 0x }, /* FP_REGS */
\
{ 0x, 0x, 0x0003, 0x }, /* FRAME_REGS */
\
- { 0x, 0x, 0x0004, 0x }, /* VL_REGS */
\
- { 0x, 0x, 0x0008, 0x }, /* VTYPE_REGS */
\
{ 0x, 0x, 0x, 0x0001 }, /* V0_REGS */
\
{ 0x, 0x, 0x, 0xfffe }, /* VNoV0_REGS */
\
{ 0x, 0x, 0x, 0x }, /* V_REGS */
\
--
2.37.2
[PATCH] RISC-V: Recognized Svinval and Svnapot extensions
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add svinval and svnapot extension.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_SVINVAL): New.
(MASK_SVNAPOT): Ditto.
(TARGET_SVINVAL): Ditto.
(TARGET_SVNAPOT): Ditto.
* config/riscv/riscv.opt (riscv_sv_subext): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-23.c:New.
* gcc.target/riscv/predef-24.c:Ditto.
---
gcc/common/config/riscv/riscv-common.cc| 6 +++
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.opt | 3 ++
gcc/testsuite/gcc.target/riscv/predef-23.c | 47 ++
gcc/testsuite/gcc.target/riscv/predef-24.c | 47 ++
5 files changed, 109 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-24.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index dead3802f83..a5fe782bb61 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -202,6 +202,9 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
+
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
@@ -1226,6 +1229,9 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zmmul", _options::x_riscv_zm_subext, MASK_ZMMUL},
+ {"svinval", _options::x_riscv_sv_subext, MASK_SVINVAL},
+ {"svnapot", _options::x_riscv_sv_subext, MASK_SVNAPOT},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 55e0bc0a0e9..63ac56a8ca0 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -162,6 +162,12 @@ enum stack_protector_guard {
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
+#define MASK_SVINVAL (1 << 0)
+#define MASK_SVNAPOT (1 << 1)
+
+#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
+#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
+
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN. */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 8923a11a97d..949311775c1 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -224,6 +224,9 @@ int riscv_zf_subext
TargetVariable
int riscv_zm_subext
+TargetVariable
+int riscv_sv_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/predef-23.c
b/gcc/testsuite/gcc.target/riscv/predef-23.c
new file mode 100644
index 000..64bde17efa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-23.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svinval -mabi=lp64 -mcmodel=medlow
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c) || (__riscv_c != (2 * 1000 * 1000))
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a) || (__riscv_a != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m) || (__riscv_m != (2 * 1000 * 1000))
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f) || (__riscv_f != (2 * 1000 * 1000 + 2 * 1000))
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d) || (__riscv_d != (2 * 1000 * 1000 + 2 * 1000))
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_svinval)
+#error "__riscv_svinval"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-24.c
b/gcc/testsuite/gcc.target/riscv/predef-24.c
new file mode 100644
index 000..2b51a19eacd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-24.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svnapot -mabi=lp64 -mcmodel=medlow
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c) || (__riscv_c != (2 * 1000 * 1000))
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a) || (__riscv_a != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m)
[PATCH] RISC-V: Add type attribute for atomic instructions.
gcc/ChangeLog: * config/riscv/riscv.md: Add atomic type attribute. * config/riscv/sync.md: Add atomic type for atomic instructions. --- gcc/config/riscv/riscv.md | 2 +- gcc/config/riscv/sync.md | 15 ++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b3654915fde..9384ced0447 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -317,7 +317,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, + atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 7deb290d9dc..449f275e6a2 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -62,7 +62,8 @@ UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" "%F2amoswap.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 8))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") @@ -73,7 +74,8 @@ UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" "%F2amo.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 8))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=") @@ -86,7 +88,8 @@ UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" "%F3amo.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 8))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=") @@ -98,7 +101,8 @@ (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" "%F3amoswap.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 8))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=") @@ -112,7 +116,8 @@ (clobber (match_scratch:GPR 6 "="))] "TARGET_ATOMIC" "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" - [(set (attr "length") (const_int 20))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 20))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output -- 2.37.2
[PATCH v2] PR target/97682 - Fix to reuse t1 register between call address and epilogue.
- When expanding the call pattern, choose t1 register be a jump register.
Epilogue also uses a t1 register to adjust Stack point. The call pattern
and epilogue will initial t1 twice, if both are generated in the same
function. The call pattern will emit 'la t1,symbol' and 'jalr
t1'instructions.
Epilogue also emits 'li t1,4096' and 'addi sp,sp,t1' instructions.
But li and addi instructions will be placed between la and jalr
instructions.
The la instruction will be removed by some optimizations,
because t1 register define twice, the first define instruction look
likes duplicate.
- To resolve this issue, Prologue and Epilogue use the t0 register
be a temporary register, the call pattern use the t1 register be
a temporary register.
gcc/ChangeLog:
PR target/97682
* config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Change register to
t0.
(RISCV_CALL_ADDRESS_TEMP_REGNUM): New Marco, define t1 register.
(RISCV_CALL_ADDRESS_TEMP): Use it for call instructions.
* config/riscv/riscv.c (riscv_legitimize_call_address): Use
RISCV_CALL_ADDRESS_TEMP.
(riscv_compute_frame_info): Change temporary register to t0 form t1.
(riscv_trampoline_init): Adjust comment.
gcc/testsuite/ChangeLog
PR target/97682
* g++.target/riscv/pr97682.C: New test.
* gcc.target/riscv/interrupt-3.c: Check register for t0.
* gcc.target/riscv/interrupt-4.c: Likewise.
---
gcc/config/riscv/riscv.c | 23 +--
gcc/config/riscv/riscv.h | 6 +-
gcc/testsuite/g++.target/riscv/pr97682.C | 160 +++
gcc/testsuite/gcc.target/riscv/interrupt-3.c | 4 +-
gcc/testsuite/gcc.target/riscv/interrupt-4.c | 4 +-
5 files changed, 181 insertions(+), 16 deletions(-)
create mode 100644 gcc/testsuite/g++.target/riscv/pr97682.C
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 989a9f15250..35029e7b435 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3110,7 +3110,7 @@ riscv_legitimize_call_address (rtx addr)
{
if (!call_insn_operand (addr, VOIDmode))
{
- rtx reg = RISCV_PROLOGUE_TEMP (Pmode);
+ rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode);
riscv_emit_move (reg, addr);
return reg;
}
@@ -3707,18 +3707,18 @@ riscv_compute_frame_info (void)
{
struct riscv_frame_info *frame;
HOST_WIDE_INT offset;
- bool interrupt_save_t1 = false;
+ bool interrupt_save_prologue_temp = false;
unsigned int regno, i, num_x_saved = 0, num_f_saved = 0;
frame = >machine->frame;
/* In an interrupt function, if we have a large frame, then we need to
- save/restore t1. We check for this before clearing the frame struct. */
+ save/restore t0. We check for this before clearing the frame struct. */
if (cfun->machine->interrupt_handler_p)
{
HOST_WIDE_INT step1 = riscv_first_stack_step (frame);
if (! SMALL_OPERAND (frame->total_size - step1))
- interrupt_save_t1 = true;
+ interrupt_save_prologue_temp = true;
}
memset (frame, 0, sizeof (*frame));
@@ -3728,7 +3728,8 @@ riscv_compute_frame_info (void)
/* Find out which GPRs we need to save. */
for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (riscv_save_reg_p (regno)
- || (interrupt_save_t1 && (regno == T1_REGNUM)))
+ || (interrupt_save_prologue_temp
+ && (regno == RISCV_PROLOGUE_TEMP_REGNUM)))
frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
/* If this function calls eh_return, we must also save and restore the
@@ -4902,9 +4903,9 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
/* lui t2, hi(chain)
-lui t1, hi(func)
+lui t0, hi(func)
addit2, t2, lo(chain)
-jr r1, lo(func)
+jr t0, lo(func)
*/
unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code;
unsigned HOST_WIDE_INT lo_chain_code, lo_func_code;
@@ -4929,7 +4930,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
mem = adjust_address (m_tramp, SImode, 0);
riscv_emit_move (mem, lui_hi_chain);
- /* Gen lui t1, hi(func). */
+ /* Gen lui t0, hi(func). */
rtx hi_func = riscv_force_binary (SImode, PLUS, target_function,
fixup_value);
hi_func = riscv_force_binary (SImode, AND, hi_func,
@@ -4956,7 +4957,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode));
riscv_emit_move (mem, addi_lo_chain);
- /* Gen jr r1, lo(func). */
+ /* Gen jr t0, lo(func). */
rtx lo_func = riscv_force_binary (SImode, AND, target_function,
[PATCH] PR target/97682 - Fix to reuse t1 register between call address and epilogue.
- When expanding the call pattern, choose t1 register be a jump register.
Epilogue also uses a t1 register to adjust Stack point. The call pattern
and epilogue will initial t1 twice, if both are generated in the same
function. The call pattern will emit 'la t1,symbol' and 'jalr
t1'instructions.
Epilogue also emits 'li t1,4096' and 'addi sp,sp,t1' instructions.
But li and addi instructions will be placed between la and jalr
instructions.
The la instruction will be removed by some optimizations,
because t1 register define twice, the first define instruction look
likes duplicate.
- To resolve this issue, Prologue and Epilogue use the t0 register
be temp register, the call pattern use the t1 register be tmp register.
gcc/ChangeLog:
PR target/97682
* config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Change register to
t0.
(RISCV_CALL_ADDRESS_TEMP_REGNUM): New Marco, define t1 register.
(RISCV_CALL_ADDRESS_TEMP): Use it for call instructions.
* config/riscv/riscv.c (riscv_legitimize_call_address): Use
RISCV_CALL_ADDRESS_TEMP.
(riscv_trampoline_init): Adjust comment.
gcc/testsuite/ChangeLog
PR target/97682
* g++.target/riscv/pr97682.C: New test.
---
gcc/config/riscv/riscv.c | 14 +-
gcc/config/riscv/riscv.h | 6 +-
gcc/testsuite/g++.target/riscv/pr97682.C | 160 +++
3 files changed, 172 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/g++.target/riscv/pr97682.C
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 989a9f15250..ac4b04540e6 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3110,7 +3110,7 @@ riscv_legitimize_call_address (rtx addr)
{
if (!call_insn_operand (addr, VOIDmode))
{
- rtx reg = RISCV_PROLOGUE_TEMP (Pmode);
+ rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode);
riscv_emit_move (reg, addr);
return reg;
}
@@ -4902,9 +4902,9 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
/* lui t2, hi(chain)
-lui t1, hi(func)
+lui t0, hi(func)
addit2, t2, lo(chain)
-jr r1, lo(func)
+jr t0, lo(func)
*/
unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code;
unsigned HOST_WIDE_INT lo_chain_code, lo_func_code;
@@ -4929,7 +4929,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
mem = adjust_address (m_tramp, SImode, 0);
riscv_emit_move (mem, lui_hi_chain);
- /* Gen lui t1, hi(func). */
+ /* Gen lui t0, hi(func). */
rtx hi_func = riscv_force_binary (SImode, PLUS, target_function,
fixup_value);
hi_func = riscv_force_binary (SImode, AND, hi_func,
@@ -4956,7 +4956,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode));
riscv_emit_move (mem, addi_lo_chain);
- /* Gen jr r1, lo(func). */
+ /* Gen jr t0, lo(func). */
rtx lo_func = riscv_force_binary (SImode, AND, target_function,
imm12_mask);
lo_func = riscv_force_binary (SImode, ASHIFT, lo_func, GEN_INT (20));
@@ -4975,9 +4975,9 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
/* auipc t2, 0
-l[wd] t1, target_function_offset(t2)
+l[wd] t0, target_function_offset(t2)
l[wd] t2, static_chain_offset(t2)
-jr t1
+jr t0
*/
trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD);
trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 172c7ca7c98..3bd1993c4c9 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -342,9 +342,13 @@ extern const char *riscv_default_mtune (int argc, const
char **argv);
The epilogue temporary mustn't conflict with the return registers,
the frame pointer, the EH stack adjustment, or the EH data registers. */
-#define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
+#define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST)
#define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE,
RISCV_PROLOGUE_TEMP_REGNUM)
+#define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1)
+#define RISCV_CALL_ADDRESS_TEMP(MODE) \
+ gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM)
+
#define MCOUNT_NAME "_mcount"
#define NO_PROFILE_COUNTERS 1
diff --git a/gcc/testsuite/g++.target/riscv/pr97682.C
b/gcc/testsuite/g++.target/riscv/pr97682.C
new file mode 100644
index 000..03c7a447de5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr97682.C
@@ -0,0
Re: [PATCH, nds32] Missing target_cpu_default in TARGET_DEFAULT_TARGET_FLAGS.
2013/12/13 Chung-Ju Wu jasonw...@gmail.com: 2013/12/11 Monk Chiang sh.chian...@gmail.com: Hi, Recently I used --target=nds32be-elf to configure nds32 gcc, it seems that the big endian is not set as default. [...] The following is the patch to fix this issue. Tested on nds32be-elf. OK to apply? Index: common/config/nds32/nds32-common.c === --- common/config/nds32/nds32-common.c (revision 205880) +++ common/config/nds32/nds32-common.c (working copy) @@ -93,7 +93,8 @@ TARGET_CMOV : Generate conditional move instruction. */ Could you also extend the comment about adding TARGET_CPU_DEFAULT? That would be great to let other developers realize why we need it. :) #undef TARGET_DEFAULT_TARGET_FLAGS #define TARGET_DEFAULT_TARGET_FLAGS\ - (MASK_GP_DIRECT \ + (TARGET_CPU_DEFAULT \ + | MASK_GP_DIRECT\ | MASK_16_BIT \ | MASK_PERF_EXT \ | MASK_CMOV) Index: ChangeLog === --- ChangeLog (revision 205880) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2013-12-11 Monk Chiang sh.chian...@gmail.com In ChangeLog formatting, there should be two spaces between 'Chiang' and ''. + + * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): + Redefine. + Suggest using 'Consider TARGET_CPU_DEFAULT settings.' 2013-12-11 Bin Cheng bin.ch...@arm.com OK with those changes. Thank you for the patch fixing that issue. :) Best regards, jasonwucj I add comment to describe why I adding TARGET_CPU_DEFAULT, and fix typo in ChangeLog fle. Thank you for your suggestion. Index: ChangeLog === --- ChangeLog (revision 206039) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2013-12-17 Monk Chiang sh.chian...@gmail.com + + * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): + Consider TARGET_CPU_DEFAULT settings. + 2013-12-16 Jakub Jelinek ja...@redhat.com * predict.h (PROB_LIKELY): Fix the value. Index: common/config/nds32/nds32-common.c === --- common/config/nds32/nds32-common.c (revision 206039) +++ common/config/nds32/nds32-common.c (working copy) @@ -86,14 +86,23 @@ /* Run-time Target Specification. */ -/* Default enable +/* The default target flags consist of + TARGET_CPU_DEFAULT and other MASK_XXX flags. + + The value of TARGET_CPU_DEFAULT is set by + the process of 'configure' and 'make' stage. + Please check gcc/config.gcc for more implementation detail. + + Other MASK_XXX flags are set individually. + By default we enable TARGET_GP_DIRECT: Generate gp-imply instruction. TARGET_16_BIT : Generate 16/32 bit mixed length instruction. TARGET_PERF_EXT : Generate performance extention instrcution. TARGET_CMOV : Generate conditional move instruction. */ #undef TARGET_DEFAULT_TARGET_FLAGS #define TARGET_DEFAULT_TARGET_FLAGS\ - (MASK_GP_DIRECT \ + (TARGET_CPU_DEFAULT \ + | MASK_GP_DIRECT\ | MASK_16_BIT \ | MASK_PERF_EXT \ | MASK_CMOV) Monk
[PATCH, nds32] Missing target_cpu_default in TARGET_DEFAULT_TARGET_FLAGS.
Hi, Recently I used --target=nds32be-elf to configure nds32 gcc, it seems that the big endian is not set as default. In the config.gcc, I notice that target_cpu_default is defined as: nds32le-*-*) target_cpu_default=0 nds32be-*-*) target_cpu_default=0|MASK_BIG_ENDIAN But the TARGET_CPU_DEFAULT is not added into TARGET_DEFAULT_TARGET_FLAGS so that MASK_BIG_ENDIAN is not enabled for nds32be-elf. The following is the patch to fix this issue. Tested on nds32be-elf. OK to apply? Index: common/config/nds32/nds32-common.c === --- common/config/nds32/nds32-common.c (revision 205880) +++ common/config/nds32/nds32-common.c (working copy) @@ -93,7 +93,8 @@ TARGET_CMOV : Generate conditional move instruction. */ #undef TARGET_DEFAULT_TARGET_FLAGS #define TARGET_DEFAULT_TARGET_FLAGS\ - (MASK_GP_DIRECT \ + (TARGET_CPU_DEFAULT \ + | MASK_GP_DIRECT\ | MASK_16_BIT \ | MASK_PERF_EXT \ | MASK_CMOV) Index: ChangeLog === --- ChangeLog (revision 205880) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2013-12-11 Monk Chiang sh.chian...@gmail.com + + * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): + Redefine. + 2013-12-11 Bin Cheng bin.ch...@arm.com Reverted: Monk
