On 21 September 2015 at 15:38, James Greenhalgh
wrote:
> ---
> gcc/
>
> 2015-09-21 James Greenhalgh
>
> * config/aarch64/aarch64-simd.md
>
> (aarch64_float_truncate_hi_v4sf): Rewrite as an expand.
>
On Mon, Sep 21, 2015 at 10:44:32AM +0100, Alan Lawrence wrote:
> [Resending in plain text] This makes sense to me now, although I find
> your comment slightly confusing:
>
> [] in that
> +;; the meaning of HI and LO is always taken with a little-endian view of
> +;; the vector
>
> You mean
On 21/09/15 15:38, James Greenhalgh wrote:
On Mon, Sep 21, 2015 at 10:44:32AM +0100, Alan Lawrence wrote:
[Resending in plain text] This makes sense to me now, although I find
your comment slightly confusing:
[] in that
+;; the meaning of HI and LO is always taken with a little-endian
[Resending in plain text] This makes sense to me now, although I find
your comment slightly confusing:
[] in that
+;; the meaning of HI and LO is always taken with a little-endian view of
+;; the vector
You mean vec_unpacks_{hi,lo} (which seems to go against the
*architectural* bit after
On 10 September 2015 at 16:02, James Greenhalgh
wrote:
>
> On Wed, Sep 09, 2015 at 10:28:28AM +0100, Christophe Lyon wrote:
>> On 9 September 2015 at 10:31, James Greenhalgh
>> wrote:
>> >
>> > Hi,
>> >
>> > This patch clears up some remaining
On 09/09/15 11:31, Alan Lawrence wrote:
Hmmm, hang on. I'm not quite sure what the actual issue/bug is here, but is this
the same issue as my patch 12 "with BE RTL fix"?
(https://gcc.gnu.org/ml/gcc-patches/2015-08/msg01482.html, explanation last at
On Wed, Sep 09, 2015 at 10:28:28AM +0100, Christophe Lyon wrote:
> On 9 September 2015 at 10:31, James Greenhalgh
> wrote:
> >
> > Hi,
> >
> > This patch clears up some remaining confusion in the vector lane orderings
> > for the two intrinsics mentioned in the title.
Hi,
This patch clears up some remaining confusion in the vector lane orderings
for the two intrinsics mentioned in the title.
Bootstrapped on aarch64-none-linux-gnu and regression tested for
aarch64_be-none-elf with no issues.
OK?
Thanks,
James
---
2015-09-09 James Greenhalgh
Hmmm, hang on. I'm not quite sure what the actual issue/bug is here, but is this
the same issue as my patch 12 "with BE RTL fix"?
(https://gcc.gnu.org/ml/gcc-patches/2015-08/msg01482.html, explanation last at
https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02365.html) I pushed this as
r227551
On 9 September 2015 at 10:31, James Greenhalgh wrote:
>
> Hi,
>
> This patch clears up some remaining confusion in the vector lane orderings
> for the two intrinsics mentioned in the title.
>
> Bootstrapped on aarch64-none-linux-gnu and regression tested for
>
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