+;; Rd = (eq (reg1) (reg2/imm))// optimize for size on Thumb2
+;;subs T1, Reg1, reg2
+;;negs Rd, T1
+;;adcs Rd, Rd, T1
Only the second operation has to be flag setting. A later pass will
convert the first and third instructions to flag clobbering if
On 01/08/13 14:02, Kyrylo Tkachov wrote:
+;; Rd = (eq (reg1) (reg2/imm)) // optimize for size on Thumb2
+;; subs T1, Reg1, reg2
+;; negs Rd, T1
+;; adcs Rd, Rd, T1
Only the second operation has to be flag setting. A later pass will
convert the first and third instructions to flag
Hi all,
Resurrecting this thread...
On 01/07/13 12:05, Kyrylo Tkachov wrote:
Hi Richard,
This hurts code size.
Therefore I've disabled the new peephole2 for
optimize_insn_for_size_p
so that
the original peephole before r200197 is used when optimising for
size.
I've also added a
On 31/07/13 14:31, Kyrylo Tkachov wrote:
Hi all,
Resurrecting this thread...
On 01/07/13 12:05, Kyrylo Tkachov wrote:
Hi Richard,
This hurts code size.
Therefore I've disabled the new peephole2 for
optimize_insn_for_size_p
so that
the original peephole before r200197 is used when
On 01/07/13 12:05, Kyrylo Tkachov wrote:
Hi Richard,
This hurts code size.
Therefore I've disabled the new peephole2 for optimize_insn_for_size_p
so that
the original peephole before r200197 is used when optimising for size.
I've also added a test to confirm that the new peephole2 for the
Hi Richard,
This hurts code size.
Therefore I've disabled the new peephole2 for optimize_insn_for_size_p
so that
the original peephole before r200197 is used when optimising for size.
I've also added a test to confirm that the new peephole2 for the non-CC
setting variants is being
Hi all,
With r200197 the test pr46975.c now fails because the code:
/* { dg-options -mthumb -Os } */
int foo (int s)
{
return s == 1;
}
now generates:
0: f1a0 0001 sub.w r0, r0, #1
4: fab0 f080 clz r0, r0
8: 0940lsrsr0, r0, #5
a:
On 21/06/13 09:49, Kyrylo Tkachov wrote:
Hi all,
With r200197 the test pr46975.c now fails because the code:
/* { dg-options -mthumb -Os } */
int foo (int s)
{
return s == 1;
}
now generates:
0: f1a0 0001 sub.w r0, r0, #1
4: fab0 f080 clz r0, r0
