On 02/02/18 12:21, Eric Botcazou wrote:
>> That's always been my interpretation too. Seems like we may be changing
>> the meaning of this macro...
>
> The main (and essentially only) effect of WORD_REGISTER_OPERATIONS in the
> compiler happens during combine and is explained by this comment take
> That's always been my interpretation too. Seems like we may be changing
> the meaning of this macro...
The main (and essentially only) effect of WORD_REGISTER_OPERATIONS in the
compiler happens during combine and is explained by this comment taken from
eliminate_regs_1 and written by Jim in 1
> By QImode addition, do you mean:
>
>(set (subreg:QI (reg:SI X1) N)
> (plus:QI (subreg:QI (reg:SI X2) N)
>(subreg:QI (reg:SI X3) N)))
>
> ?
Yes.
> I thought the point was instead that the target expected such ops
> to be done on word_mode, even if the values involved
On 31/01/18 19:04, Richard Sandiford wrote:
> Eric Botcazou writes:
>>> Tested on SPARC64/Linux and ARM/EABI, applied on mainline and 7 branch.
>>
>> As discussed in the audit trail, this beefs up the internal documentation
>> about WORD_REGISTER_OPERATIONS.
>>
>> Tested with 'make doc', applied
Eric Botcazou writes:
>> Tested on SPARC64/Linux and ARM/EABI, applied on mainline and 7 branch.
>
> As discussed in the audit trail, this beefs up the internal documentation
> about WORD_REGISTER_OPERATIONS.
>
> Tested with 'make doc', applied on mainline and 7 branch.
>
>
> 2018-01-31 Eric Bot
> Tested on SPARC64/Linux and ARM/EABI, applied on mainline and 7 branch.
As discussed in the audit trail, this beefs up the internal documentation
about WORD_REGISTER_OPERATIONS.
Tested with 'make doc', applied on mainline and 7 branch.
2018-01-31 Eric Botcazou
PR rtl-optimization
This is a regression present on mainline and 7 branch for big-endian ARM in
the form of a wrong elimination of zero-extension after sign-extended load.
The problem is that reg_nonzero_bits_for_combine returns 0x for the
register (reg:HI 121) when queried for SImode after:
(insn 10 7 11 2 (s
