Re: Remove non-GAS non-ELF support in alpha backend

On Wed, Mar 14, 2012 at 07:02:33PM +0100, Rainer Orth wrote: > Richard Henderson writes: > > > On 03/14/12 09:09, Rainer Orth wrote: > > > > Nearly ok. > > > >> + targetm.asm_file_start_file_directive = 0; > > > > This is default and may be deleted. > > Or would be if alpha.c

Re: [PATCH][AArch64] Add BIC-imm and ORR-imm SIMD pattern

On Mon, Sep 25, 2017 at 11:13:57AM +0100, Sudi Das wrote: > > Hi James > > I put aarch64_output_simd_general_immediate looking at the similarities of > the immediates for mov/mvni and orr/bic. The CHECK macro in > aarch64_simd_valid_immediate both checks > and converts the immediates in a manner

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #2 of 8

On Tue, Sep 26, 2017 at 11:06:09AM -0500, Segher Boessenkool wrote: > > @@ -6850,52 +6850,41 @@ (define_insn_and_split "movsi_from_sf" > >rtx op1 = operands[1]; > >rtx op2 = operands[2]; > >rtx op0_di = gen_rtx_REG (DImode, REGNO (op0)); > > + rtx op2_si = gen_rtx_REG (SImode, REGNO

[PATCH] C++: show location of problematic extern "C" specifications

There are a few places where the C++ FE will complain when attempting to do things within an extern "C" linkage specifier. I've run into problems where it wasn't clear where the pertinent extern "C" was; for example, when failing to close an extern "C" linkage specifier in a header, leading to

Enable ifunc attribute by default for SPARC GNU/Linux

Similar to other architectures with IFUNC binutils/glibc support, this patch enables the ifunc attribute for SPARC GNU/Linux. This is needed for building glibc with the current checks on IFUNC resolver types (and use of the attribute in glibc rather than manually created IFUNCs is beneficial

[patch, fortran, committed] Fix wrong warning inside associate construct

Hello world, I have committed the attached patch as obvious after regression-testing. It removes the wrong warning from my recend DO warning patch that Jakub pointed out. The test case that is restored with this patch is enough to catch any regression. Regards Thomas 2017-09-26

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #3 of 8

On Tue, Sep 26, 2017 at 11:36:14AM -0500, Segher Boessenkool wrote: > Hi! > > On Tue, Sep 26, 2017 at 10:34:44AM -0400, Michael Meissner wrote: > > * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a > > DFmode to a SFmode, and then needing to move the SFmode to a GPR > >

Re: [PATCH] [ARC][ZOL] Account for empty body loops

* Claudiu Zissulescu [2017-09-01 14:32:10 +0200]: > From: claziss > > Hi Andrew, > > By mistake I've pushed an incoplete ZOL-rework patch, and it missing the > attached parts. Please can you check if it is ok? > > Thank you, > Claudiu

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #7 of 8

On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote: > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR): > Adjust code to eliminate needing to do the shift right 32-bits > operation after XSCVDPSPN. After staring at this way too long... Looks

[committed] Fix PR 39570 - cabs/cabsf named differently on NetBSD

I have committed the attached patch to fix PR 39570. The problem is that the NetBSD cabs/cabsf/cabsl funcions are called __c99_cabs etc. as NetBSD needed to change the ABI before it had symbol versioning. This is handled in the system header file as double cabs(double _Complex)

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #7 of 8

On Tue, Sep 26, 2017 at 04:56:54PM -0500, Segher Boessenkool wrote: > On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote: > > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR): > > Adjust code to eliminate needing to do the shift right 32-bits > > operation

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

On 25 September 2017 at 17:24, Jan Hubicka wrote: >> Hi Honza, >> Could you please have a look at this patch ? >> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg02063.html > > I can and I should have done long time ago. I really apologize for slow > response > and I will try to be

Re: 0002-Part-2.-Document-finstrument-control-flow-and-notrack attribute

On 09/26/2017 07:45 AM, Tsimbalist, Igor V wrote: Here is the updated version (version#3). All comments below are fixed. This still needs more work. Specific comments below: +The @code{nocf_check} attribute is applied to an object's type. +In case of assignment of a function address or a

Re: [PATCH] Make SRA qsort comparator transitive

On September 26, 2017 5:20:25 PM GMT+02:00, Martin Jambor wrote: >Hi, > >On Mon, Sep 25, 2017 at 04:22:06PM +0300, Alexander Monakov wrote: >> >> Thanks! If this is resolved, haifa-sched autoprefetch ranking will >become the >> last remaining (among discovered so far)

Re: [PATCH v2,rs6000] Replace swap of a loaded vector constant with load of a swapped vector constant

On Sep 26, 2017, at 5:57 AM, Segher Boessenkool wrote: > >> +/* { dg-final { scan-assembler-not "swap" } } */ > > So what is this really testing for? xxswapd? But a) we never generate > that, and b) you could use a better regex? Agreed, this looks like an

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #2 of 8

Hi, On Tue, Sep 26, 2017 at 10:32:03AM -0400, Michael Meissner wrote: > * config/rs6000/rs6000.md (movsi_from_sf): Adjust code to > eliminate doing a 32-bit shift right or vector extract after doing > XSCVDPSPN. Use zero_extendsidi2 instead of p8_mfvsrd_4_disf to > move

Re: [GCC][PATCH][TESTSUITE][ARM][COMMITTED] Invert check to misalign in vect_hw_misalign (PR 78421)

On Sep 25, 2017, at 9:58 PM, Christophe Lyon wrote: > > Yes, thanks! I was missing the 'expr' part. > > Here is what I have committed (r253187), to avoid further noise in the > results. Yup, looks good. Thanks.

Re: [PATCH][GRAPHITE] More TLC

On Tue, Sep 26, 2017 at 09:19:50AM -0500, Sebastian Pop wrote: > Sven, is there already a function that computes the sum of all > strides in a proximity map? Maybe you have code that does > something similar in pet or ppcg? What exactly do you want to sum? If this involves any counting, then it

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #6 of 8

On Tue, Sep 26, 2017 at 10:44:24AM -0400, Michael Meissner wrote: > * config/rs6000/vsx.md (vsx_xscvdpspn): Eliminate useless > alternative constraint. > (vsx_xscvspdpn): Likewise. > (vsx_xscvspdpn_scalar): Likewise. Okay, nice cleanup! Thanks, Segher

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #8 of 8

On Tue, Sep 26, 2017 at 10:50:14AM -0400, Michael Meissner wrote: > * gcc.target/powerpc/pr71977-1.c: Update test to know that we > don't generate a 32-bit shift after doing XSCVDPSPN. > * gcc.target/powerpc/direct-move-float1.c: Likewise. > *

Re: [PATCH] Make SRA qsort comparator transitive

Hi, On Mon, Sep 25, 2017 at 04:22:06PM +0300, Alexander Monakov wrote: > > Thanks! If this is resolved, haifa-sched autoprefetch ranking will become the > last remaining (among discovered so far) inconsistent qsort comparator in GCC. > So the following has passed bootstrap and testing on

[PING] [PATCH] rl78 adddi3 improvement

Hi, I would like to ping the below patch posted on 14th of august. Thank you! Sebastian -Original Message- From: Sebastian Perta Sent: 14 August 2017 15:26 To: 'gcc-patches@gcc.gnu.org' Subject: [PATCH] rl78 adddi3 improvement The following patch improves

Re: [PATCH 4/5] New target check: vect_nopeel - v2

Andreas Krebbel writes: > - vect_nopeel renamed to vect_no_peel > - documentation added. > > gcc/testsuite/ChangeLog: > > 2017-09-26 Andreas Krebbel > > * doc/sourcebuild.texi: Document vect_no_peel. > > gcc/testsuite/ChangeLog: > >

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #4 of 8

On Tue, Sep 26, 2017 at 10:36:34AM -0400, Michael Meissner wrote: > * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Move insn so that > it is adjacent to the other XSCVSPDP insns. Okay for trunk. Thanks, Segher

Re: [patch, fortran] Warn about out-of-bounds access with DO subscripts

Hi! On Mon, 25 Sep 2017 18:50:49 +0200, Thomas Koenig wrote: Thanks for the review, committed as r253156. Now, on to some other bugs... No, back to this one please. ;-) OK, if you insist :-) Apparently, the changes you prepared for existing testcases did not get

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #3 of 8

Hi! On Tue, Sep 26, 2017 at 10:34:44AM -0400, Michael Meissner wrote: > * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a > DFmode to a SFmode, and then needing to move the SFmode to a GPR > to use the XSCVDPSP instruction instead of FRSP and XSCVDPSPN. > ---

Re: [PATCH v2] [libcc1] Rename C{,P}_COMPILER_NAME and remove triplet from them

Ping^2. On Friday, September 15 2017, I wrote: > Ping. > > On Friday, September 01 2017, I wrote: > >> On Wednesday, August 23 2017, Pedro Alves wrote: >> >>> On 08/23/2017 05:17 AM, Sergio Durigan Junior wrote: Hi there, This is a series of two patches, one for GDB and one for

Re: [patch, fortran] Warn about out-of-bounds access with DO subscripts

Hi Jakub, associate(k => v, l => a(i, j), m => a(i, :)) And I don't really see a bug in the testcase... Hm, I will look at this. Maybe some strange interaction with associate here... Regards Thomas

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #5 of 8

Hi! On Tue, Sep 26, 2017 at 10:39:06AM -0400, Michael Meissner wrote: > * config/rs6000/vsx.md (vsx_xscvdpsp_scalar): Use "ww" constraint > instead of "f" to allow SFmode to be in traditional Altivec > registers. Okay. Thanks, Segher

[GCC][PATCH][testsuite][mid-end] Fix failing slp test on aarch64 and arm.

Hi All, The slp vectorization test currently fails on AArch32 and AArch64 due to it not taking into account that we do have 128 bit vectors in NEON. This means that two of the loops get vectorized instead of just 1. So update the conditions to include a check for neon. Regtested on

Re: [PATCH] BRIG frontend: request for a global review

Hi, On Sun, Sep 17, 2017 at 02:13:34PM +0200, Thomas Schwinge wrote: > Hi! > > On Tue, 24 Jan 2017 15:30:34 -0500, David Malcolm wrote: > > On Tue, 2017-01-24 at 13:52 +0100, Martin Jambor wrote: > > > [...] I have just > > > committed the BRIG FE as revision 244867. > >

Re: [PATCH][GRAPHITE] More -fopt-info, do not abort from ISL

On Mon, Sep 25, 2017 at 4:47 AM, Richard Biener wrote: > > The following also dumps if the optimized schedule is equal to the > original one. It also makes all ISL operations (well, nearly) not > abort on errors but instead propagate errors upward. > > Bootstrapped and tested

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #1 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #3 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [PATCH] x32: Encode %esp as %rsp to avoid 0x67 prefix

On Sun, Sep 24, 2017 at 11:25:34AM +0200, Uros Bizjak wrote: > We can use 'q' modifier just before register output part (plus a small > simplification). > > Can you try the attached (untested) patch? > > Uros. > Index: i386.c > ===

Re: [PATCH][GCC] Simplification of 1U << (31 - x)

Still waiting on Jakub's comment on whether there are more things needed at the backend. But I have updated the patch according to Richard's comments. Thanks Sudi From: Richard Biener Sent: Friday, August 4, 2017 11:16 AM To: Sudi Das Cc: Wilco Dijkstra; Jakub

Re: [PATCH][GRAPHITE] Simplify SCOP detection

On Tue, Sep 26, 2017 at 7:03 AM, Richard Biener wrote: > > The following is the result of me trying to understand SCOP detection > and the validity checks spread around the machinery. It removes several > quadraticnesses by folding validity checks into >

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #7 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [PATCH][GCC] Simplification of 1U << (31 - x)

On Tue, Sep 26, 2017 at 12:44:10PM +, Sudi Das wrote: > > Still waiting on Jakub's comment on whether there are more things needed > at the backend. But I have updated the patch according to Richard's > comments. Well, we don't want to regress performance wise on one of the most important

Re: [PATCH] Add helper to sort sibling loops, do so in GRAPHITE

On Mon, Sep 25, 2017 at 8:18 AM, Richard Biener wrote: > > The following adds a helper to sort the sibling loop list in RPO order > as it can get messed up (we only ever add loops at the start of the list). > GRAPHITE SCOP detection assumes this list is sorted naturally in RPO

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #2 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [PATCH][GRAPHITE] More TLC

On Mon, Sep 25, 2017 at 8:12 AM, Richard Biener wrote: > On Fri, 22 Sep 2017, Sebastian Pop wrote: > > > On Fri, Sep 22, 2017 at 8:03 AM, Richard Biener > wrote: > > > > > > > > This simplifies canonicalize_loop_closed_ssa and does other minimal > > > TLC.

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #5 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [Patch, Fortran] PR 82143: add a -fdefault-real-16 flag

On Tue, Sep 26, 2017 at 4:44 AM, Janus Weil wrote: > 2017-09-25 23:23 GMT+02:00 Steve Kargl : >> On Mon, Sep 25, 2017 at 11:14:42PM +0200, Janus Weil wrote: >>> 2017-09-25 17:07 GMT+02:00 David Edelsohn : >>> >

Re: [PATCH 3/5] pr65947-9.c: Requires char to be signed by default.

On Tue, Sep 26, 2017 at 1:39 PM, Andreas Krebbel wrote: > Fails on S/390 with char defaulting to unsigned char. Ok. > gcc/testsuite/ChangeLog: > > 2017-09-26 Andreas Krebbel > > * gcc.dg/vect/pr65947-9.c: Use signed char

Re: [PATCH 4/5] New target check: vect_nopeel - v2

Hi Andreas, > diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi > index 307c726..3acfd85 100644 > --- a/gcc/doc/sourcebuild.texi > +++ b/gcc/doc/sourcebuild.texi > @@ -1398,6 +1398,9 @@ Target supports a vector misalign access. > @item vect_no_align > Target does not support a

RE: 0002-Part-2.-Document-finstrument-control-flow-and-notrack attribute

Here is the updated version (version#3). All comments below are fixed. Igor > -Original Message- > From: Tsimbalist, Igor V > Sent: Monday, September 25, 2017 11:57 PM > To: Sandra Loosemore ; 'gcc- > patc...@gcc.gnu.org' > Cc: Jeff Law

RE: 0005-Part-5.-Add-x86-CET-documentation

Here is a new version of the patch. Igor > -Original Message- > From: Sandra Loosemore [mailto:san...@codesourcery.com] > Sent: Monday, September 25, 2017 5:43 AM > To: Uros Bizjak ; Tsimbalist, Igor V > > Cc: gcc-patches@gcc.gnu.org >

Re: [PATCH] Fix PR82321

On Tue, Sep 26, 2017 at 6:02 AM, Richard Biener wrote: > > Latent, exposed by me removing the "redundant" > rewrite-into-loop-closed-ssa. > > Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. > > Richard. > > 2017-09-26 Richard Biener > >

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #1 of 8

Hi! On Tue, Sep 26, 2017 at 10:30:03AM -0400, Michael Meissner wrote: > I have broken the patches down to 8 chunks. Thanks for doing this. > +(define_split > + [(set (match_operand:DI 0 "int_reg_operand") > + (sign_extend:DI (match_operand:SI 1 "vsx_register_operand")))] Should be EXTSI

Re: [PATCH 4/5] New target check: vect_nopeel - v2

- vect_nopeel renamed to vect_no_peel - documentation added. gcc/testsuite/ChangeLog: 2017-09-26 Andreas Krebbel * doc/sourcebuild.texi: Document vect_no_peel. gcc/testsuite/ChangeLog: 2017-09-26 Andreas Krebbel *

Re: [PATCH 2/5] pr60656.c: New target check: vect_mult_long

On 09/26/2017 01:57 PM, Rainer Orth wrote: > Hi Andreas, > >> We don't have a 64 bit vector integer multiply on z. Add a specific >> check for that. >> >> 2017-09-26 Andreas Krebbel >> >> * gcc.dg/vect/pr60656.c: Check vect_mult_long. >> *

Re: [PATCH][GCC] Simplification of 1U << (31 - x)

Jakub Jelinek wrote: > Well, we don't want to regress performance wise on one of the most important > primary targets.  I don't care that much if the RTL/backend work is done > together with the patch, or as a follow-up during stage1/3, but it should be > done, the testcases I've posted can be

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #4 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #8 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [PATCH] x32: Encode %esp as %rsp to avoid 0x67 prefix

On Tue, Sep 26, 2017 at 2:19 PM, Jakub Jelinek wrote: > On Sun, Sep 24, 2017 at 11:25:34AM +0200, Uros Bizjak wrote: >> We can use 'q' modifier just before register output part (plus a small >> simplification). >> >> Can you try the attached (untested) patch? >> >> Uros. > >>

[PATCH 1/2] C++: avoid partial duplicate implementation of cp_parser_error

In r251026 (aka 3fe34694f0990d1d649711ede0326497f8a849dc, "C/C++: show pertinent open token when missing a close token") I copied part of cp_parser_error into cp_parser_required_error, leading to duplication of code. This patch eliminates this duplication by merging the two copies of the code

[PATCH 2/2] C/C++: add fix-it hints for various missing symbols (v2)

The patch improves our C/C++ frontends' handling of missing symbols, by making c_parser_require and cp_parser_require use "better" locations for the diagnostic, and insert fix-it hints, under certain circumstances (see the comments in the patch for full details). For example, for this code with a

[PATCH 0/2] Re: [PATCH] C/C++: add fix-it hints for various missing symbols

On Mon, 2017-08-28 at 09:22 -0600, Jeff Law wrote: > On 07/03/2017 12:37 PM, David Malcolm wrote: > > This patch improves our C/C++ frontends' handling of missing > > symbols, by making c_parser_require and cp_parser_require use > > "better" locations for the diagnostic, and insert fix-it hints, >

Re: [PATCH], Improve moving SFmode to GPR on PowerPC, #6 of 8

Off list, Segher asked that I break the patch eliminating a shift right when transfering SFmode from a vector register to a GPR register down into smaller chunks. The power7 and power8 instructions that convert values in the double precision format to single precision actually duplicate the

Re: [Patch, Fortran] PR 82143: add a -fdefault-real-16 flag

2017-09-25 23:23 GMT+02:00 Steve Kargl : > On Mon, Sep 25, 2017 at 11:14:42PM +0200, Janus Weil wrote: >> 2017-09-25 17:07 GMT+02:00 David Edelsohn : >> > promotion_3.f90 and promotion_4.f90 are failing on at least PowerPC >> > and AArch64.

Re: [Patch, Fortran] PR 82143: add a -fdefault-real-16 flag

2017-09-26 10:44 GMT+02:00 Janus Weil : > 2017-09-25 23:23 GMT+02:00 Steve Kargl : >> On Mon, Sep 25, 2017 at 11:14:42PM +0200, Janus Weil wrote: >>> 2017-09-25 17:07 GMT+02:00 David Edelsohn : >>> > promotion_3.f90 and

Re: [Patch, Fortran] PR 82143: add a -fdefault-real-16 flag

Hi Janus, > Attached is a more complete patch, which should fix all problems that > were reported concerning these two test cases. Would be great if > someone could confirm that it works on a failing target (I currently > only have access to x86_64-linux-gnu machines). I've just checked

Re: [libgfortran] Replace implicit conversions between enums in io/transfer.c by explicit casts.

On Mon, Sep 25, 2017 at 8:12 PM, Prathamesh Kulkarni wrote: > On 12 September 2017 at 17:08, Prathamesh Kulkarni > wrote: >> Hi, >> I am working on patch for PR78736 >> (https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00011.html), >>

Re: [patch, fortran] Warn about out-of-bounds access with DO subscripts

Hi! On Mon, 25 Sep 2017 18:50:49 +0200, Thomas Koenig wrote: > Thanks for the review, committed as r253156. > > Now, on to some other bugs... No, back to this one please. ;-) Apparently, the changes you prepared for existing testcases did not get committed, so I'm now

Re: [Ada] Use the Monotonic Clock on Linux

On 09/25/2017 02:36 PM, Duncan Sands wrote: +    --  The most recent calls to clock_gettime were more better. were more better -> were better Yes, we fixed that in a latter commit. :-) https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=2a6c14a68616dfb8d8578bb8692c5e05de4aade3#patch3

Re: [Ada] Improve performance of 'Image with enumeration types.

On 09/25/2017 02:47 PM, Duncan Sands wrote: it looks like this is in essence inlining the run-time library routine. In which case, shouldn't you only do it if inlining is enabled?  For example, it seems rather odd to do this if compiling with -Os. Actually, measurements showed that this

[patch] [arm] Fix pr82175 - fix -mcpu=native not working correctly

The new option processing machinery relies on %< rules in the specs to suppress options that are rewritten. Suppression appears to be a two phase process where the option is partially suppressed when %< is processed and then fully suppressed at the end of the string. Strings are separated by

Re: Transform (x / y) != 0 to x >=y and (x / y) == 0 to x < y if x, y are unsigned

On Mon, Sep 25, 2017 at 7:14 PM, Prathamesh Kulkarni wrote: > On 18 September 2017 at 15:40, Prathamesh Kulkarni > wrote: >> On 15 September 2017 at 22:09, Marc Glisse wrote: >>> On Fri, 15 Sep 2017, Wilco

[PATCH] Fix PR82320

Bootstrapped and tested on x86_64-unkown-linux-gnu, applied. Richard. 2017-09-26 Richard Biener PR tree-optimization/82320 * tree-ssa-sccvn.c (set_ssa_val_to): Changing undef to undef isn't a change. * gcc.dg/torture/pr82320.c: New

[C++ Patch] PR 65579 ("gcc requires definition of a static constexpr member...")

Hi, this is a relatively old bug already analyzed by Martin last year. He also proposed a patch: https://gcc.gnu.org/ml/gcc-patches/2016-03/msg00593.html After a short exchange Jason proposed a different approach based on simply completing the involved vars:

Re: [PATCH v2,rs6000] Replace swap of a loaded vector constant with load of a swapped vector constant

Hi Kelvin, On Mon, Sep 25, 2017 at 04:11:32PM -0600, Kelvin Nilsen wrote: > On Power8 little endian, two instructions are needed to load from the > natural in-memory representation of a vector into a vector register: a > load followed by a swap. When the vector value to be loaded is a >

[PATCH] Fix PR82321

Latent, exposed by me removing the "redundant" rewrite-into-loop-closed-ssa. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2017-09-26 Richard Biener PR tree-optimization/82321 * graphite.c (canonicalize_loop_closed_ssa): Properly

Re: [PATCH 1/8] Enable vect testcases on S/390.

Hi Andreas, > Add s390 platform checks where appropriate. > > gcc/testsuite/ChangeLog: > > 2017-09-26 Andreas Krebbel > > * lib/target-supports.exp: Enable tests for S/390. this needs to be more specific: which procs were modified? Besides, the changes to

Re: [Patch, Fortran] PR 82143: add a -fdefault-real-16 flag

Hi Rainer, >> Attached is a more complete patch, which should fix all problems that >> were reported concerning these two test cases. Would be great if >> someone could confirm that it works on a failing target (I currently >> only have access to x86_64-linux-gnu machines). > > I've just checked

Re: [Ada] Improve performance of 'Image with enumeration types.

Hi Pierre-Marie, On 09/26/2017 11:30 AM, Pierre-Marie de Rodat wrote: On 09/25/2017 02:47 PM, Duncan Sands wrote: it looks like this is in essence inlining the run-time library routine. In which case, shouldn't you only do it if inlining is enabled?  For example, it seems rather odd to do

Re: [Ada] Improve performance of 'Image with enumeration types.

Duncan, > >>it looks like this is in essence inlining the run-time library > >>routine. In which case, shouldn't you only do it if inlining is > >>enabled?  For example, it seems rather odd to do this if > >>compiling with -Os. > > > >Actually, measurements showed that this instance of inlining

Re: [Ada] Improve performance of 'Image with enumeration types.

> By the way, why not always do this "inlining", even when not optimizing? Because this generates more bloated code and inferior debugging experience. > This is a trick question, because when you answer "because XYZ" I will then > reply "but XYZ is a common reason that people disable inlining

Re: [Ada] Improve performance of 'Image with enumeration types.

On 09/26/2017 12:17 PM, Eric Botcazou wrote: By the way, why not always do this "inlining", even when not optimizing? Because this generates more bloated code and inferior debugging experience. This is a trick question, because when you answer "because XYZ" I will then reply "but XYZ is a

[PATCH 4/8] S/390: Add FP vec_pack/unpack

gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vector.md ("vec_unpacks_lo_v4sf") ("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df") ("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders. --- gcc/ChangeLog | 6 +++

[PATCH 1/8] Enable vect testcases on S/390.

Add s390 platform checks where appropriate. gcc/testsuite/ChangeLog: 2017-09-26 Andreas Krebbel * lib/target-supports.exp: Enable tests for S/390. --- gcc/testsuite/ChangeLog | 4 ++ gcc/testsuite/lib/target-supports.exp | 131

[PATCH 3/8] S/390: Add support for vec_shr

gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/predicates.md ("const_shift_by_byte_operand"): New predicate. * config/s390/vector.md ("*vec_srb"): Change modes to V_128 and V16QI. ("*vec_slb"): New insn pattern.

[PATCH 2/8] S/390: Add widening vector mult lo/hi patterns

Add support for widening vector multiply lo/hi patterns. These do not directly match on IBM Z instructions but can be emulated with even/odd + vector merge. gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vector.md ("vec_widen_umult_lo_")

[PATCH 5/8] S/390: Fix rtl standard names for vector unpack low->lo

gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vector.md ("vec_unpacks_low_v16qi"): Rename to vec_unpacks_lo_v16qi. ("vec_unpacku_low_v16qi"): Rename to vec_unpacku_lo_v16qi. --- gcc/ChangeLog | 6 ++

[PATCH 0/8] S/390: Enable vect tests on S/390 + fixes and improvements

Committed to mainline Andreas Krebbel (8): Enable vect testcases on S/390. S/390: Add widening vector mult lo/hi patterns S/390: Add support for vec_shr S/390: Add FP vec_pack/unpack S/390: Fix rtl standard names for vector unpack low->lo S/390: Set the preferred mode for float

Re: [Ada] Improve performance of 'Image with enumeration types.

Hi Arno, it looks like this is in essence inlining the run-time library routine. In which case, shouldn't you only do it if inlining is enabled?  For example, it seems rather odd to do this if compiling with -Os. Actually, measurements showed that this instance of inlining is a win for both

[PATCH 7/8] S/390: Fix vector fp unordered compares

V2DF mode was still hard-coded here. gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/s390.c (s390_expand_vec_compare): Use the new mode independent expanders. * config/s390/vector.md ("vec_cmpuneq", "vec_cmpltgt")

[PATCH 8/8] S/390: Fix vmslg instruction and builtin.

gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vx-builtins.md ("vmslg"): Add missing operand in assembler output. * config/s390/s390-builtins.def: Fix constraint on op4. --- gcc/ChangeLog | 6 ++

[PATCH 6/8] S/390: Set the preferred mode for float vectors

gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/s390.c (s390_preferred_simd_mode): Return V4SFmode for SFmode. --- gcc/ChangeLog | 5 + gcc/config/s390/s390.c | 8 2 files changed, 13 insertions(+) diff --git

[PATCH 0/5] vect testsuite adjustments for S/390

These patches adjust the vect testcases and target support checks in order to make the right set of testcases to be run on S/390 (z13 and z14). Ok for mainline? Andreas Krebbel (5): Enable vect_float with S/390 VXE and adjust testcases pr60656.c: New target check: vect_mult_long

[PATCH 1/5] Enable vect_float with S/390 VXE and adjust testcases

The target supports routines provide vect_double and vect_float but these do not appear to be used consequently in the vect testcases. With z13 we only have support for vector double but with z14 also for vector float. This patch adds vect_float to the testcases using the float data type and make

[PATCH 4/5] New target check: vect_nopeel

Without peeling loops for vector alignment the vectorization costs are lower and in some cases make the loop vectorizer cover optimizations which otherwise would be handelt in slp instead. This adds a new target check for that purpose. gcc/testsuite/ChangeLog: 2017-09-26 Andreas Krebbel

[PATCH 2/5] pr60656.c: New target check: vect_mult_long

We don't have a 64 bit vector integer multiply on z. Add a specific check for that. 2017-09-26 Andreas Krebbel * gcc.dg/vect/pr60656.c: Check vect_mult_long. * lib/target-supports.exp (check_effective_target_vect_mult_long): New proc. ---

[PATCH 3/5] pr65947-9.c: Requires char to be signed by default.

Fails on S/390 with char defaulting to unsigned char. gcc/testsuite/ChangeLog: 2017-09-26 Andreas Krebbel * gcc.dg/vect/pr65947-9.c: Use signed char explicitly. --- gcc/testsuite/gcc.dg/vect/pr65947-9.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 5/5] Testcases using dg-options require at least -mzarch.

Testcases which override the vect default options using dg-options need at least -mzarch on S/390 32 bit. gcc/testsuite/ChangeLog: 2017-09-26 Andreas Krebbel * gfortran.dg/vect/fast-math-mgrid-resid.f: Use -mzarch on S/390. *

Re: [patch, fortran] Warn about out-of-bounds access with DO subscripts

On Tue, Sep 26, 2017 at 09:17:40AM +0200, Thomas Schwinge wrote: > Hi! > > On Mon, 25 Sep 2017 18:50:49 +0200, Thomas Koenig > wrote: > > Thanks for the review, committed as r253156. > > > > Now, on to some other bugs... > > No, back to this one please. ;-) > >

Re: [PATCH 1/8] Enable vect testcases on S/390.

On 09/26/2017 01:06 PM, Rainer Orth wrote: > Hi Andreas, > >> Add s390 platform checks where appropriate. >> >> gcc/testsuite/ChangeLog: >> >> 2017-09-26 Andreas Krebbel >> >> * lib/target-supports.exp: Enable tests for S/390. > > this needs to be more

Re: [PATCH 2/5] pr60656.c: New target check: vect_mult_long

Hi Andreas, > We don't have a 64 bit vector integer multiply on z. Add a specific > check for that. > > 2017-09-26 Andreas Krebbel > > * gcc.dg/vect/pr60656.c: Check vect_mult_long. > * lib/target-supports.exp (check_effective_target_vect_mult_long): >

[PATCH] Optimize x == 0 && y == 0 into (x | y) == 0 in reassoc range opt (PR middle-end/35691)

Hi! Right now we handle x == 0 && y == 0 into (x | y) == 0 and x == -1 && y == -1 into (x & y) == -1 optimizations just in match.pd, where it will handle the case where the && (or || if using !=) is actually & (or |) and they are next to each other. It doesn't handle the case when we have such

[PATCH][GRAPHITE] Simplify SCOP detection

The following is the result of me trying to understand SCOP detection and the validity checks spread around the machinery. It removes several quadraticnesses by folding validity checks into scop_detection::harmful_loop_in_region where we already walk over all BBs in the region and process

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