Hi Luis,
On 14/05/18 21:41, Luis Machado wrote:
On 05/11/2018 06:46 AM, Kyrill Tkachov wrote:
Hi Luis,
On 10/05/18 11:31, Luis Machado wrote:
On 05/09/2018 10:44 AM, Kyrill Tkachov wrote:
On 09/05/18 13:30, Luis Machado wrote:
Hi Kyrill,
On 05/08/2018 11:09 AM, Kyrill Tkachov wrote:
Hi
On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
> Hi,
>
> Attached patch handles PR63185 when we reach PHI with temp != NULLL.
> We could see the PHI and if there isn't any uses for PHI that is
> interesting, we could ignore that ?
>
> Bootstrapped and regression tested on x86_64-linux-gnu.
>
I realised I had forgotten to copy the maintainers...
https://gcc.gnu.org/ml/gcc-patches/2018-05/msg00613.html
Thanks,
Kyrill
On 14/05/18 14:38, Kyrill Tkachov wrote:
Hi all,
This patch implements the usadv16qi and ssadv16qi standard names.
See the thread at on g...@gcc.gnu.org [1] for backgr
Hi all,
This is a respin of James's patch from:
https://gcc.gnu.org/ml/gcc-patches/2017-12/msg00614.html
The original patch was approved and committed but was later reverted because of
failures on big-endian.
This tweaked version fixes the big-endian failures in
aarch64_expand_vector_init by p
Hi all,
We've a deficiency in our vec_set family of patterns.
We don't support directly loading a vector lane using LD1 for V2DImode and all
the vector floating-point modes.
We do do it correctly for the other integer vector modes (V4SI, V8HI etc)
though.
The alternatives on the relative float
On Tue, 15 May 2018, Richard Biener wrote:
> On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
>
> > Hi,
> >
> > Attached patch handles PR63185 when we reach PHI with temp != NULLL.
> > We could see the PHI and if there isn't any uses for PHI that is
> > interesting, we could ignore that ?
> >
Hi Luis,
On 14/05/18 22:18, Luis Machado wrote:
Hi,
Here's an updated version of the patch (now reverted) that addresses the
previous bootstrap problem (signedness and long long/int conversion).
I've checked that it bootstraps properly on both aarch64-linux and x86_64-linux
and that tests lo
On Tue, May 15, 2018 at 10:20 AM Kyrill Tkachov
wrote:
> Hi all,
> This is a respin of James's patch from:
https://gcc.gnu.org/ml/gcc-patches/2017-12/msg00614.html
> The original patch was approved and committed but was later reverted
because of failures on big-endian.
> This tweaked version fix
On Thu, May 10, 2018 at 8:31 AM Richard Sandiford <
richard.sandif...@linaro.org> wrote:
> Richard Biener writes:
> > On Wed, May 9, 2018 at 1:29 PM, Richard Sandiford
> > wrote:
> >> Richard Biener writes:
> >>> On Wed, May 9, 2018 at 12:34 PM, Richard Sandiford
> >>> wrote:
> The SLP un
On Fri, May 11, 2018 at 7:15 PM Richard Sandiford <
richard.sandif...@linaro.org> wrote:
> There are four optabs for various forms of fused multiply-add:
> fma, fms, fnma and fnms. Of these, only fma had a direct gimple
> representation. For the other three we relied on special pattern-
> matchi
Hello gcc-patch list,
While trying to build a x86_64-linux hosted cross arm bare metal compiler with
both --with-multilib-list=rmprofile and --without-headers, the libgcc build
fails while trying to build the armv8-m variant with the following message:
In file included from .../build/gcc/include/
Hi Jérôme,
On 15/05/18 11:53, Jérôme Lambourg wrote:
Hello gcc-patch list,
While trying to build a x86_64-linux hosted cross arm bare metal compiler with
both --with-multilib-list=rmprofile and --without-headers, the libgcc build
fails while trying to build the armv8-m variant with the followin
Hi,
On 05/15/2018 06:37 AM, Kyrill Tkachov wrote:
Hi Luis,
On 14/05/18 22:18, Luis Machado wrote:
Hi,
Here's an updated version of the patch (now reverted) that addresses
the previous bootstrap problem (signedness and long long/int conversion).
I've checked that it bootstraps properly on b
Hi,
On Fri, May 11 2018, Richard Sandiford wrote:
> There are four optabs for various forms of fused multiply-add:
> fma, fms, fnma and fnms. Of these, only fma had a direct gimple
> representation. For the other three we relied on special pattern-
> matching during expand, although tree-ssa-mat
Calling unqualified __invoke can't find the wrong function, because
users can't use that name in their own namespaces, but qualifying it
should make name lookup slightly faster.
* include/std/variant (__gen_vtable_impl::__visit_invoke): Qualify
__invoke to prevent ADL.
Tested pow
The path::operator/=(const Source&) and path::append overloads were
still following the semantics of the Filesystem TS not C++17. Only
the path::operator/=(const path&) overload was correct.
This change adds more tests for path::operator/=(const path&) and adds
new tests to verify that the other
Hi,
noticed a few times while working on various issues, maybe we want to
add the macro now? Tested x86_64-linux.
Thanks, Paolo.
2018-05-15 Paolo Carlini
* cp-tree.h (DECL_MAYBE_IN_CHARGE_CDTOR_P): New.
(FOR_EACH_CLONE): Update.
* decl.c (grok
On Tue, 15 May 2018, Richard Biener wrote:
> On Tue, 15 May 2018, Richard Biener wrote:
>
> > On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
> >
> > > Hi,
> > >
> > > Attached patch handles PR63185 when we reach PHI with temp != NULLL.
> > > We could see the PHI and if there isn't any uses
I think these tests #include because I just copied an
existing test to a new file, and didn't remove the header.
* testsuite/27_io/filesystem/path/decompose/extension.cc: Remove
unused header.
* testsuite/27_io/filesystem/path/query/empty.cc: Likewise.
* testsuit
ping
From: Wilco Dijkstra
Sent: 04 January 2018 17:46
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Improve register allocation of fma
This patch improves register allocation of fma by preferring to update the
accumulator register. This is done by adding fma insns with operand 1 as the
a
On Tue, 15 May 2018, Richard Biener wrote:
> On Tue, 15 May 2018, Richard Biener wrote:
>
> > On Tue, 15 May 2018, Richard Biener wrote:
> >
> > > On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
> > >
> > > > Hi,
> > > >
> > > > Attached patch handles PR63185 when we reach PHI with temp !=
ping
From: Wilco Dijkstra
Sent: 25 October 2017 16:29
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Simplify frame pointer logic
Simplify frame pointer logic based on review comments here
(https://gcc.gnu.org/ml/gcc-patches/2017-10/msg01727.html).
This patch incrementally adds to these f
ping
From: Wilco Dijkstra
Sent: 17 November 2017 15:21
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Set SLOW_BYTE_ACCESS
Contrary to all documentation, SLOW_BYTE_ACCESS simply means accessing
bitfields by their declared type, which results in better codegeneration on
practically
any t
The correct definition seems to be has_root_directory() for all systems
we care about.
PR libstdc++/83891
* include/bits/fs_path.h (path::is_absolute()): Use same definition
for all operating systems.
* include/experimental/bits/fs_path.h (path::is_absolute()): Lik
OK.
On Tue, May 15, 2018 at 8:07 AM, Paolo Carlini wrote:
> Hi,
>
> noticed a few times while working on various issues, maybe we want to add
> the macro now? Tested x86_64-linux.
>
> Thanks, Paolo.
>
>
>
This patch resolves the issue in PR85782, which involves a C++ ICE
caused by OpenACC loops which contain continue statements. The problem
is that genericize_continue_stmt expects a continue label for the loop,
but that wasn't getting set up acc loops. This patch fixes that by
calling genericize_omp
On Tue, 15 May 2018, Richard Biener wrote:
> On Tue, 15 May 2018, Richard Biener wrote:
>
> > On Tue, 15 May 2018, Richard Biener wrote:
> >
> > > On Tue, 15 May 2018, Richard Biener wrote:
> > >
> > > > On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
> > > >
> > > > > Hi,
> > > > >
> > >
On 05/15/2018 02:15 AM, Richard Biener wrote:
> On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
>
>> Hi,
>>
>> Attached patch handles PR63185 when we reach PHI with temp != NULLL.
>> We could see the PHI and if there isn't any uses for PHI that is
>> interesting, we could ignore that ?
>>
>> Bo
Constrain constructors and member functions of random number engines so
that functions taking seed sequences can only be called with types that
meet the seed sequence requirements.
PR libstdc++/85749
* include/bits/random.h (__detail::__is_seed_seq): New SFINAE helper.
(li
On Fri, May 11, 2018 at 1:53 PM, Richard Biener
wrote:
> On Fri, May 4, 2018 at 6:23 PM, Bin Cheng wrote:
>> Hi,
>> Following Jeff's suggestion, I am now using existing tree-ssa-live.c and
>> tree-ssa-coalesce.c to compute register pressure, rather than inventing
>> another live range solver.
>>
On 15/05/18 14:24, Wilco Dijkstra wrote:
>
> ping
>
>
I see nothing about you addressing James' comment from 17th November...
>
>
> From: Wilco Dijkstra
> Sent: 17 November 2017 15:21
> To: GCC Patches
> Cc: nd
> Subject: [PATCH][AArch64] Set SLOW_BYTE_ACCESS
>
>
> Contrary to all docum
Hi,
this patch silences sanity check that makes sure that everything is in
partition 0 and thus boundary cost is 0 when there is only one partition.
In the testcase there is external initializer which does not get partitioned
and thus we end up with cost 1. Fixed by not accounting references from
Hi,
> I see nothing about you addressing James' comment from 17th November...
I addressed that in a separate patch, see
https://patchwork.ozlabs.org/patch/839126/
Wilco
On Sun, 2018-05-13 at 22:19 -0600, Gerald Pfeifer wrote:
> This is triggered by a report from Martin who rightfully pointed
> out that it's not straightforward to validate wwwdocs changes before
> committing a change.
>
> Martin, what do you think? Would that have avoided the challenges
> your
On 15/05/18 16:36 +0100, Jonathan Wakely wrote:
Constrain constructors and member functions of random number engines so
that functions taking seed sequences can only be called with types that
meet the seed sequence requirements.
PR libstdc++/85749
* include/bits/random.h (__detai
On 15/05/18 17:01, Wilco Dijkstra wrote:
> Hi,
>
>> I see nothing about you addressing James' comment from 17th November...
>
> I addressed that in a separate patch, see
> https://patchwork.ozlabs.org/patch/839126/
>
> Wilco
>
Which doesn't appear to have been approved. Did you follow up wi
As I said in the bugzilla PR, these assertions are all to catch our
own mistakes, not user error.
If we're comfortable the code is correct then we should remove them.
Should we wait until near the end of stage 1, to get more time with
these checks in place?
diff --git a/libstdc++-v3/ChangeLog
On Mon, May 14, 2018 at 03:41:34PM -0500, Luis Machado wrote:
> On 05/11/2018 06:46 AM, Kyrill Tkachov wrote:
> > Hi Luis,
> >
> > On 10/05/18 11:31, Luis Machado wrote:
> >>
> >> On 05/09/2018 10:44 AM, Kyrill Tkachov wrote:
> >>>
> >>> On 09/05/18 13:30, Luis Machado wrote:
> Hi Kyrill,
> >
Hi,
> Which doesn't appear to have been approved. Did you follow up with Jeff?
I'll get back to that one at some point - it'll take some time to agree on a way
forward with the callback.
Wilco
On Tue, May 15, 2018 at 08:00:49AM -0500, Wilco Dijkstra wrote:
>
> ping
This seems like a fairly horrible hack around the register allocator
behaviour.
BUt, OK.
James
> This patch improves register allocation of fma by preferring to update the
> accumulator register. This is done by adding f
On May 15, 2018 5:04:53 PM GMT+02:00, Jeff Law wrote:
>On 05/15/2018 02:15 AM, Richard Biener wrote:
>> On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
>>
>>> Hi,
>>>
>>> Attached patch handles PR63185 when we reach PHI with temp != NULLL.
>>> We could see the PHI and if there isn't any uses f
Kyrill Tkachov writes:
> Hi all,
>
> We've a deficiency in our vec_set family of patterns. We don't
> support directly loading a vector lane using LD1 for V2DImode and all
> the vector floating-point modes. We do do it correctly for the other
> integer vector modes (V4SI, V8HI etc) though.
>
>
Hi,
James Greenhalgh wrote:
>
> This seems like a fairly horrible hack around the register allocator
> behaviour.
That is why I proposed to improve the register allocator so one can explicitly
specify the copy preference in the md syntax. However that wasn't accepted,
so we'll have to use a hack
On 05/15/2018 03:20 AM, Richard Biener wrote:
>
> First (baby) step is the following - it arranges to collect the
> defs we need to continue walking from and implements trivial
> reduction by stopping at (full) kills. This allows us to handle
> the new testcase (which was already handled in the v
Segher:
I removed the Power 6 test file. I also went back through the tests
and checked that each test had an instruction count check. I found a
few that were missing the instruction check. I added the instruction
checks and updated the expected instruction counts for the LE and BEcases. The
DR 1560 in C++14 fixed this rule to not do a gratuitous lvalue-rvalue
conversion in this case.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit c7b8b79f72865740ead84aa602a6bc8651a60a93
Author: Jason Merrill
Date: Tue May 15 15:46:51 2018 -0400
PR c++/64372 - CWG 1560, gratuito
Hi Richard,
On 15 May 2018 at 19:20, Richard Biener wrote:
> On Tue, 15 May 2018, Richard Biener wrote:
>
>> On Mon, 14 May 2018, Kugan Vivekanandarajah wrote:
>>
>> > Hi,
>> >
>> > Attached patch handles PR63185 when we reach PHI with temp != NULLL.
>> > We could see the PHI and if there isn't a
Hi Carl,
On Tue, May 15, 2018 at 01:43:18PM -0700, Carl Love wrote:
> * gcc.target/powerpc/vsx-vector-6-be.c: Remove file
Full stop.
> * gcc.target/powerpc/vsx-vector-6-be.p7.c (dg-final): New test file for
> Power 7.
The whole file is new, so just
* gcc.target/powerpc
While working on something else I noticed that this function was
generating warnings when it's supposed to be quiet.
Tested x86_64-pc-linux-gnu, applied to trunk.
commit ea990203b6a7562e399c22ffd70e7391106d6dc5
Author: Jason Merrill
Date: Tue May 15 15:30:43 2018 -0400
* constexpr.
In C++11 and up, the implicitly-declared copy constructor and
assignment operator are deprecated if one of them, or the destructor,
is user-provided. Implementing that in G++ turned up a few dodgy uses
in the compiler.
In general it's unsafe to copy an ipa_edge_args, because if one of the
pointer
The function "warning" returns bool to indicated whether or not any
diagnostic was actually emitted; warn_deprecated_use should as well.
It's also unnecessary to duplicate the warning code between the cases
of null or non-null "decl", since the actual warnings were the same.
The only thing that's
On 05/14/2018 03:21 PM, Jeff Law wrote:
On 05/11/2018 05:09 PM, Martin Sebor wrote:
The attached patch extends -Wrestrict to constrain valid offset
ranges into objects of struct types to the bounds of the object
type, the same way the warning already handles arrays. This
makes it possible to de
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