[PING][PATCH][Aarch64] v2: Arithmetic overflow addv patterns [Patch 2/4]

Ping. Last patch here: https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00735.html

Re: [PATCH 1/4] Clean up of new format of -falign-FOO.

ET_THUMB ? 2 : 4; return align > min_insn_size ? align - min_insn_size : 0; } Which breaks with your current change. I think this needs to be modified to: 'align = 1 << label_to_alignment (label).levels[0].log' Regards, Michael Collison

Re: [PATCH v2] RISC-V: Add autovec FP binary operations.

Robin, Why do we need '-ffast-math' with the tests? On 6/15/23 11:10, Robin Dapp via Gcc-patches wrote: Hi, changes from V1: - Add VF_AUTO iterator and use it. - Ensured we don't ICE with -march=rv64gcv_zfhmin. this implements the floating-point autovec expanders for binary operations: vf

Re: [PATCH v2] RISC-V: Add autovec FP unary operations.

Hi Robin, Looks good to me except for note that this seems to depend on a new function: emit_vlmax_fp_insn which appears to be part of your autovec FP binary operation. So that patch would need to be merged first from what I can see. On 6/15/23 11:12, Robin Dapp via Gcc-patches wrote: Hi,

[PATCH] vect: Check that vector factor is a compile-time constant

While working on autovectorizing for the RISCV port I encountered an issue where vect_do_peeling assumes that the vectorization factor is a compile-time constant. The vectorization is not a compile-time constant on RISCV. Tested on RISCV and x86_64-linux-gnu. Okay? Michael gcc/     * tree-v

Re: [PATCH] vect: Check that vector factor is a compile-time constant

Richard how would I check for a full masked main vector loop? On 2/22/23 03:20, Richard Biener wrote: On Wed, Feb 22, 2023 at 12:03 AM Michael Collison wrote: While working on autovectorizing for the RISCV port I encountered an issue where vect_do_peeling assumes that the vectorization factor

Re: [PATCH] vect: Check that vector factor is a compile-time constant

Juzhe, I disagree with this comment. There are many stakeholders for autovectorization and waiting until GCC 14 is not a viable solution for us as well as other stakeholders ready to begin work on autovectorization. As we discussed I have been moving forward with patches for autovectorizatio

Re: [PATCH] vect: Check that vector factor is a compile-time constant

ation work is no more experimental than the intrinsics work which is still being merged. On 2/22/23 23:01, Jeff Law wrote: On 2/22/23 10:54, Michael Collison wrote: Juzhe, I disagree with this comment. There are many stakeholders for autovectorization and waiting until GCC 14 is not a viab

Re: [PATCH] vect: Check that vector factor is a compile-time constant

able VF. It might be possible to trigger the problem on SVE too, with a sufficiently convoluted test case. (Haven't tried though.) Richard Biener writes: On Wed, Feb 22, 2023 at 12:03 AM Michael Collison wrote: While working on autovectorizing for the RISCV port I encountered an issue where vec

[PATCH 00/07] RISC-V: Add auto-vectorization support

This series of patches adds foundational support for RISC-V autovectorization. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization patterns th

[PATCH 01/07] RISC-V: Add auto-vectorization support

This patch adds foundational support in the form of: 1. New predicates 2. New function prototypes 3. Exporting emit_vlmax_vsetvl to global scope 4. Add a new command line option -mriscv_vector_lmul gcc/ChangeLog:     * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):     New externa

[PATCH 02/07] RISC-V: Add auto-vectorization support

This patch adds foundational support by making two functions that handle predication policies visibly globally. gcc/ChangeLog:     * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):     Remove static declaration to to make externally visible.     (get_mask_policy_for_pred): Dit

[PATCH 03/07] RISC-V: Add auto-vectorization support

From: Michael Collison Date: Thu, 2 Mar 2023 12:27:36 -0500 Subject: [PATCH] Autovectorization patch set 2 --- gcc/config.gcc| 2 +- gcc/config/riscv/riscv-vector-cost.cc | 620 ++ gcc/config/riscv/riscv-vector-cost.h | 400 + gcc

[PATCH 04/07] RISC-V: Add auto-vectorization support

This patch adds support for functions used in implementing various portions of autovectorization support. gcc/ChangeLog:     * config/riscv/riscv-v.cc (riscv_classify_vlmul_field):     New function.     (riscv_vector_preferred_simd_mode): Ditto.     (get_mask_policy_no_pred): Ditto.     (get_ta

[PATCH 05/07] RISC-V: Add auto-vectorization support

This patch adds support for registering target hooks for basic autovectorization support as well as basic tuning information for the vector extension. gcc/ChangeLog:     * config/riscv/riscv-cores.def (RISCV_TUNE):     Add VECTOR_TUNE_INFO parameter and     * common/config/riscv/riscv-common.c

[PATCH 06/07] RISC-V: Add auto-vectorization support

ription for RISC-V 'V' Extension for GNU compiler. +;; Copyright (C) 2022-2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd. +;; Contributed by Michael Collison (colli...@rivosinc.com, Rivos Inc. + +;; This file is part of GCC

[PATCH 07/07] RISC-V: Add auto-vectorization support

This patch adds tests for autovectorization of integer add and subtract. gcc/testsuite/ChangeLog:     * gcc.target/riscv/rvv/autovec: New directory     for autovectorization tests.     * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New     test to verify code generation of vector add on rv32.  

[PATCH v2 00/07] RISC-V: autovec: Add auto-vectorization support

This series of patches adds foundational support for RISC-V autovectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization pat

[PATCH v2 01/07] RISC-V: autovec: Add new predicates and function prototypes

This patch adds foundational support in the form of: 1. New predicates 2. New function prototypes 3. Exporting emit_vlmax_vsetvl to global scope 4. Add a new command line option -mriscv_vector_lmu 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv

[PATCH v2 02/07] RISC-V: autovec: Export policy functions to global scope

This patch adds foundational support by making two functions that handle predication policies visibly globally. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred

[PATCH v2 03/07] RISC-V: autovec: Add vector cost model

This patches adds two new files to support the vector cost model and modifies the Makefile fragment to build the cost model c++ file. Due to the large size this patch is provided as an attachment. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong

[PATCH v2 04/07] RISC-V: autovec: Add auto-vectorization support functions

This patch adds support for functions used in implementing various portions of autovectorization support. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv/riscv-v.cc (riscv_classify_vlmul_field):            New function

[PATCH v2 05/07] RISC-V: autovec: Add tuning and target vectorization hooks

This patch adds support for registering target hooks for basic autovectorization support as well as basic tuning information for the vector extension. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong            * config/riscv/riscv-cores.def (RISCV_TUNE

[PATCH V2 06/07] RISC-V: autovec: Add autovectorization patterns for add & sub

This patch adds patterns that provide basic autovectorization support for integer adds and subtracts. gcc/ChangeLog: 2023-03-02  Michael Collison                Juzhe Zhong                * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include

[PATCH v2 07/07] RISC-V: autovec: Add autovectorization patterns for add & sub

This patch adds tests for autovectorization of integer add and subtract. gcc/testsuite/ChangeLog: 2023-03-02  Michael Collison                Vineet Gupta                 * gcc.target/riscv/rvv/autovec: New directory            for autovectorization tests

Re: [PATCH v2 00/07] RISC-V: autovec: Add auto-vectorization support

Thanks for the feedback, will try that next time. Michael Collison > On Mar 5, 2023, at 11:06 PM, Xi Ruoyao wrote: > > On Sun, 2023-03-05 at 22:13 -0500, Michael Collison wrote: > > /* snip */ > >> - Fixed ChangeLog email formatting > > Unfortunately it&#

[PATCH v3 0/6] RISC-V: autovec: Add auto-vectorization support

de RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Michael Collison (6): RISC-V: Add new predicates and function prototypes RISC-V: autovec: Export policy functions to global scope RISC-V:autovec: Add auto-vectorization support functions

[PATCH v3 1/6] RISC-V: autovec: Add new predicates and function prototypes

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto

[PATCH v3 3/6] RISC-V: autovec: Add auto-vectorization support functions

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_classify_vlmul_field): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto

[PATCH v3 2/6] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH v3 4/6] RISC-V: autovec: Add target vectorization hooks

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_option_override): Set riscv_vectorization_factor. (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement

[PATCH v3 5/6] RISC-V: autovec: Add autovectorization patterns for add & sub

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector

[PATCH v3 6/6] RISC-V: autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

[PATCH v2] vect: Check that vector factor is a compile-time constant

2023-03-05 Michael Collison * tree-vect-loop-manip.cc (vect_do_peeling): Use result of constant_lower_bound instead of vf in case vf is not a compile time constant. --- gcc/tree-vect-loop-manip.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc

[PATCH] vect: Verify that GET_MODE_NUNITS is power-of-2

Michael Collison * poly-int.h (exact_div_p): New function to verify that argument is a power of 2 poly_int. * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a power of 2. --- gcc/poly-int.h | 17 + gcc/tree

[PATCH] vect: Verify that GET_MODE_NUNITS is greater than one.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is greater than one. --- gcc/tree-vect-slp.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc

Re: [PATCH, gcc7, aarch64] Add arithmetic overflow patterns

Hi Richard, Note that this patch appears to depend on your previous patch: https://gcc.gnu.org/ml/gcc-patches/2016-01/txtDPaXOBMuOB.txt for the definition of define_mode_attr DWI. I was looking at this patch as I was working on Bugzilla 68543 which this will address. Regards, Michael

[PING][ARM] Re: Use vector wide add for mixed-mode adds

Second Ping. Most recent patch posted here: https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01682.html Regards, Michael Collison -- Michael Collison Linaro Toolchain Working Group michael.colli...@linaro.org

Re: [PATCH, gcc7, aarch64] Add arithmetic overflow patterns

patterns? The subv patterns expand into calls to gen_sub3_compare1 which does not emit sign or zero extends. Why the difference? On 01/28/2016 10:53 AM, Richard Henderson wrote: On 01/28/2016 01:50 AM, Michael Collison wrote: Hi Richard, Note that this patch appears to depend on your previous

Re: [ARM] Use vector wide add for mixed-mode adds

sting infrastructure with the latest trunk and the only failure is 'slp-reduc-3.c'. Okay for GCC 7? 2016-02-12 Michael Collison * config/arm/neon.md (widen_sum): New patterns where mode is VQI to improve mixed mode vectorization. * config/arm/neon.md (vec_sel_widen_ssum_lo3)

[ARM] Add support for overflow add, sub, and neg operations

Michael Collison * config/arm/arm-modes.def: Add new condition code mode CC_V to represent the overflow bit. * config/arm/arm.c (maybe_get_arm_condition_code): Add support for CC_Vmode. * config/arm/arm.md (addv4, add3_compareV, addsi3_compareV_upper): New patterns to

Re: [ARM] Add support for overflow add, sub, and neg operations

On 02/25/2016 02:51 AM, Kyrill Tkachov wrote: Hi Michael, On 24/02/16 23:02, Michael Collison wrote: This patch adds support for builtin overflow of add, subtract and negate. This patch is targeted for gcc 7 stage 1. It was tested with no regressions in arm and thumb modes on the following

[PATCH][ARM] PR target/70008

trunk? 2016-02-28 Michael Collison PR target/70008 * config/arm/arm.md (*subsi3_carryin): Only match pattern if TARGET_ARM due to 'rsc' instruction alternative. * config/arm/thumb2.md (*thumb2_subsi3_carryin): New pattern. -- Michael Collison Linaro Toolchain Wor

Re: [PATCH][ARM] PR target/70008

On 2/29/2016 4:06 AM, Kyrill Tkachov wrote: Hi Michael, On 29/02/16 04:47, Michael Collison wrote: This patches address PR 70008, where a reverse subtract with carry instruction can be generated in thumb2 mode. It was tested with no regressions in arm and thumb modes on the following

Re: [ARM] Add support for overflow add, sub, and neg operations

On 2/29/2016 4:13 AM, Kyrill Tkachov wrote: On 26/02/16 10:32, Michael Collison wrote: On 02/25/2016 02:51 AM, Kyrill Tkachov wrote: Hi Michael, On 24/02/16 23:02, Michael Collison wrote: This patch adds support for builtin overflow of add, subtract and negate. This patch is targeted

[PATCH][ARM] PR target/70014

This patches addresses PR 70014, where the predicates and operand do not match and could cause problems with the register allocator. Tested successfully on arm-none-linux-gnueabi arm-none-linux-gnuabihf armeb-none-linux-gnuabihf arm-none-eabi Okay for trunk? 2016-03-01 Michael Collison

Re: [PATCH][ARM] PR target/70008

rn out into it's own insn. I'm testing this change now. Let me know if this direction is okay with you. On 02/29/2016 08:29 AM, Richard Earnshaw (lists) wrote: On 29/02/16 11:21, Michael Collison wrote: On 2/29/2016 4:06 AM, Kyrill Tkachov wrote: Hi Michael, On 29/02/16 04:47, Micha

Re: [PATCH][ARM] PR target/70008

Okay for trunk? 2016-02-28 Michael Collison PR target/70008 * config/arm/arm.md (*subsi3_carryin): Change predicate to arm_rhs_operand to be consistent with constraints. Only allow pattern for TARGET_ARM. * config/arm/thumb2.md (*thumb2_subsi3_carryin): New pattern. On 02/2

Re: [ARM] Optimize compare against smin/umin

Here is an updated patch that addresses the issues you mentioned: 2015-07-24 Michael Collison * gcc/config/arm/arm.md (*arm_smin_cmp): New pattern. (*arm_umin_cmp): Likewise. * gcc.target/arm/mincmp.c: Test min compare idiom. diff --git a/gcc/config

[PATCH] Optimize certain end of loop conditions into min/max operation

unsignedint m, unsignedint n) { unsignedint i, bound = (m < n) ? m : n; for (i = 0; i < m && i < n; ++i) a[i] = b[i] + c[i]; } Performed bootstrap and make check on: x86_64_unknown-linux-gnu, arm-linux-gnueabihf, and aarch64-linux-gnu. Okay for trunk? 2015-07-24 Micha

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

at 5:41 AM, Michael Collison wrote: This patch is designed to optimize end of loop conditions involving of the form i < x && i < y into i < min (x, y). Loop condition involving '>' are handled similarly using max(x,y). As an example: #define N 1024 in

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

Hi Jeff, Yes I will create a test case. I'm not quite sure what to check for even in the machine dependent test case. It's quite possible for the instructions that are generated to change over time. On 7/31/2015 9:20 AM, Jeff Law wrote: On 07/28/2015 01:41 AM, Richard Biener wrote: The abo

Re: [PATCH, PR 57195] Allow mode iterators inside angle brackets

On 09/14/2015 02:34 AM, Richard Sandiford wrote: Michael Collison writes: Here is a modified patch that takes your comments into account. Breaking on depth == 0 with '>' does not work due to the code looking for whitespace. What goes wrong? Just to make sure we're talk

[PING] [Aarch64] Use vector wide add for mixed-mode adds

Ping. Originally posted here: https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00408.html Regards, Michael Collison -- Michael Collison Linaro Toolchain Working Group michael.colli...@linaro.org

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

On 07/31/2015 11:27 AM, Jeff Law wrote: On 07/31/2015 12:18 PM, Michael Collison wrote: Hi Jeff, Yes I will create a test case. I'm not quite sure what to check for even in the machine dependent test case. It's quite possible for the instructions that are generated to change over tim

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

Marc, Can you elaborate on merging the patterns using 'ext' as mentioned in your post? I don't see any documentation or examples. On 09/18/2015 12:00 AM, Marc Glisse wrote: On Thu, 17 Sep 2015, Michael Collison wrote: Here is the the patch modified with test cases for MIN_EXP

Re: [ARM] Use vector wide add for mixed-mode adds

e-linux-gnueabihf. 2015-09-22 Michael Collison * config/arm/neon.md (widen_sum): New patterns where mode is VQI to improve mixed mode add vectorization. -- Michael Collison Linaro Toolchain Working Group michael.colli...@linaro.org diff --git a/gcc/config/arm/neon.md b/gcc/config/

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

ix that currently you have to replicate the merged pattern with swapped comparison operands. Otherwise I'm fine with the general approach. Richard. On Fri, 18 Sep 2015, Marc Glisse wrote: On Thu, 17 Sep 2015, Michael Collison wrote: Here is the the patch modified with test cases for

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

The current patch is attached. 2015-09-30 Michael Collison Andrew Pinski * match.pd ((x < y) && (x < z) -> x < min (y,z), (x > y) and (x > z) -> x > max (y,z)) * testsuite/gcc.dg/tree-ssa/minmax-loopend.c: New test. On 09/30/2015 01:

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

Richard and Marc, Latest patch attached which incorporates all comments. 2015-09-30 Michael Collison Andrew Pinski * match.pd ((x < y) && (x < z) -> x < min (y,z), (x > y) and (x > z) -> x > max (y,z)) * testsuite/gcc.dg/tree-ssa/minma

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

comparisons. As I was saying, :c is useless. (x:c y z) is replaced by two copies of the transformation, one with (x y z) and the other with (x z y) In your transformation, both versions would be equivalent, so the second one is redundant. Also, if you have: a=x -- Michael Collison Linaro

Re: [PATCH] Optimize certain end of loop conditions into min/max operation

Marc, Ah I did misunderstand you. Patch with match.pd formatting fix. On 10/01/2015 01:05 AM, Marc Glisse wrote: On Thu, 1 Oct 2015, Michael Collison wrote: ChangeLog formatting and test case fixed. Oups, sorry for the lack of precision, but I meant indenting the code in match.pd, I

Re: [ARM] Use vector wide add for mixed-mode adds

-flto -ffat-lto-objects execution test gcc.dg/vect/vect-outer-4l.c -flto -ffat-lto-objects execution test I am debugging but have not tracked down the root cause yet. Feedback? 2015-07-22 Michael Collison * config/arm/neon.md (widen_sum): New patterns where mode is VQI to improve mixed

Re: [ARM] Use vector wide add for mixed-mode adds

AN" "vmovl. %q0, %f1" [(set_attr "type" "neon_shift_imm_long")] These patterns are similar to the new patterns I am adding and I am wondering if my patterns should exclude BYTES_BIG_ENDIAN? On 10/08/2015 04:02 AM, Kyrill Tkachov wrote: Hi Michael, On 01/10/

[ARM][PATCH, PR 68223] arm_[su]min_cmp pattern fails

The patterns arm_smin_cmp and arm_umin_cmp patterns fail if operand 0 and operand 2 are equal and both are less than operand 1. The solution is to remove the two patterns. 2015-11-06 Michael Collison PR target/68223 * gcc/config/arm/arm.md (*arm_smin_cmp): Remove pattern

Re: [Aarch64] Use vector wide add for mixed-mode adds

Michael Collison * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) (aarch64_w_internal): New patterns * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes. * gcc.target/aarch64/saddw-1.c: New test. * gcc.target/aarch64/saddw-2.c: New test. * gcc.target/aarch64

Re: [Aarch64] Use vector wide add for mixed-mode adds

On 11/22/2015 8:48 AM, James Greenhalgh wrote: On Sun, Nov 08, 2015 at 11:51:47PM -0700, Michael Collison wrote: 2015-11-06 Michael Collison * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) (aarch64_w_internal): New patterns * config/aarch64/iterators.md (Vhalf, VDBLW

Re: [Aarch64] Use vector wide add for mixed-mode adds

This is a followup patch which addresses formatting comments posted here: https://gcc.gnu.org/ml/gcc-patches/2015-11/msg02611.html 2015-11-24 Michael Collison * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) (aarch64_w_internal): New patterns * config/aarch64/iterators.md

Re: [ARM] Use vector wide add for mixed-mode adds

bug with vector loads using VUZP operations. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68532 Validated on arm-none-eabi, arm-none-linux-gnueabi, arm-none-linux-gnueabihf, and armeb-none-linux-gnueabihf. 2015-11-29 Michael Collison * config/arm/neon.md (widen_sum): New patterns where

[PING] [ARM] Use vector wide add for mixed-mode adds

Ping. Originally posted here: https://gcc.gnu.org/ml/gcc-patches/2015-11/msg03440.html Regards, Michael Collison

[PATCH] match.pd: rewrite select to branchless expression

rate branchless code for one of the functions in coremark. Bootstrapped and tested on x86 and RISC-V. Okay? Michael. 2022-11-08  Michael Collison      * match.pd ((cond (and (x , 0x1) == 0), y, (z op y) )     -> (-(and (x , 0x1)) & z ) op y) 2022-11-08  Michael Collison      * gcc

Re: [PATCH] match.pd: rewrite select to branchless expression

    (op (bit_and (negate (convert:type (bit_and @0 { build_one_cst (type); }))) @2) @1 On 11/9/22 02:41, Richard Biener wrote: On Tue, Nov 8, 2022 at 9:02 PM Michael Collison wrote: This patches transforms (cond (and (x , 0x1) == 0), y, (z op y)) into (-(and (x , 0x1)) & z ) op y, wh

[PATCH v2] match.pd: rewrite select to branchless expression

rate branchless code for one of the functions in coremark. Bootstrapped and tested on x86 and RISC-V. Okay? Michael. 2022-11-10  Michael Collison      * match.pd ((x & 0x1) == 0) ? y : z y     -> (-(typeof(y))(x & 0x1) & z) y. 2022-11-10  Michael Collison     * gcc.dg/tree-s

Re: [PATCH v2] match.pd: rewrite select to branchless expression

: On Fri, 11 Nov 2022 at 07:58, Michael Collison wrote: This patches transforms ((x & 0x1) == 0) ? y : z y -into (-(typeof(y))(x & 0x1) & z) y, where op is a '^' or a '|'. It also transforms (cond (and (x , 0x1) != 0), (z op y), y ) into (-(and (x , 0x1)) &am

Re: [PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv.

:40 AM Michael Collison wrote: From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data

Re: [PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

ener <mailto:richard.guent...@gmail.com>; Jeff Law <mailto:jeffreya...@gmail.com>; Palmer Dabbelt <mailto:pal...@dabbelt.com> *CC:* Michael Collison <mailto:colli...@rivosinc.com>; gcc-patches <mailto:gcc-patches@gcc.gnu.org>; 钟居哲 <mailto:juzhe.zh...

Re: [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations

Hi Kito, I will remove the unused UNSPECs, thank you for finding them. I removed the include of "vector-iterators.md" because "riscv.md" already includes it and I was receiving multiple definition errors. On 4/18/23 21:19, Kito Cheng wrote: diff --git a/gcc/config/riscv/vector-iterators.md

[PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_vector_preferred_simd_mode): New. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto

[PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store

2023-04-25 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector.md: Remove

[PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

[PATCH v5 00/10] RISC-V: autovec: Add autovec support

contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Kevin Lee (2): This patch adds a guard for VNx1 vectors that are present in ports like riscv. This patch supports 8 bit auto-vectorization in riscv. Michael Collison (8): RISC-V: Add new predicates a

[PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer

2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64.

[PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv.

From: Kevin Lee Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new condition --- gcc/tree-vect-data-refs.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc index 8daf7bd7dd3..df393ba723

[PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): New function. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto

[PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv.

From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.

[PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect

[PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE

Re: [PATCH v4 05/10] RISC-V: autovec: Add autovectorization patterns for binary integer operations

Hi Robin and Juzhe, Just took a look and I like the approach. On 4/26/23 19:43, juzhe.zhong wrote: Yeah，Robin stuff is what I want and is making perfect sense for me. Replied Message FromRobin Dapp Date04/27/2023 02:15 To juzhe.zh...@rivai.ai

Re: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions

HI Kito, I see there have been many comments on the "riscv_vector_preferred_simd_mode" hook, is there an updated version? On 5/3/23 06:53, Kito Cheng wrote: @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* Implement TARGET_VECTORIZE_PRE

[PATCH v6 0/9] RISC-V: autovec: Add autovec support

ener - Used RVV_VUNDEF macro to fix failing patterns Changes in v2 - Updated ChangeLog entry to include RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Kevin Lee (1): RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv

[PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_vector_preferred_simd_mode): New. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto

[PATCH v6 5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store

2023-04-25 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector.md: Remove

[PATCH v6 2/9] RISC-V: autovec: Export policy functions to global scope

2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h

[PATCH v6 3/9] RISC-V:autovec: Add auto-vectorization support functions

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): New function. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto

[PATCH v6 4/9] RISC-V:autovec: Add target vectorization hooks

2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv.cc (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. (riscv_get_mask_mode

[PATCH v6 8/9] RISC-V:autovec: Add autovectorization tests for binary integer

2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64.

[PATCH v6 7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2.

-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect

[PATCH v6 9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv.

From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/l

[PATCH v6 6/9] RISC-V:autovec: Add autovectorization tests for add & sub

2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv

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