> Note that the ADDXC, ADDXCCC, SUBXC and SUBXCCC instructions do not
> support immediate operands. Hence the patch breaks vis3-enabling arches
> and niagara-7.
Egad. I totally overlooked this (yet the -mcpu=niagara7 -m64 testsuite is
rather explicit) and this is a bit
> Note that the ADDXC, ADDXCCC, SUBXC and SUBXCCC instructions do not
> support immediate operands. Hence the patch breaks vis3-enabling arches
> and niagara-7.
Egad. I totally overlooked this (yet the -mcpu=niagara7 -m64 testsuite is
rather explicit) and this is a bit of a shame, especially fo
Hi Eric.
+(define_insn "*plus_sltu_vis3"
+ [(set (match_operand:W 0 "register_operand" "=r")
+ (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
+ (const_int 0))
+ (match_operand:W 1 "arith_operand" "rI")))]
+ "TARGET_ARCH64 && TARG
This was initially in preparation for the overflow checking support and aimed
at untangling CCCmode and CC_NOOVmode, but ends up doing a little more:
- add TARGET_FIXED_CONDITION_CODE_REGS hook to eliminate more explicitly
redundant comparisons and, on V9, to generate more movcc instructions.
