Am 08.02.2011 um 08:44 schrieb rickman:
Do you expect these tools to be used to design chips costing far,
far over $3 Million just for the mask set?
I'm trying to think 20 years into the future. Especially if it's only
a matter of allowing a compile time flag or not.
Markus
- - - - -
On Feb 7, 2011, at 2:05 PM, Markus Hitter wrote:
Isn't a nanometer pretty big when doing chip design? Others might have
more/any experience in this area.
I doubt PCB will ever be a suitable tool for chip design.
1 nm is good enough for models that assume materials are continuous and
On 08/02/11 09:20, Markus Hitter wrote:
Am 08.02.2011 um 08:44 schrieb rickman:
Do you expect these tools to be used to design chips costing far, far
over $3 Million just for the mask set?
I'm trying to think 20 years into the future. Especially if it's only a
matter of allowing a
John Doty j...@noqsi.com writes:
I doubt PCB will ever be a suitable tool for chip design.
Why? It should not make that a priority. But the hierachical features
outlined elsewhere, layer types, a sufficiently generic via mechanism,
its not too far from making it possible to do chip design.
On Feb 8, 2011, at 3:48 AM, Stephan Boettcher wrote:
John Doty j...@noqsi.com writes:
I doubt PCB will ever be a suitable tool for chip design.
Why?
Because it's far too ad hoc in its design. It's a collection of special
features, lacking any fundamental notion of a design as a
On Feb 4, 2011, at 9:07 PM, Kai-Martin Knaak wrote:
Another cite from the master attribute list:
A basic problem is that the master attribute list, symbol creation guide, and
gsymcheck all represent a much narrower vision than the actual breadth of the
gEDA application space. A symbol
From: rickman [1]gnuarm.g...@arius.com
Date: Tue, 08 Feb 2011 02:44:09 -0500
Subject: Re: gEDA-user: transition of pcb internal units to metric
(SI, mm)
The cost to [1]tape-out a chip at 90 nm is at least US$1,000,000 and
exceeds US$3,000,000 for 65 nm.^[2][40]
Do you
Andrew Miner wrote:
The current standard for wafer diameter is 300 mm (11.8) = 109 sq inches.
You would loose about 1/4 of the area to the edge effects on the wafer so
you are looking at ~75 in sq of usable space. When you consider that most
of the parts that we use on our PCBs have an IC die
On Feb 7, 2011, at 10:41 AM, DJ Delorie wrote:
* nanometer internal units
* 32-bit values on 32-bit machines, 64-bit on 64-bit.
* configure option for 64-bit values regardless of machine in case you
need a board larger than seven feet across.
What about storing both imperial and
From: David Smith [1]dave.sm...@st.com
Date: Tue, 8 Feb 2011 14:32:24 +
I am not an expert on ASIC manufacture, but I think that you've made
some incorrect assumptions there.
Yes, the standard wafer at current cutting-edge processes is 300 mm
(although for older and
On Tue, 8 Feb 2011 07:27:01 -0800
Edward Hennessy ehen...@sbcglobal.net wrote:
On Feb 7, 2011, at 10:41 AM, DJ Delorie wrote:
* nanometer internal units
* 32-bit values on 32-bit machines, 64-bit on 64-bit.
* configure option for 64-bit values regardless of machine in case
you
John Coppens wrote:
So, the soldering
point has a fine layer of a metal which does accept solder, deposited
during the manufacturing.
IMHO, this layer is usually iron and not that fine -- abut half a mm.
There might be some additional chemical activation involved. But I am
not sure.
If
On 2/8/2011 12:23 PM, Colin D Bennett wrote:
On Tue, 8 Feb 2011 07:27:01 -0800
Edward Hennessyehen...@sbcglobal.net wrote:
On Feb 7, 2011, at 10:41 AM, DJ Delorie wrote:
* nanometer internal units
* 32-bit values on 32-bit machines, 64-bit on 64-bit.
* configure option for 64-bit values
On 2/8/2011 11:24 AM, Andrew Miner wrote:
From: David Smith[1]dave.sm...@st.com
Date: Tue, 8 Feb 2011 14:32:24 +
I am not an expert on ASIC manufacture, but I think that you've made
some incorrect assumptions there.
Yes, the standard wafer at current
Am 08.02.2011 12:17, schrieb John Doty:
On Feb 8, 2011, at 3:48 AM, Stephan Boettcher wrote:
John Doty j...@noqsi.com writes:
I doubt PCB will ever be a suitable tool for chip design.
Why?
Because it's far too ad hoc in its design. It's a collection of
special features, lacking any
Am 08.02.2011 10:14, schrieb Link:
Seeing as 32-bit operating systems (even on 64-bit machines!) are still
widely used, and anything smaller than a nanometre is overkill for the
time being, I'd say playing nice with 32-bit is, at the moment, more
important than making sure people can design
rickman wrote:
This is past the point of being silly. IC design was brought into this
conversation to justify changing the tools to record dimensions down to
picometer levels.
Let's aim for the lowest possible denominator: The Planck length!
Stephan Boettcher wrote:
I doubt PCB will ever be a suitable tool for chip design.
Why?
Because a jack-of-all-trades is an expert in none.
---)kaimartin(---
--
Kai-Martin Knaak
Email: k...@familieknaak.de
Öffentlicher PGP-Schlüssel:
So I have a 25 page schematic, and I want to do some rudimentary checks
on it. For example I would like to know if I wired power pins to gnd
pins or only have inputs or outputs on a given net.
What tools does geda have for this type of checking?
What
Oliver King-Smith wrote:
So I have a 25 page schematic, and I want to do some rudimentary checks on
it.
For example I would like to know if I wired power pins to gnd pins or only
have
inputs or outputs on a given net.
What tools does geda have for this type of checking?
I have defined a number of symbols with an embedded part # for ease of
ordering. An example of such a part # is
T 700 1000 8 10 0 0 0 0 1
part_number=PMBS3904
This is visible on the schematic (if you turn on invisible text).
However when I run gattrib on the schematic with this
On Feb 8, 2011, at 7:08 PM, Oliver King-Smith wrote:
Does anyone know if this is a feature or bug?
It's the way it works. Whether it's a bug depends on what you're trying to do.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com
22 matches
Mail list logo
