[gem5-dev] Change in gem5/gem5[master]: sim: Clean up some mild style bugs in clocked_object.hh.

Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/20088 ) Change subject: sim: Clean up some mild style bugs in clocked_object.hh. .. sim: Clean up some mild style bugs in

[gem5-dev] Change in gem5/gem5[master]: arch-x86: Updating fault condition for write to cr4

Hello kokoro, Gabe Black, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19892 to look at the new patch set (#3). Change subject: arch-x86: Updating fault condition for write to cr4

[gem5-dev] Change in gem5/gem5[master]: arch-x86: Updating fault condition for write to cr4

Hello kokoro, Gabe Black, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19892 to look at the new patch set (#2). Change subject: arch-x86: Updating fault condition for write to cr4

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MI

Pouya Fotouhi has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19888 ) Change subject: mem-ruby: Use check_on_cache_probe on MI .. mem-ruby: Use check_on_cache_probe on MI This change uses

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MOESI

Pouya Fotouhi has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19890 ) Change subject: mem-ruby: Use check_on_cache_probe on MOESI .. mem-ruby: Use check_on_cache_probe on MOESI This change

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MOESI hammer

Pouya Fotouhi has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19891 ) Change subject: mem-ruby: Use check_on_cache_probe on MOESI hammer .. mem-ruby: Use check_on_cache_probe on MOESI hammer

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MOESI CMP

Pouya Fotouhi has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19908 ) Change subject: mem-ruby: Use check_on_cache_probe on MOESI CMP .. mem-ruby: Use check_on_cache_probe on MOESI CMP This

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Update Page Table Entry

YIFEI LIU has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20108 ) Change subject: arch-riscv: Update Page Table Entry .. arch-riscv: Update Page Table Entry This patch updates the

Re: [gem5-dev] Remote GDB with Multiple Instruction Widths?

In x86, a software breakpoint is generally only one byte, the int3 instruction which is defined for that purpose. It's put at the start of whatever instruction you want to catch. In other ISAs like ARM which have different instruction sizes, I'm assuming gdb either figures out what the size of the

[gem5-dev] Change in gem5/gem5[master]: sim: Clean up some mild style bugs in clocked_object.hh.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20088 ) Change subject: sim: Clean up some mild style bugs in clocked_object.hh. .. sim: Clean up some mild style bugs in

[gem5-dev] Change in gem5/gem5[master]: sim: Add a hook Clocked objects can implement for frequency changes.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20089 ) Change subject: sim: Add a hook Clocked objects can implement for frequency changes. .. sim: Add a hook

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix invalid whenReady

Daniel Carvalho has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20068 ) Change subject: mem-cache: Fix invalid whenReady .. mem-cache: Fix invalid whenReady When a writeback needs

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

Jordi Vaquero has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19812 ) Change subject: arch-arm: Added LD/ST atomic instruction family and SWP instrs .. arch-arm: Added LD/ST atomic

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe to protect locked lines from eviction

Pouya Fotouhi has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19868 ) Change subject: mem-ruby: Use check_on_cache_probe to protect locked lines from eviction .. mem-ruby: Use

[gem5-dev] Change in gem5/gem5[master]: python: FdtState using interrupt-cells

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/20050 ) Change subject: python: FdtState using interrupt-cells .. python: FdtState using interrupt-cells Change-Id:

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe to protect locked lines from eviction

Pouya Fotouhi has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/16809 ) Change subject: mem-ruby: Use check_on_cache_probe to protect locked lines from eviction .. mem-ruby: Use

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Enable DTB autogeneration in GICv3

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/20053 ) Change subject: dev-arm: Enable DTB autogeneration in GICv3 .. dev-arm: Enable DTB autogeneration in GICv3

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Fix PCI node's interrupt-map property

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/20052 ) Change subject: dev-arm: Fix PCI node's interrupt-map property .. dev-arm: Fix PCI node's interrupt-map property

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Use FdtState to generate GIC properites

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/20051 ) Change subject: dev-arm: Use FdtState to generate GIC properites .. dev-arm: Use FdtState to generate GIC properites

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

Jordi Vaquero has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19811 ) Change subject: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func .. arch-arm: Adding CAS/CASP AMO

[gem5-dev] Change in gem5/gem5[master]: sim-se: rename Process::setpgid member

Brandon Potter has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/20008 ) Change subject: sim-se: rename Process::setpgid member .. sim-se: rename Process::setpgid member The getter methods to

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs

Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 to look at the new patch set (#13). Change subject: arch-arm: Added LD/ST atomic instruction family and SWP instrs

[gem5-dev] Change in gem5/gem5[master]: python: FdtState using interrupt-cells

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20050 to review the following change. Change subject: python: FdtState using interrupt-cells ..

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Enable DTB autogeneration in GICv3

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20053 to review the following change. Change subject: dev-arm: Enable DTB autogeneration in GICv3

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Fix PCI node's interrupt-map property

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20052 to review the following change. Change subject: dev-arm: Fix PCI node's interrupt-map property

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Use FdtState to generate GIC properites

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20051 to review the following change. Change subject: dev-arm: Use FdtState to generate GIC properites

[gem5-dev] Change in gem5/gem5[master]: base: assert that stats bucket size is greater than 0

Ciro Santilli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20049 ) Change subject: base: assert that stats bucket size is greater than 0 .. base: assert that stats bucket size

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20048 to look at the new patch set (#2). Change subject: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

Ciro Santilli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20048 ) Change subject: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0 .. arch-arm, cpu: fix ARM ubsan build on GCC

[gem5-dev] Change in gem5/gem5[master]: misc: Update MAINTAINERS with a system tag

Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19931 ) Change subject: misc: Update MAINTAINERS with a system tag .. misc: Update MAINTAINERS with a system tag The code in