Can I pipe up and tell you I agree? I also think it’s better to get the basic support implemented and then expand it incrementally.
Many thanks to Alec for all the effort, and also to Jason for the shepherding. Steve From: Jason Lowe-Power Sent: Monday, November 21, 2016 9:08 AM To: gem5 Developer List Subject: Re: [gem5-dev] RISC-V Patches Hi Alec, I think it's fine to push without 100% of the possible features working. If we waited until every possible feature was working we'd never push any patches ;). Just getting the RISCV support out there and letting others use it is what's most important, IMO. Others can pipe up and tell me I'm wrong, though! Jason On Mon, Nov 21, 2016 at 11:05 AM Alec Roelke <ar...@virginia.edu> wrote: > Hi Jason, > > I had removed the tests from the regression patch that fail due to the > error I pointed out in my initial message because I didn't think it was > appropriate to include failing tests in a gem5 release, and had planned to > add them when the bug was fixed. I'm pretty busy at the moment with > several deadlines in the next few weeks, so I don't know if I'll be able to > get to it anytime soon. > > Thanks, > Alec > > On Mon, Nov 21, 2016 at 11:31 AM, Jason Lowe-Power <ja...@lowepower.com> > wrote: > > > Hi Alec, > > > > These are ready according to me. Unless someone has an objection, I'll > push > > them on Friday (assuming I can get up after all the food on Thursday). > > > > Note: All of the tests are passing for me with minor changes in the > > instruction rates, etc. > > > > Thanks again for these patches. I think that this is one of the most > > important additions to gem5 in a while :). > > > > Cheers, > > Jason > > > > On Sun, Nov 20, 2016 at 2:20 PM Alec Roelke <ar...@virginia.edu> wrote: > > > > > Hello Everyone, > > > > > > It has been about two weeks since the last review for my 8 RISC-V > patches > > > except the 7th patch, so it seems to me like most of them can be > > > committed? The patches are: > > > - 3624 (arch: [Patch 1/5] Added RISC-V base instruction set RV64I) > > > - 3627 (riscv: [Patch 2/5] Added RISC-V multiply extension RV64M) > > > - 3628 (riscv: [Patch 3/5] Added RISCV floating point extensions > RV64FD) > > > - 3629 (riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A) > > > - 3630 (riscv: [Patch 5/5] Added missing support for timing CPU models) > > > - 3668 (riscv: [Patch 6/5] Improve Linux emulation for RISC-V) > > > - 3693 (riscv: [Patch 7/5] Corrected LRSC semantics) > > > - 3694 (riscv: [Patch 8/5] Added some regression tests to RISC-V) > > > > > > There is a bug that sometimes occurs with the O3 CPU model where a > memory > > > access may cross a cache line boundary (see the first comment chain of > > > patch 3693) and cause a panic. I have not encountered this except when > > > trying to run some of the regression tests I made for patch 3694 on O3. > > It > > > would make the most sense to change patch 3624 to fix it, but since > that > > > would delay shipping it, I think it would be better to make a new > patch. > > > > > > Thanks, > > > Alec Roelke > > > _______________________________________________ > > > gem5-dev mailing list > > > gem5-dev@gem5.org > > > http://m5sim.org/mailman/listinfo/gem5-dev > > > > > _______________________________________________ > > gem5-dev mailing list > > gem5-dev@gem5.org > > http://m5sim.org/mailman/listinfo/gem5-dev > > > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
