Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68798?usp=email )
Change subject: stdlib: make cache size optional in classic
......................................................................
stdlib: make cache size optional in classic
Makes cache size optional for classic cache hierarchy.
This is required because the user will be able to provide is own cache class
with the size already set.
The classic and ruby now have different interface, one with optional
size and the other with non optional size.
This causes problem with the shared abstract classes
Abstract{Two,Three}LevelCacheHierarchy.
This class was not doing much, the easiest solution was to remove it.
Change-Id: I3ed9fa6a9296c5945831806150f2a295c69ccdec
---
M src/python/SConscript
D
src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py
D
src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
M src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
A src/python/gem5/components/cachehierarchies/classic/utils.py
M
src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
11 files changed, 167 insertions(+), 247 deletions(-)
diff --git a/src/python/SConscript b/src/python/SConscript
index aeeb892..c150935 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -59,10 +59,6 @@
'gem5/components/cachehierarchies/__init__.py')
PySource('gem5.components.cachehierarchies',
'gem5/components/cachehierarchies/abstract_cache_hierarchy.py')
-PySource('gem5.components.cachehierarchies',
- 'gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py')
-PySource('gem5.components.cachehierarchies',
- 'gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py')
PySource('gem5.components.cachehierarchies.chi',
'gem5/components/cachehierarchies/chi/__init__.py')
PySource('gem5.components.cachehierarchies.chi',
@@ -85,6 +81,8 @@
'gem5/components/cachehierarchies/classic/'
'abstract_classic_cache_hierarchy.py')
PySource('gem5.components.cachehierarchies.classic',
+ 'gem5/components/cachehierarchies/classic/utils.py')
+PySource('gem5.components.cachehierarchies.classic',
'gem5/components/cachehierarchies/classic/no_cache.py')
PySource('gem5.components.cachehierarchies.classic',
'gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py')
diff --git
a/src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py
deleted file mode 100644
index 4d2f21a..0000000
---
a/src/python/gem5/components/cachehierarchies/abstract_three_level_cache_hierarchy.py
+++ /dev/null
@@ -1,52 +0,0 @@
-# Copyright (c) 2022 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-class AbstractThreeLevelCacheHierarchy:
- """
- An abstract three-level hierarchy with configurable size and
associativity
- for each of L1, L2, and L3 caches.
- """
-
- def __init__(
- self,
- l1i_size: str,
- l1i_assoc: int,
- l1d_size: str,
- l1d_assoc: int,
- l2_size: str,
- l2_assoc: int,
- l3_size: str,
- l3_assoc: int,
- ):
- self._l1i_size = l1i_size
- self._l1i_assoc = l1i_assoc
- self._l1d_size = l1d_size
- self._l1d_assoc = l1d_assoc
- self._l2_size = l2_size
- self._l2_assoc = l2_assoc
- self._l3_size = l3_size
- self._l3_assoc = l3_assoc
diff --git
a/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
deleted file mode 100644
index d6a035f..0000000
---
a/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py
+++ /dev/null
@@ -1,73 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-class AbstractTwoLevelCacheHierarchy:
- """
- An abstract two-level hierarchy with a configurable L1 and L2 size and
- associativity.
- """
-
- def __init__(
- self,
- l1i_size: str,
- l1i_assoc: int,
- l1d_size: str,
- l1d_assoc: int,
- l2_size: str,
- l2_assoc: int,
- ):
- """
- :param l1i_size: The size of the L1 Instruction cache
(e.g. "32kB").
-
- :type l1i_size: str
-
- :param l1i_assoc:
-
- :type l1i_assoc: int
-
- :param l1d_size: The size of the L1 Data cache (e.g. "32kB").
-
- :type l1d_size: str
-
- :param l1d_assoc:
-
- :type l1d_assoc: int
-
- :param l2_size: The size of the L2 cache (e.g., "256kB").
-
- :type l2_size: str
-
- :param l2_assoc:
-
- :type l2_assoc: int
- """
- self._l1i_size = l1i_size
- self._l1i_assoc = l1i_assoc
- self._l1d_size = l1d_size
- self._l1d_assoc = l1d_assoc
- self._l2_size = l2_size
- self._l2_assoc = l2_assoc
diff --git
a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
index 6329b56..6f3ab04 100644
--- a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
+++ b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
@@ -34,7 +34,7 @@
A simple L2 Cache with default values.
"""
- size = "512kB"
+ size = "256kB"
assoc = 16
tag_latency = 10
data_latency = 10
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
index dc44c9e..ea2a8e8 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
@@ -31,8 +31,11 @@
from .caches.mmu_cache import MMUCache
from ...boards.abstract_board import AbstractBoard
from ....isas import ISA
-
from m5.objects import Cache, BaseXBar, SystemXBar, BadAddr, Port
+from typing import Optional
+
+from .utils import add_caches
+
from ....utils.override import *
@@ -58,8 +61,10 @@
def __init__(
self,
- l1d_size: str,
- l1i_size: str,
+ l1d_size: Optional[str] = None,
+ l1i_size: Optional[str] = None,
+ l1d_assoc: Optional[int] = None,
+ l1i_assoc: Optional[int] = None,
membus: BaseXBar = _get_default_membus.__func__(),
) -> None:
"""
@@ -76,6 +81,9 @@
self._l1d_size = l1d_size
self._l1i_size = l1i_size
+ self._l1i_assoc = l1i_assoc
+ self._l1d_assoc = l1d_assoc
+
@overrides(AbstractClassicCacheHierarchy)
def get_mem_side_port(self) -> Port:
return self.membus.mem_side_ports
@@ -93,15 +101,21 @@
for cntr in board.get_memory().get_memory_controllers():
cntr.port = self.membus.mem_side_ports
- self.l1icaches = [
- L1ICache(size=self._l1i_size)
- for i in range(board.get_processor().get_num_cores())
- ]
+ _num_cores = board.get_processor().get_num_cores()
- self.l1dcaches = [
- L1DCache(size=self._l1d_size)
- for i in range(board.get_processor().get_num_cores())
- ]
+ self.l1icaches = add_caches(
+ cache=L1ICache,
+ num_caches=_num_cores,
+ size=self._l1i_size,
+ assoc=self._l1i_assoc,
+ )
+ self.l1dcaches = add_caches(
+ cache=L1DCache,
+ num_caches=_num_cores,
+ size=self._l1d_size,
+ assoc=self._l1d_assoc,
+ )
+
# ITLB Page walk caches
self.iptw_caches = [
MMUCache(size="8KiB")
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index f10828b..80319e1 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -26,7 +26,6 @@
from ..abstract_cache_hierarchy import AbstractCacheHierarchy
from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
-from ..abstract_two_level_cache_hierarchy import
AbstractTwoLevelCacheHierarchy
from .caches.l1dcache import L1DCache
from .caches.l1icache import L1ICache
from .caches.l2cache import L2Cache
@@ -34,13 +33,15 @@
from ...boards.abstract_board import AbstractBoard
from ....isas import ISA
from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
+from typing import Optional
+
+from .utils import add_buses, add_caches
+
from ....utils.override import *
-class PrivateL1PrivateL2CacheHierarchy(
- AbstractClassicCacheHierarchy, AbstractTwoLevelCacheHierarchy
-):
+class PrivateL1PrivateL2CacheHierarchy(AbstractClassicCacheHierarchy):
"""
A cache setup where each core has a private L1 Data and Instruction
Cache,
and a private L2 cache.
@@ -64,9 +65,12 @@
def __init__(
self,
- l1d_size: str,
- l1i_size: str,
- l2_size: str,
+ l1d_size: Optional[str] = None,
+ l1i_size: Optional[str] = None,
+ l2_size: Optional[str] = None,
+ l1d_assoc: Optional[int] = None,
+ l1i_assoc: Optional[int] = None,
+ l2_assoc: Optional[int] = None,
membus: BaseXBar = _get_default_membus.__func__(),
) -> None:
"""
@@ -89,15 +93,13 @@
"""
AbstractClassicCacheHierarchy.__init__(self=self)
- AbstractTwoLevelCacheHierarchy.__init__(
- self,
- l1i_size=l1i_size,
- l1i_assoc=8,
- l1d_size=l1d_size,
- l1d_assoc=8,
- l2_size=l2_size,
- l2_assoc=4,
- )
+ self._l1i_size = l1i_size
+ self._l1d_size = l1d_size
+ self._l2_size = l2_size
+
+ self._l1i_assoc = l1i_assoc
+ self._l1d_assoc = l1d_assoc
+ self._l2_assoc = l2_assoc
self.membus = membus
@@ -118,21 +120,31 @@
for cntr in board.get_memory().get_memory_controllers():
cntr.port = self.membus.mem_side_ports
- self.l1icaches = [
- L1ICache(size=self._l1i_size)
- for i in range(board.get_processor().get_num_cores())
- ]
- self.l1dcaches = [
- L1DCache(size=self._l1d_size)
- for i in range(board.get_processor().get_num_cores())
- ]
- self.l2buses = [
- L2XBar() for i in range(board.get_processor().get_num_cores())
- ]
- self.l2caches = [
- L2Cache(size=self._l2_size)
- for i in range(board.get_processor().get_num_cores())
- ]
+ _num_cores = board.get_processor().get_num_cores()
+
+ self.l1icaches = add_caches(
+ cache=L1ICache,
+ num_caches=_num_cores,
+ size=self._l1i_size,
+ assoc=self._l1i_assoc,
+ )
+
+ self.l1dcaches = add_caches(
+ cache=L1DCache,
+ num_caches=_num_cores,
+ size=self._l1d_size,
+ assoc=self._l1d_assoc,
+ )
+
+ self.l2buses = add_buses(bus=L2XBar, num_buses=_num_cores)
+
+ self.l2caches = add_caches(
+ cache=L2Cache,
+ num_caches=_num_cores,
+ size=self._l2_size,
+ assoc=self._l2_assoc,
+ )
+
# ITLB Page walk caches
self.iptw_caches = [
MMUCache(size="8KiB")
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
index 602c99c..c7f3fee 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
@@ -26,7 +26,6 @@
from ..abstract_cache_hierarchy import AbstractCacheHierarchy
from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
-from ..abstract_two_level_cache_hierarchy import
AbstractTwoLevelCacheHierarchy
from .caches.l1dcache import L1DCache
from .caches.l1icache import L1ICache
from .caches.l2cache import L2Cache
@@ -34,13 +33,14 @@
from ...boards.abstract_board import AbstractBoard
from ....isas import ISA
from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
+from typing import Optional
+
+from .utils import add_buses, add_caches
from ....utils.override import *
-class PrivateL1SharedL2CacheHierarchy(
- AbstractClassicCacheHierarchy, AbstractTwoLevelCacheHierarchy
-):
+class PrivateL1SharedL2CacheHierarchy(AbstractClassicCacheHierarchy):
"""
A cache setup where each core has a private L1 Data and Instruction
Cache,
and a L2 cache is shared with all cores. The shared L2 cache is mostly
@@ -65,12 +65,12 @@
def __init__(
self,
- l1d_size: str,
- l1i_size: str,
- l2_size: str,
- l1d_assoc: int = 8,
- l1i_assoc: int = 8,
- l2_assoc: int = 16,
+ l1d_size: Optional[str] = None,
+ l1i_size: Optional[str] = None,
+ l2_size: Optional[str] = None,
+ l1d_assoc: Optional[int] = None,
+ l1i_assoc: Optional[int] = None,
+ l2_assoc: Optional[int] = None,
membus: BaseXBar = _get_default_membus.__func__(),
) -> None:
"""
@@ -85,15 +85,13 @@
"""
AbstractClassicCacheHierarchy.__init__(self=self)
- AbstractTwoLevelCacheHierarchy.__init__(
- self,
- l1i_size=l1i_size,
- l1i_assoc=l1i_assoc,
- l1d_size=l1d_size,
- l1d_assoc=l1d_assoc,
- l2_size=l2_size,
- l2_assoc=l2_assoc,
- )
+ self._l1i_size = l1i_size
+ self._l1d_size = l1d_size
+ self._l2_size = l2_size
+
+ self._l1i_assoc = l1i_assoc
+ self._l1d_assoc = l1d_assoc
+ self._l2_assoc = l2_assoc
self.membus = membus
@@ -114,20 +112,31 @@
for cntr in board.get_memory().get_memory_controllers():
cntr.port = self.membus.mem_side_ports
- self.l1icaches = [
- L1ICache(
- size=self._l1i_size,
- assoc=self._l1i_assoc,
- writeback_clean=False,
- )
- for i in range(board.get_processor().get_num_cores())
- ]
- self.l1dcaches = [
- L1DCache(size=self._l1d_size, assoc=self._l1d_assoc)
- for i in range(board.get_processor().get_num_cores())
- ]
- self.l2bus = L2XBar()
- self.l2cache = L2Cache(size=self._l2_size, assoc=self._l2_assoc)
+ _num_cores = board.get_processor().get_num_cores()
+
+ self.l1icaches = add_caches(
+ cache=L1ICache,
+ num_caches=_num_cores,
+ size=self._l1i_size,
+ assoc=self._l1i_assoc,
+ )
+
+ self.l1dcaches = add_caches(
+ cache=L1DCache,
+ num_caches=_num_cores,
+ size=self._l1d_size,
+ assoc=self._l1d_assoc,
+ )
+
+ self.l2bus = add_buses(bus=L2XBar, num_buses=1)[0]
+
+ self.l2cache = add_caches(
+ cache=L2Cache,
+ num_caches=1,
+ size=self._l2_size,
+ assoc=self._l2_assoc,
+ )[0]
+
# ITLB Page walk caches
self.iptw_caches = [
MMUCache(size="8KiB", writeback_clean=False)
diff --git a/src/python/gem5/components/cachehierarchies/classic/utils.py
b/src/python/gem5/components/cachehierarchies/classic/utils.py
new file mode 100644
index 0000000..a6e3bb3
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/classic/utils.py
@@ -0,0 +1,30 @@
+from m5.objects import NULL
+from typing import Optional
+
+from m5.objects import (
+ Cache,
+ BaseXBar,
+)
+
+
+def add_caches(
+ cache: Cache,
+ num_caches: int,
+ size: Optional[str] = None,
+ assoc: Optional[int] = None,
+):
+
+ caches = [cache() for _ in range(num_caches)]
+
+ for cache in caches:
+ if size:
+ cache.size = size
+ if assoc:
+ cache.assoc = assoc
+
+ return caches
+
+
+def add_buses(bus: BaseXBar, num_buses: int):
+ buses = [bus() for _ in range(num_buses)]
+ return buses
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
index 89b6b21..cd2d388 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
@@ -26,9 +26,6 @@
from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
-from ..abstract_three_level_cache_hierarchy import (
- AbstractThreeLevelCacheHierarchy,
-)
from ....coherence_protocol import CoherenceProtocol
from ....isas import ISA
from ...boards.abstract_board import AbstractBoard
@@ -44,9 +41,7 @@
from m5.objects import RubySystem, RubySequencer, DMASequencer,
RubyPortProxy
-class MESIThreeLevelCacheHierarchy(
- AbstractRubyCacheHierarchy, AbstractThreeLevelCacheHierarchy
-):
+class MESIThreeLevelCacheHierarchy(AbstractRubyCacheHierarchy):
"""A three-level private-L1-private-L2-shared-L3 MESI hierarchy.
The on-chip network is a point-to-point all-to-all simple network.
@@ -65,17 +60,14 @@
num_l3_banks: int,
):
AbstractRubyCacheHierarchy.__init__(self=self)
- AbstractThreeLevelCacheHierarchy.__init__(
- self,
- l1i_size=l1i_size,
- l1i_assoc=l1i_assoc,
- l1d_size=l1d_size,
- l1d_assoc=l1d_assoc,
- l2_size=l2_size,
- l2_assoc=l2_assoc,
- l3_size=l3_size,
- l3_assoc=l3_assoc,
- )
+ self._l1i_size = l1i_size
+ self._l1i_assoc = l1i_assoc
+ self._l1d_size = l1d_size
+ self._l1d_assoc = l1d_assoc
+ self._l2_size = l2_size
+ self._l2_assoc = l2_assoc
+ self._l3_size = l3_size
+ self._l3_assoc = l3_assoc
self._num_l3_banks = num_l3_banks
@@ -98,6 +90,7 @@
self._l1_controllers = []
self._l2_controllers = []
self._l3_controllers = []
+
cores = board.get_processor().get_cores()
for core_idx, core in enumerate(cores):
l1_cache = L1Cache(
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index 79c8b0a..273b4ed 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -26,7 +26,6 @@
from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
-from ..abstract_two_level_cache_hierarchy import
AbstractTwoLevelCacheHierarchy
from ....coherence_protocol import CoherenceProtocol
from ....isas import ISA
from ...boards.abstract_board import AbstractBoard
@@ -41,9 +40,7 @@
from m5.objects import RubySystem, RubySequencer, DMASequencer,
RubyPortProxy
-class MESITwoLevelCacheHierarchy(
- AbstractRubyCacheHierarchy, AbstractTwoLevelCacheHierarchy
-):
+class MESITwoLevelCacheHierarchy(AbstractRubyCacheHierarchy):
"""A two level private L1 shared L2 MESI hierarchy.
In addition to the normal two level parameters, you can also change the
@@ -63,15 +60,12 @@
num_l2_banks: int,
):
AbstractRubyCacheHierarchy.__init__(self=self)
- AbstractTwoLevelCacheHierarchy.__init__(
- self,
- l1i_size=l1i_size,
- l1i_assoc=l1i_assoc,
- l1d_size=l1d_size,
- l1d_assoc=l1d_assoc,
- l2_size=l2_size,
- l2_assoc=l2_assoc,
- )
+ self._l1i_size = l1i_size
+ self._l1i_assoc = l1i_assoc
+ self._l1d_size = l1d_size
+ self._l1d_assoc = l1d_assoc
+ self._l2_size = l2_size
+ self._l2_assoc = l2_assoc
self._num_l2_banks = num_l2_banks
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
index dc66af3..35a8b80 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
@@ -44,9 +44,7 @@
from gem5.utils.override import *
-class RISCVMatchedCacheHierarchy(
- AbstractClassicCacheHierarchy, AbstractTwoLevelCacheHierarchy
-):
+class RISCVMatchedCacheHierarchy(AbstractClassicCacheHierarchy):
"""
A cache setup where each core has a private L1 Data and Instruction
Cache,
@@ -72,15 +70,12 @@
:type l2_size: str
"""
AbstractClassicCacheHierarchy.__init__(self=self)
- AbstractTwoLevelCacheHierarchy.__init__(
- self,
- l1i_size="32kB",
- l1i_assoc=4,
- l1d_size="32kB",
- l1d_assoc=8,
- l2_size=l2_size,
- l2_assoc=16,
- )
+ self._l1i_size = "32kB"
+ self._l1i_assoc = 4
+ self._l1d_size = "32kB"
+ self._l1d_assoc = 8
+ self._l2_size = l2_size
+ self._l2_assoc = 16
self.membus = SystemXBar(width=64)
self.membus.badaddr_responder = BadAddr()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3ed9fa6a9296c5945831806150f2a295c69ccdec
Gerrit-Change-Number: 68798
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet <tom.rol...@huawei.com>
Gerrit-MessageType: newchange
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