轩胡 has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67296?usp=email )
Change subject: arch-riscv,cpu-minor: Add stall signal in fetch2 stage
......................................................................
arch-riscv,cpu-minor: Add stall signal in fetch2 stage
* The execution result of `vsetvli` inst in risc-v v-ext will influence
the microop-based decoder of vector arith and mem insts.
* Decode stage will be stalled and all insts in the same cycle
after `vsetvli` will be dropped, when there is a `vsetvli` in decoder.
* The execution of `vsetvli` will resume decode stage.
Change-Id: Ic4b2c5d35eec9d8e0d8713fda998dba7b8c16ee2
---
M src/cpu/minor/fetch2.cc
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 0ff0140..dfac3cb 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -303,6 +303,7 @@
unsigned int output_index = 0;
+ bool fetch2_stall = false;
/* Pack instructions into the output while we can. This may
involve
* using more than one input line. Note that lineWidth will be 0
* for faulting lines */
@@ -310,7 +311,8 @@
(line_in->isFault() ||
fetch_info.inputIndex < line_in->lineWidth) && /* More
input */
output_index < outputWidth && /* More output to fill */
- prediction.isBubble() /* No predicted branch */)
+ prediction.isBubble() && /* No predicted branch */
+ !fetch2_stall)
{
ThreadContext *thread = cpu.getContext(line_in->id.threadId);
InstDecoder *decoder = thread->getDecoderPtr();
@@ -386,6 +388,7 @@
line_in->lineBaseAddr + fetch_info.inputIndex);
DPRINTF(Fetch, "Offering MachInst to decoder addr:
0x%x\n",
line_in->lineBaseAddr + fetch_info.inputIndex);
+ fetch2_stall = decoder->isStalled();
}
/* Maybe make the above a loop to accomodate ISAs with
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic4b2c5d35eec9d8e0d8713fda998dba7b8c16ee2
Gerrit-Change-Number: 67296
Gerrit-PatchSet: 1
Gerrit-Owner: 轩胡 <huxuan0...@gmail.com>
Gerrit-MessageType: newchange
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