Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/35835?usp=email )

 (

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: arch-x86, mem: Add support for PCID to x86
......................................................................

arch-x86, mem: Add support for PCID to x86

This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.

Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35835
Maintainer: Bobby Bruce <bbr...@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/x86/cpuid.cc
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
4 files changed, 35 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 9d1390d..4ce66df 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -109,7 +109,7 @@
                 break;
               case FamilyModelSteppingBrandFeatures:
                 result = CpuidResult(0x00020f51, 0x00000405,
-                                     0xebd3fbff, 0x00000001);
+                                     0xebd3fbff, 0x00020001);
                 break;
               case NameString1:
               case NameString2:
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 705a509..f4831b3 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -546,6 +546,7 @@
 {
     VAddr addr = vaddr;
     CR3 cr3 = tc->readMiscRegNoEffect(misc_reg::Cr3);
+    CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
     // Check if we're in long mode or not
     Efer efer = tc->readMiscRegNoEffect(misc_reg::Efer);
     dataSize = 8;
@@ -557,7 +558,6 @@
         enableNX = efer.nxe;
     } else {
         // We're in some flavor of legacy mode.
-        CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
         if (cr4.pae) {
             // Do legacy PAE.
             state = PAEPDP;
@@ -581,7 +581,10 @@
     entry.vaddr = vaddr;

     Request::Flags flags = Request::PHYSICAL;
-    if (cr3.pcd)
+
+    // PCD can't be used if CR4.PCIDE=1 [sec 2.5
+    // of Intel's Software Developer's manual]
+    if (!cr4.pcide && cr3.pcd)
         flags.set(Request::UNCACHEABLE);

     RequestPtr request = std::make_shared<Request>(
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index bca74d5..a195fdf 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -593,6 +593,17 @@
             tc->setMiscReg(misc_reg::Cr0, cr0);

             tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
+
+            // Setting CR3 to the process pid so that concatinated
+            // page addr with lower 12 bits of CR3 can be used in SE
+            // mode as well to avoid conflicts between tlb entries with
+            // same virtual addresses belonging to different processes
+            tc->setMiscReg(misc_reg::Cr3, pTable->pid());
+
+            // Setting pcide bit in CR4
+            CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
+            cr4.pcide = 1;
+            tc->setMiscReg(misc_reg::Cr4, cr4);
         }
     }
 }
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 3550384..1784142 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -621,12 +621,14 @@
                            // Base Address
     Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
                              // Base Address
+    Bitfield<11, 0> pcid; // Process-Context Identifier
     Bitfield<4> pcd; // Page-Level Cache Disable
     Bitfield<3> pwt; // Page-Level Writethrough
 EndBitUnion(CR3)

 BitUnion64(CR4)
     Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
+    Bitfield<17> pcide; // PCID Enable
     Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
                            // WRGSBASE instructions
     Bitfield<10> osxmmexcpt; // Operating System Unmasked

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35835?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Gerrit-Change-Number: 35835
Gerrit-PatchSet: 7
Gerrit-Owner: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

Reply via email to