Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63675?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: fix CHI memory controller
......................................................................
mem-ruby: fix CHI memory controller
Break up the transition to READING_MEM into two separate steps so
contention at the requestToMemory queue won't block the TBE
initialization.
JIRA: https://gem5.atlassian.net/browse/GEM5-1195
Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63675
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Bobby Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/mem/ruby/protocol/chi/CHI-mem.sm
1 file changed, 37 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/chi/CHI-mem.sm
b/src/mem/ruby/protocol/chi/CHI-mem.sm
index d7a50fd..c47d20f 100644
--- a/src/mem/ruby/protocol/chi/CHI-mem.sm
+++ b/src/mem/ruby/protocol/chi/CHI-mem.sm
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 ARM Limited
+ * Copyright (c) 2021,2022 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -119,6 +119,7 @@
Trigger_ReceiveDone, desc="";
Trigger_SendRetry, desc="";
Trigger_SendPCrdGrant, desc="";
+ Trigger_SendMemoryRead, desc="";
}
@@ -551,6 +552,14 @@
}
}
+ action(triggerSendMemoryRead, "tsmr", desc="Trigger sendMemoryRead") {
+ assert(is_valid(tbe));
+ enqueue(triggerOutPort, TriggerMsg, 0) {
+ out_msg.addr := address;
+ out_msg.event := Event:Trigger_SendMemoryRead;
+ }
+ }
+
action(sendMemoryRead, "smr", desc="Send request to memory") {
assert(is_valid(tbe));
enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
@@ -698,18 +707,23 @@
transition(READY, ReadNoSnp, READING_MEM) {
allocateTBE;
initializeFromReqTBE;
- sendMemoryRead;
+ triggerSendMemoryRead;
popReqInQueue;
}
transition(READY, ReadNoSnpSep, READING_MEM) {
allocateTBE;
initializeFromReqTBE;
- sendMemoryRead;
+ triggerSendMemoryRead;
sendReadReceipt;
popReqInQueue;
}
+ transition(READING_MEM, Trigger_SendMemoryRead) {
+ sendMemoryRead;
+ popTriggerQueue;
+ }
+
transition(READING_MEM, MemoryData, SENDING_NET_DATA) {
prepareSend;
sendDataAndCheck;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Gerrit-Change-Number: 63675
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Muck <tiago.m...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daecheol You <daecheol....@samsung.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Tiago Muck <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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