Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66592?usp=email )
Change subject: stdlib, tests: Refactor SimpleProcessor and SimpleCore
......................................................................
stdlib, tests: Refactor SimpleProcessor and SimpleCore
1. Add riscv_bits parameters to cpu_simobject_factory
2. Use Riscv32CPU if user set riscv_bits = 32
Change-Id: I411ba912a16fc870d02fe1850f387b1a5e6ecbea
---
M src/python/gem5/components/processors/simple_core.py
M src/python/gem5/components/processors/simple_processor.py
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/src/python/gem5/components/processors/simple_core.py
b/src/python/gem5/components/processors/simple_core.py
index 15e15dc..6391eda 100644
--- a/src/python/gem5/components/processors/simple_core.py
+++ b/src/python/gem5/components/processors/simple_core.py
@@ -42,7 +42,8 @@
"""
def __init__(
- self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None
+ self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None,
+ riscv_bits: int = 64,
):
# If the ISA is not specified, we infer it via the
`get_runtime_isa`
@@ -55,7 +56,8 @@
super().__init__(
core=SimpleCore.cpu_simobject_factory(
- isa=isa, cpu_type=cpu_type, core_id=core_id
+ isa=isa, cpu_type=cpu_type, core_id=core_id,
+ riscv_bits=riscv_bits,
),
isa=isa,
)
@@ -66,7 +68,9 @@
return self._cpu_type
@classmethod
- def cpu_simobject_factory(cls, cpu_type: CPUTypes, isa: ISA, core_id:
int):
+ def cpu_simobject_factory(
+ cls, cpu_type: CPUTypes, isa: ISA, core_id: int, riscv_bits: int =
64
+ ):
"""
A factory used to return the SimObject core object given the cpu
type,
and ISA target. An exception will be thrown if there is an
@@ -130,6 +134,10 @@
f"{_isa_string_map[isa]}V8"
f"{_cpu_types_string_map[cpu_type]}"
)
+ elif riscv_bits == 32:
+ cpu_class_str = (
+ f"{_isa_string_map[isa]}32"
f"{_cpu_types_string_map[cpu_type]}"
+ )
else:
cpu_class_str = (
f"{_isa_string_map[isa]}"
f"{_cpu_types_string_map[cpu_type]}"
diff --git a/src/python/gem5/components/processors/simple_processor.py
b/src/python/gem5/components/processors/simple_processor.py
index 510e37d..0cafed1 100644
--- a/src/python/gem5/components/processors/simple_processor.py
+++ b/src/python/gem5/components/processors/simple_processor.py
@@ -42,7 +42,8 @@
"""
def __init__(
- self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] = None
+ self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] =
None,
+ riscv_bits: int = 64,
) -> None:
"""
:param cpu_type: The CPU type for each type in the processor.
@@ -64,7 +65,8 @@
)
super().__init__(
cores=[
- SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa)
+ SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa,
+ riscv_bits=riscv_bits)
for i in range(num_cores)
]
)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I411ba912a16fc870d02fe1850f387b1a5e6ecbea
Gerrit-Change-Number: 66592
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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