Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24943 )
Change subject: arch-arm: make SetPCCPRS microop SerializeAfter
......................................................................
arch-arm: make SetPCCPRS microop SerializeAfter
Updating CPRS needs to be SerializeAfter to ensure that all following
instructions are executed with the new CPRS. Otherwise, for example,
the following instructions will access the banked register from the
previous mode.
The missing SerializeAfter had the consequence that the instruction rfe
(return from exception) did not work correctly with the DerivO3CPU
model.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-303
Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
---
M src/arch/arm/isa/insts/macromem.isa
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/insts/macromem.isa
b/src/arch/arm/isa/insts/macromem.isa
index 251e5c2..d9eea19 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -691,7 +691,7 @@
'MicroSetPCCPSR',
{'code': setPCCPSRDecl,
'predicate_test': predicateTest},
- ['IsMicroop'])
+ ['IsMicroop', 'IsSerializeAfter'])
header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
MicroIntImmDeclare.subst(microAddXiUopIop) + \
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Gerrit-Change-Number: 24943
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen <nilsasmuss...@gmail.com>
Gerrit-MessageType: newchange
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