Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38487 )
Change subject: config,arch,sim: Drop the useArchPT and kvmInSE params from
Process.
......................................................................
config,arch,sim: Drop the useArchPT and kvmInSE params from Process.
These flags only did anything in x86 but were present in all ISAs.
Instead, we can unconditionally use the arch PT in x86 where that
support exists, and also unconditionally use the more complete and
accurate process initialization code which is used for KVM when in SE
mode.
Since the other ISAs weren't using these flags, the only change to them
is to remove a fatal_if() that would trigger if useArchPT was set.
Change-Id: I38b454f2a3ded71a033cb1da3ef5565d9c30a509
---
M configs/example/apu_se.py
M configs/example/se.py
M src/arch/arm/process.cc
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/riscv/process.cc
M src/arch/sparc/process.cc
M src/arch/x86/linux/se_workload.cc
M src/arch/x86/process.cc
M src/sim/Process.py
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_emul.hh
13 files changed, 308 insertions(+), 410 deletions(-)
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 14f7163..5f2b7a4 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -504,9 +504,6 @@
have_kvm_support = 'BaseKvmCPU' in globals()
if have_kvm_support and buildEnv['TARGET_ISA'] == "x86":
system.vm = KvmVM()
- for i in range(len(host_cpu.workload)):
- host_cpu.workload[i].useArchPT = True
- host_cpu.workload[i].kvmInSE = True
else:
fatal("KvmCPU can only be used in SE mode with x86")
diff --git a/configs/example/se.py b/configs/example/se.py
index 9119c40..5c7a1e3 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -207,9 +207,6 @@
if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
if buildEnv['TARGET_ISA'] == 'x86':
system.kvm_vm = KvmVM()
- for process in multiprocesses:
- process.useArchPT = True
- process.kvmInSE = True
else:
fatal("KvmCPU can only be used in SE mode with x86")
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6f37d11..1cb50b7 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -64,9 +64,7 @@
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile),
arch(_arch)
-{
- fatal_if(params.useArchPT, "Arch page tables not implemented.");
-}
+{}
ArmProcess32::ArmProcess32(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 44f4f32..0b6c289 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -51,7 +51,6 @@
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
{
- fatal_if(params.useArchPT, "Arch page tables not implemented.");
// Set up stack. On MIPS, stack starts at the top of kuseg
// user address space. MIPS stack grows down from here
Addr stack_base = 0x7FFFFFFF;
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 9e8d2ad..7ff40d2 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -52,7 +52,6 @@
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
{
- fatal_if(params.useArchPT, "Arch page tables not implemented.");
// Set up break point (Top of Heap)
Addr brk_point = image.maxAddr();
brk_point = roundUp(brk_point, PageBytes);
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 10c1378..5d6a624 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -62,9 +62,7 @@
Process(params,
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
-{
- fatal_if(params.useArchPT, "Arch page tables not implemented.");
-}
+{}
RiscvProcess64::RiscvProcess64(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index b292c86..1fd2d27 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -55,7 +55,6 @@
objFile),
StackBias(_StackBias)
{
- fatal_if(params.useArchPT, "Arch page tables not implemented.");
// Initialize these to 0s
fillStart = 0;
spillStart = 0;
diff --git a/src/arch/x86/linux/se_workload.cc
b/src/arch/x86/linux/se_workload.cc
index 72170f7..ecb1f03 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -128,18 +128,15 @@
void
EmuLinux::event(ThreadContext *tc)
{
- Process *process = tc->getProcessPtr();
auto pcState = tc->pcState();
- if (process->kvmInSE) {
- Addr pc_page = mbits(pcState.pc(), 63, 12);
- if (pc_page == syscallCodeVirtAddr) {
- syscall(tc);
- return;
- } else if (pc_page == PFHandlerVirtAddr) {
- pageFault(tc);
- return;
- }
+ Addr pc_page = mbits(pcState.pc(), 63, 12);
+ if (pc_page == syscallCodeVirtAddr) {
+ syscall(tc);
+ return;
+ } else if (pc_page == PFHandlerVirtAddr) {
+ pageFault(tc);
+ return;
}
warn("Unexpected workload event at pc %#x.", pcState.pc());
}
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index cdcee31..b2df546 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -79,12 +79,8 @@
X86Process::X86Process(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
- Process(params, params.useArchPT ?
- static_cast<EmulationPageTable *>(
- new ArchPageTable(params.name, params.pid,
- params.system, PageBytes)) :
- new EmulationPageTable(params.name, params.pid,
- PageBytes),
+ Process(params, new ArchPageTable(params.name, params.pid,
+ params.system, PageBytes),
objFile)
{
}
@@ -122,8 +118,8 @@
::Loader::ObjectFile *objFile) :
X86Process(params, objFile)
{
- if (kvmInSE)
- panic("KVM CPU model does not support 32 bit processes");
+ panic_if(system->validKvmEnvironment(),
+ "KVM CPU model does not support 32 bit processes");
_gdtStart = ULL(0xffffd000);
_gdtSize = PageBytes;
@@ -173,417 +169,346 @@
vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
- if (kvmInSE) {
- PortProxy physProxy = system->physProxy;
+ PortProxy physProxy = system->physProxy;
- Addr syscallCodePhysAddr = system->allocPhysPages(1);
- Addr gdtPhysAddr = system->allocPhysPages(1);
- Addr idtPhysAddr = system->allocPhysPages(1);
- Addr istPhysAddr = system->allocPhysPages(1);
- Addr tssPhysAddr = system->allocPhysPages(1);
- Addr pfHandlerPhysAddr = system->allocPhysPages(1);
+ Addr syscallCodePhysAddr = system->allocPhysPages(1);
+ Addr gdtPhysAddr = system->allocPhysPages(1);
+ Addr idtPhysAddr = system->allocPhysPages(1);
+ Addr istPhysAddr = system->allocPhysPages(1);
+ Addr tssPhysAddr = system->allocPhysPages(1);
+ Addr pfHandlerPhysAddr = system->allocPhysPages(1);
- /*
- * Set up the gdt.
- */
- uint8_t numGDTEntries = 0;
- uint64_t nullDescriptor = 0;
- physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
- &nullDescriptor, 8);
- numGDTEntries++;
+ /*
+ * Set up the gdt.
+ */
+ uint8_t numGDTEntries = 0;
+ uint64_t nullDescriptor = 0;
+ physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
+ &nullDescriptor, 8);
+ numGDTEntries++;
- SegDescriptor initDesc = 0;
- initDesc.type.codeOrData = 0; // code or data type
- initDesc.type.c = 0; // conforming
- initDesc.type.r = 1; // readable
- initDesc.dpl = 0; // privilege
- initDesc.p = 1; // present
- initDesc.l = 1; // longmode - 64 bit
- initDesc.d = 0; // operand size
- initDesc.g = 1;
- initDesc.s = 1; // system segment
- initDesc.limit = 0xFFFFFFFF;
- initDesc.base = 0;
+ SegDescriptor initDesc = 0;
+ initDesc.type.codeOrData = 0; // code or data type
+ initDesc.type.c = 0; // conforming
+ initDesc.type.r = 1; // readable
+ initDesc.dpl = 0; // privilege
+ initDesc.p = 1; // present
+ initDesc.l = 1; // longmode - 64 bit
+ initDesc.d = 0; // operand size
+ initDesc.g = 1;
+ initDesc.s = 1; // system segment
+ initDesc.limit = 0xFFFFFFFF;
+ initDesc.base = 0;
- //64 bit code segment
- SegDescriptor csLowPLDesc = initDesc;
- csLowPLDesc.type.codeOrData = 1;
- csLowPLDesc.dpl = 0;
- uint64_t csLowPLDescVal = csLowPLDesc;
- physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
- &csLowPLDescVal, 8);
+ //64 bit code segment
+ SegDescriptor csLowPLDesc = initDesc;
+ csLowPLDesc.type.codeOrData = 1;
+ csLowPLDesc.dpl = 0;
+ uint64_t csLowPLDescVal = csLowPLDesc;
+ physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
+ &csLowPLDescVal, 8);
- numGDTEntries++;
+ numGDTEntries++;
- SegSelector csLowPL = 0;
- csLowPL.si = numGDTEntries - 1;
- csLowPL.rpl = 0;
+ SegSelector csLowPL = 0;
+ csLowPL.si = numGDTEntries - 1;
+ csLowPL.rpl = 0;
- //64 bit data segment
- SegDescriptor dsLowPLDesc = initDesc;
- dsLowPLDesc.type.codeOrData = 0;
- dsLowPLDesc.dpl = 0;
- uint64_t dsLowPLDescVal = dsLowPLDesc;
- physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
- &dsLowPLDescVal, 8);
+ //64 bit data segment
+ SegDescriptor dsLowPLDesc = initDesc;
+ dsLowPLDesc.type.codeOrData = 0;
+ dsLowPLDesc.dpl = 0;
+ uint64_t dsLowPLDescVal = dsLowPLDesc;
+ physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
+ &dsLowPLDescVal, 8);
- numGDTEntries++;
+ numGDTEntries++;
- SegSelector dsLowPL = 0;
- dsLowPL.si = numGDTEntries - 1;
- dsLowPL.rpl = 0;
+ SegSelector dsLowPL = 0;
+ dsLowPL.si = numGDTEntries - 1;
+ dsLowPL.rpl = 0;
- //64 bit data segment
- SegDescriptor dsDesc = initDesc;
- dsDesc.type.codeOrData = 0;
- dsDesc.dpl = 3;
- uint64_t dsDescVal = dsDesc;
- physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
- &dsDescVal, 8);
+ //64 bit data segment
+ SegDescriptor dsDesc = initDesc;
+ dsDesc.type.codeOrData = 0;
+ dsDesc.dpl = 3;
+ uint64_t dsDescVal = dsDesc;
+ physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
+ &dsDescVal, 8);
- numGDTEntries++;
+ numGDTEntries++;
- SegSelector ds = 0;
- ds.si = numGDTEntries - 1;
- ds.rpl = 3;
+ SegSelector ds = 0;
+ ds.si = numGDTEntries - 1;
+ ds.rpl = 3;
- //64 bit code segment
- SegDescriptor csDesc = initDesc;
- csDesc.type.codeOrData = 1;
- csDesc.dpl = 3;
- uint64_t csDescVal = csDesc;
- physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
- &csDescVal, 8);
+ //64 bit code segment
+ SegDescriptor csDesc = initDesc;
+ csDesc.type.codeOrData = 1;
+ csDesc.dpl = 3;
+ uint64_t csDescVal = csDesc;
+ physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
+ &csDescVal, 8);
- numGDTEntries++;
+ numGDTEntries++;
- SegSelector cs = 0;
- cs.si = numGDTEntries - 1;
- cs.rpl = 3;
+ SegSelector cs = 0;
+ cs.si = numGDTEntries - 1;
+ cs.rpl = 3;
- SegSelector scall = 0;
- scall.si = csLowPL.si;
- scall.rpl = 0;
+ SegSelector scall = 0;
+ scall.si = csLowPL.si;
+ scall.rpl = 0;
- SegSelector sret = 0;
- sret.si = dsLowPL.si;
- sret.rpl = 3;
+ SegSelector sret = 0;
+ sret.si = dsLowPL.si;
+ sret.rpl = 3;
- /* In long mode the TSS has been extended to 16 Bytes */
- TSSlow TSSDescLow = 0;
- TSSDescLow.type = 0xB;
- TSSDescLow.dpl = 0; // Privelege level 0
- TSSDescLow.p = 1; // Present
- TSSDescLow.limit = 0xFFFFFFFF;
- TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
+ /* In long mode the TSS has been extended to 16 Bytes */
+ TSSlow TSSDescLow = 0;
+ TSSDescLow.type = 0xB;
+ TSSDescLow.dpl = 0; // Privelege level 0
+ TSSDescLow.p = 1; // Present
+ TSSDescLow.limit = 0xFFFFFFFF;
+ TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
- TSShigh TSSDescHigh = 0;
- TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
+ TSShigh TSSDescHigh = 0;
+ TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
- struct TSSDesc {
- uint64_t low;
- uint64_t high;
- } tssDescVal = {TSSDescLow, TSSDescHigh};
+ struct TSSDesc {
+ uint64_t low;
+ uint64_t high;
+ } tssDescVal = {TSSDescLow, TSSDescHigh};
- physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
- &tssDescVal, sizeof(tssDescVal));
+ physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
+ &tssDescVal, sizeof(tssDescVal));
- numGDTEntries++;
+ numGDTEntries++;
- SegSelector tssSel = 0;
- tssSel.si = numGDTEntries - 1;
+ SegSelector tssSel = 0;
+ tssSel.si = numGDTEntries - 1;
- uint64_t tss_base_addr = (TSSDescHigh.base << 32) |
TSSDescLow.base;
- uint64_t tss_limit = TSSDescLow.limit;
+ uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base;
+ uint64_t tss_limit = TSSDescLow.limit;
- SegAttr tss_attr = 0;
+ SegAttr tss_attr = 0;
- tss_attr.type = TSSDescLow.type;
- tss_attr.dpl = TSSDescLow.dpl;
- tss_attr.present = TSSDescLow.p;
- tss_attr.granularity = TSSDescLow.g;
- tss_attr.unusable = 0;
+ tss_attr.type = TSSDescLow.type;
+ tss_attr.dpl = TSSDescLow.dpl;
+ tss_attr.present = TSSDescLow.p;
+ tss_attr.granularity = TSSDescLow.g;
+ tss_attr.unusable = 0;
- for (int i = 0; i < contextIds.size(); i++) {
- ThreadContext *tc = system->threads[contextIds[i]];
+ for (int i = 0; i < contextIds.size(); i++) {
+ ThreadContext *tc = system->threads[contextIds[i]];
- tc->setMiscReg(MISCREG_CS, cs);
- tc->setMiscReg(MISCREG_DS, ds);
- tc->setMiscReg(MISCREG_ES, ds);
- tc->setMiscReg(MISCREG_FS, ds);
- tc->setMiscReg(MISCREG_GS, ds);
- tc->setMiscReg(MISCREG_SS, ds);
+ tc->setMiscReg(MISCREG_CS, cs);
+ tc->setMiscReg(MISCREG_DS, ds);
+ tc->setMiscReg(MISCREG_ES, ds);
+ tc->setMiscReg(MISCREG_FS, ds);
+ tc->setMiscReg(MISCREG_GS, ds);
+ tc->setMiscReg(MISCREG_SS, ds);
- // LDT
- tc->setMiscReg(MISCREG_TSL, 0);
- SegAttr tslAttr = 0;
- tslAttr.present = 1;
- tslAttr.type = 2;
- tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
+ // LDT
+ tc->setMiscReg(MISCREG_TSL, 0);
+ SegAttr tslAttr = 0;
+ tslAttr.present = 1;
+ tslAttr.type = 2;
+ tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
- tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
- tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
+ tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
+ tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
- tc->setMiscReg(MISCREG_TR, tssSel);
- tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
- tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
- tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
- tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
+ tc->setMiscReg(MISCREG_TR, tssSel);
+ tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
+ tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
+ tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
+ tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
- //Start using longmode segments.
- installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
- installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
+ //Start using longmode segments.
+ installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
+ installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
+ installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
+ installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
+ installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
+ installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
- Efer efer = 0;
- efer.sce = 1; // Enable system call extensions.
- efer.lme = 1; // Enable long mode.
- efer.lma = 1; // Activate long mode.
- efer.nxe = 1; // Enable nx support.
- efer.svme = 0; // Enable svm support for now.
- efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
- tc->setMiscReg(MISCREG_EFER, efer);
+ Efer efer = 0;
+ efer.sce = 1; // Enable system call extensions.
+ efer.lme = 1; // Enable long mode.
+ efer.lma = 1; // Activate long mode.
+ efer.nxe = 1; // Enable nx support.
+ efer.svme = 0; // Enable svm support for now.
+ efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
+ tc->setMiscReg(MISCREG_EFER, efer);
- //Set up the registers that describe the operating mode.
- CR0 cr0 = 0;
- cr0.pg = 1; // Turn on paging.
- cr0.cd = 0; // Don't disable caching.
- cr0.nw = 0; // This is bit is defined to be ignored.
- cr0.am = 1; // No alignment checking
- cr0.wp = 1; // Supervisor mode can write read only pages
- cr0.ne = 1;
- cr0.et = 1; // This should always be 1
- cr0.ts = 0; // We don't do task switching, so causing fp
exceptions
- // would be pointless.
- cr0.em = 0; // Allow x87 instructions to execute natively.
- cr0.mp = 1; // This doesn't really matter, but the manual
suggests
- // setting it to one.
- cr0.pe = 1; // We're definitely in protected mode.
- tc->setMiscReg(MISCREG_CR0, cr0);
+ //Set up the registers that describe the operating mode.
+ CR0 cr0 = 0;
+ cr0.pg = 1; // Turn on paging.
+ cr0.cd = 0; // Don't disable caching.
+ cr0.nw = 0; // This is bit is defined to be ignored.
+ cr0.am = 1; // No alignment checking
+ cr0.wp = 1; // Supervisor mode can write read only pages
+ cr0.ne = 1;
+ cr0.et = 1; // This should always be 1
+ cr0.ts = 0; // We don't do task switching, so causing fp exceptions
+ // would be pointless.
+ cr0.em = 0; // Allow x87 instructions to execute natively.
+ cr0.mp = 1; // This doesn't really matter, but the manual suggests
+ // setting it to one.
+ cr0.pe = 1; // We're definitely in protected mode.
+ tc->setMiscReg(MISCREG_CR0, cr0);
- CR0 cr2 = 0;
- tc->setMiscReg(MISCREG_CR2, cr2);
+ CR0 cr2 = 0;
+ tc->setMiscReg(MISCREG_CR2, cr2);
- CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
- tc->setMiscReg(MISCREG_CR3, cr3);
+ CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
+ tc->setMiscReg(MISCREG_CR3, cr3);
- CR4 cr4 = 0;
- //Turn on pae.
- cr4.osxsave = 0; // Enable XSAVE and Proc Extended States
- cr4.osxmmexcpt = 0; // Operating System Unmasked Exception
- cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
- cr4.pce = 0; // Performance-Monitoring Counter Enable
- cr4.pge = 0; // Page-Global Enable
- cr4.mce = 0; // Machine Check Enable
- cr4.pae = 1; // Physical-Address Extension
- cr4.pse = 0; // Page Size Extensions
- cr4.de = 0; // Debugging Extensions
- cr4.tsd = 0; // Time Stamp Disable
- cr4.pvi = 0; // Protected-Mode Virtual Interrupts
- cr4.vme = 0; // Virtual-8086 Mode Extensions
+ CR4 cr4 = 0;
+ //Turn on pae.
+ cr4.osxsave = 0; // Enable XSAVE and Proc Extended States
+ cr4.osxmmexcpt = 0; // Operating System Unmasked Exception
+ cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
+ cr4.pce = 0; // Performance-Monitoring Counter Enable
+ cr4.pge = 0; // Page-Global Enable
+ cr4.mce = 0; // Machine Check Enable
+ cr4.pae = 1; // Physical-Address Extension
+ cr4.pse = 0; // Page Size Extensions
+ cr4.de = 0; // Debugging Extensions
+ cr4.tsd = 0; // Time Stamp Disable
+ cr4.pvi = 0; // Protected-Mode Virtual Interrupts
+ cr4.vme = 0; // Virtual-8086 Mode Extensions
- tc->setMiscReg(MISCREG_CR4, cr4);
+ tc->setMiscReg(MISCREG_CR4, cr4);
- CR4 cr8 = 0;
- tc->setMiscReg(MISCREG_CR8, cr8);
+ CR4 cr8 = 0;
+ tc->setMiscReg(MISCREG_CR8, cr8);
- tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
+ tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
- tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
+ tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
- tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
- tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
+ tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
+ tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
- tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
- tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
+ tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
+ tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
- /* enabling syscall and sysret */
- RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
- tc->setMiscReg(MISCREG_STAR, star);
- RegVal lstar = (RegVal)syscallCodeVirtAddr;
- tc->setMiscReg(MISCREG_LSTAR, lstar);
- RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
- tc->setMiscReg(MISCREG_SF_MASK, sfmask);
- }
-
- /* Set up the content of the TSS and write it to physical memory.
*/
-
- struct {
- uint32_t reserved0; // +00h
- uint32_t RSP0_low; // +04h
- uint32_t RSP0_high; // +08h
- uint32_t RSP1_low; // +0Ch
- uint32_t RSP1_high; // +10h
- uint32_t RSP2_low; // +14h
- uint32_t RSP2_high; // +18h
- uint32_t reserved1; // +1Ch
- uint32_t reserved2; // +20h
- uint32_t IST1_low; // +24h
- uint32_t IST1_high; // +28h
- uint32_t IST2_low; // +2Ch
- uint32_t IST2_high; // +30h
- uint32_t IST3_low; // +34h
- uint32_t IST3_high; // +38h
- uint32_t IST4_low; // +3Ch
- uint32_t IST4_high; // +40h
- uint32_t IST5_low; // +44h
- uint32_t IST5_high; // +48h
- uint32_t IST6_low; // +4Ch
- uint32_t IST6_high; // +50h
- uint32_t IST7_low; // +54h
- uint32_t IST7_high; // +58h
- uint32_t reserved3; // +5Ch
- uint32_t reserved4; // +60h
- uint16_t reserved5; // +64h
- uint16_t IO_MapBase; // +66h
- } tss;
-
- /** setting Interrupt Stack Table */
- uint64_t IST_start = ISTVirtAddr + PageBytes;
- tss.IST1_low = IST_start;
- tss.IST1_high = IST_start >> 32;
- tss.RSP0_low = tss.IST1_low;
- tss.RSP0_high = tss.IST1_high;
- tss.RSP1_low = tss.IST1_low;
- tss.RSP1_high = tss.IST1_high;
- tss.RSP2_low = tss.IST1_low;
- tss.RSP2_high = tss.IST1_high;
- physProxy.writeBlob(tssPhysAddr, &tss, sizeof(tss));
-
- /* Setting IDT gates */
- GateDescriptorLow PFGateLow = 0;
- PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
- PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
- PFGateLow.selector = csLowPL;
- PFGateLow.p = 1;
- PFGateLow.dpl = 0;
- PFGateLow.type = 0xe; // gate interrupt type
- PFGateLow.IST = 0; // setting IST to 0 and using RSP0
-
- GateDescriptorHigh PFGateHigh = 0;
- PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
-
- struct {
- uint64_t low;
- uint64_t high;
- } PFGate = {PFGateLow, PFGateHigh};
-
- physProxy.writeBlob(idtPhysAddr + 0xE0, &PFGate, sizeof(PFGate));
-
- /* System call handler */
- uint8_t syscallBlob[] = {
- // mov %rax, (0xffffc90000007000)
- 0x48, 0xa3, 0x00, 0x70, 0x00,
- 0x00, 0x00, 0xc9, 0xff, 0xff,
- // sysret
- 0x48, 0x0f, 0x07
- };
-
- physProxy.writeBlob(syscallCodePhysAddr,
- syscallBlob, sizeof(syscallBlob));
-
- /** Page fault handler */
- uint8_t faultBlob[] = {
- // mov %rax, (0xffffc90000007000)
- 0x48, 0xa3, 0x00, 0x70, 0x00,
- 0x00, 0x00, 0xc9, 0xff, 0xff,
- // add $0x8, %rsp # skip error
- 0x48, 0x83, 0xc4, 0x08,
- // iretq
- 0x48, 0xcf
- };
-
- physProxy.writeBlob(pfHandlerPhysAddr, faultBlob,
sizeof(faultBlob));
-
- /* Syscall handler */
- pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
- PageBytes, false);
- /* GDT */
- pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
- /* IDT */
- pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
- /* TSS */
- pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
- /* IST */
- pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
- /* PF handler */
- pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes,
false);
- /* MMIO region for m5ops */
- pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
- 16 * PageBytes, false);
- } else {
- for (int i = 0; i < contextIds.size(); i++) {
- ThreadContext * tc = system->threads[contextIds[i]];
-
- SegAttr dataAttr = 0;
- dataAttr.dpl = 3;
- dataAttr.unusable = 0;
- dataAttr.defaultSize = 1;
- dataAttr.longMode = 1;
- dataAttr.avl = 0;
- dataAttr.granularity = 1;
- dataAttr.present = 1;
- dataAttr.type = 3;
- dataAttr.writable = 1;
- dataAttr.readable = 1;
- dataAttr.expandDown = 0;
- dataAttr.system = 1;
-
- // Initialize the segment registers.
- for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
- tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
- tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
- tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
- }
-
- SegAttr csAttr = 0;
- csAttr.dpl = 3;
- csAttr.unusable = 0;
- csAttr.defaultSize = 0;
- csAttr.longMode = 1;
- csAttr.avl = 0;
- csAttr.granularity = 1;
- csAttr.present = 1;
- csAttr.type = 10;
- csAttr.writable = 0;
- csAttr.readable = 1;
- csAttr.expandDown = 0;
- csAttr.system = 1;
-
- tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
-
- Efer efer = 0;
- efer.sce = 1; // Enable system call extensions.
- efer.lme = 1; // Enable long mode.
- efer.lma = 1; // Activate long mode.
- efer.nxe = 1; // Enable nx support.
- efer.svme = 0; // Disable svm support for now. It isn't
implemented.
- efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
- tc->setMiscReg(MISCREG_EFER, efer);
-
- // Set up the registers that describe the operating mode.
- CR0 cr0 = 0;
- cr0.pg = 1; // Turn on paging.
- cr0.cd = 0; // Don't disable caching.
- cr0.nw = 0; // This is bit is defined to be ignored.
- cr0.am = 0; // No alignment checking
- cr0.wp = 0; // Supervisor mode can write read only pages
- cr0.ne = 1;
- cr0.et = 1; // This should always be 1
- cr0.ts = 0; // We don't do task switching, so causing fp
exceptions
- // would be pointless.
- cr0.em = 0; // Allow x87 instructions to execute natively.
- cr0.mp = 1; // This doesn't really matter, but the manual
suggests
- // setting it to one.
- cr0.pe = 1; // We're definitely in protected mode.
- tc->setMiscReg(MISCREG_CR0, cr0);
-
- tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
- }
+ /* enabling syscall and sysret */
+ RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
+ tc->setMiscReg(MISCREG_STAR, star);
+ RegVal lstar = (RegVal)syscallCodeVirtAddr;
+ tc->setMiscReg(MISCREG_LSTAR, lstar);
+ RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
+ tc->setMiscReg(MISCREG_SF_MASK, sfmask);
}
+
+ /* Set up the content of the TSS and write it to physical memory. */
+
+ struct {
+ uint32_t reserved0; // +00h
+ uint32_t RSP0_low; // +04h
+ uint32_t RSP0_high; // +08h
+ uint32_t RSP1_low; // +0Ch
+ uint32_t RSP1_high; // +10h
+ uint32_t RSP2_low; // +14h
+ uint32_t RSP2_high; // +18h
+ uint32_t reserved1; // +1Ch
+ uint32_t reserved2; // +20h
+ uint32_t IST1_low; // +24h
+ uint32_t IST1_high; // +28h
+ uint32_t IST2_low; // +2Ch
+ uint32_t IST2_high; // +30h
+ uint32_t IST3_low; // +34h
+ uint32_t IST3_high; // +38h
+ uint32_t IST4_low; // +3Ch
+ uint32_t IST4_high; // +40h
+ uint32_t IST5_low; // +44h
+ uint32_t IST5_high; // +48h
+ uint32_t IST6_low; // +4Ch
+ uint32_t IST6_high; // +50h
+ uint32_t IST7_low; // +54h
+ uint32_t IST7_high; // +58h
+ uint32_t reserved3; // +5Ch
+ uint32_t reserved4; // +60h
+ uint16_t reserved5; // +64h
+ uint16_t IO_MapBase; // +66h
+ } tss;
+
+ /** setting Interrupt Stack Table */
+ uint64_t IST_start = ISTVirtAddr + PageBytes;
+ tss.IST1_low = IST_start;
+ tss.IST1_high = IST_start >> 32;
+ tss.RSP0_low = tss.IST1_low;
+ tss.RSP0_high = tss.IST1_high;
+ tss.RSP1_low = tss.IST1_low;
+ tss.RSP1_high = tss.IST1_high;
+ tss.RSP2_low = tss.IST1_low;
+ tss.RSP2_high = tss.IST1_high;
+ physProxy.writeBlob(tssPhysAddr, &tss, sizeof(tss));
+
+ /* Setting IDT gates */
+ GateDescriptorLow PFGateLow = 0;
+ PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
+ PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
+ PFGateLow.selector = csLowPL;
+ PFGateLow.p = 1;
+ PFGateLow.dpl = 0;
+ PFGateLow.type = 0xe; // gate interrupt type
+ PFGateLow.IST = 0; // setting IST to 0 and using RSP0
+
+ GateDescriptorHigh PFGateHigh = 0;
+ PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
+
+ struct {
+ uint64_t low;
+ uint64_t high;
+ } PFGate = {PFGateLow, PFGateHigh};
+
+ physProxy.writeBlob(idtPhysAddr + 0xE0, &PFGate, sizeof(PFGate));
+
+ /* System call handler */
+ uint8_t syscallBlob[] = {
+ // mov %rax, (0xffffc90000007000)
+ 0x48, 0xa3, 0x00, 0x70, 0x00,
+ 0x00, 0x00, 0xc9, 0xff, 0xff,
+ // sysret
+ 0x48, 0x0f, 0x07
+ };
+
+ physProxy.writeBlob(syscallCodePhysAddr,
+ syscallBlob, sizeof(syscallBlob));
+
+ /** Page fault handler */
+ uint8_t faultBlob[] = {
+ // mov %rax, (0xffffc90000007000)
+ 0x48, 0xa3, 0x00, 0x70, 0x00,
+ 0x00, 0x00, 0xc9, 0xff, 0xff,
+ // add $0x8, %rsp # skip error
+ 0x48, 0x83, 0xc4, 0x08,
+ // iretq
+ 0x48, 0xcf
+ };
+
+ physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
+
+ /* Syscall handler */
+ pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
+ PageBytes, false);
+ /* GDT */
+ pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
+ /* IDT */
+ pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
+ /* TSS */
+ pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
+ /* IST */
+ pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
+ /* PF handler */
+ pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
+ /* MMIO region for m5ops */
+ pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
+ 16 * PageBytes, false);
}
void
diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..d8150a5 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -41,9 +41,6 @@
output = Param.String('cout', 'filename for stdout')
errout = Param.String('cerr', 'filename for stderr')
system = Param.System(Parent.any, "system process will run on")
- useArchPT = Param.Bool('false', 'maintain an in-memory version of the
page\
- table in an architecture-specific format')
- kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in
SE')
maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
uid = Param.Int(100, 'user id')
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 315f86b..bdfa858 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -113,8 +113,6 @@
Process::Process(const ProcessParams ¶ms, EmulationPageTable *pTable,
::Loader::ObjectFile *obj_file)
: SimObject(params), system(params.system),
- useArchPT(params.useArchPT),
- kvmInSE(params.kvmInSE),
useForClone(false),
pTable(pTable),
objFile(obj_file),
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 2234cb0..184f42f 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -164,10 +164,6 @@
Stats::Scalar numSyscalls; // track how many system calls are executed
- // flag for using architecture specific page table
- bool useArchPT;
- // running KVM requires special initialization
- bool kvmInSE;
// flag for using the process as a thread which shares page tables
bool useForClone;
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 79cd35a..ec99656 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1457,8 +1457,6 @@
pp->pid = temp_pid;
pp->ppid = (flags & OS::TGT_CLONE_THREAD) ? p->ppid() : p->pid();
- pp->useArchPT = p->useArchPT;
- pp->kvmInSE = p->kvmInSE;
Process *cp = pp->create();
// TODO: there is no way to know when the Process SimObject is done
with
// the params pointer. Both the params pointer (pp) and the process
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38487
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38b454f2a3ded71a033cb1da3ef5565d9c30a509
Gerrit-Change-Number: 38487
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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