Kaustav Goswami has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51614 )
Change subject: misc: Adding instructions on how to setup a multi-channel
memory.
......................................................................
misc: Adding instructions on how to setup a multi-channel memory.
This change adds a readme file that explains how a multi-channel
memory is setup and how it works in gem5,
Change-Id: Iec53a11f115a81b30a56c3faf754e2539bf03be6
---
A src/python/gem5/components/memory/ReadMe_MultiChannel_Memory.md
1 file changed, 185 insertions(+), 0 deletions(-)
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a/src/python/gem5/components/memory/ReadMe_MultiChannel_Memory.md
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+[](https://)
+
+# Simulating Multi Channel Memories in gem5
+
+The classic main memory simulator cannot simulate multi-channel main
memories.
+In this addition, we append the gem5 components library to
add "multi\_channel.py",
+which implements a multi-channel memory device.
+
+### Directory Structure
+
+```
+├── build_opts
+├── build_tools
+├── configs
+├── ext
+├── include
+├── site_scons
+├── src ─┐
+│ └─ python ─┐
+│ └─ gem5 ─┐
+│ └─ components ─┐
+│ └─ memory
+│ multi_channel.py
+├── system
+├── tests
+└── utils
+
+```
+### Code Description
+
+The addition to the code base is the file "multi\_channel.py". In this
+section, we describe the aforementioned file.
+
+ multi_channel.py:
+ Defines a class named MultiChannelMemory, which accepts 5
parameters:
+ (a) dram_interface_class:
+ The DRAM interface type to create with this memory controller.
+ Currently tested versions are:
+ DDR4_2400_8x8
+ (b) num_channels:
+ The number of channels that needs to be simulated.
+ (c) size:
+ Optionally define the size of the memory controller's address
+ space. By default, it starts at 0 and ends at the size of DRAM
+ device specified.
+ (d) addr_mapping:
+ Defines the address mapping scheme to be used. By default,
+ the mapping scheme is RoRaBaCoCh. Other supported mapping
+ schemes are:
+ RoRaBaChCo
+ RoCoRaBaCh
+ RoRaBaCoCh [default]
+ (e) interleaving_size:
+ Defines the interleaving size of the multi-channel memory
system.
+ By default, it is equal to the atom size, i.e., 64 (bytes).
+
+### Working Example
+
+In this section, we demonstrate how a given address is decoded into its
+respective channel (Ch), rank (Ra), bank (Ba), Row (Ro) and Column (Co),
+when the address mapping scheme is given. There are three mapping schemes
+currently supported by gem5: (a) RoCoRaBaCh, (b) RoRaBaCoCh, and,
+(c) RoRaBaChCo. We provide examples of each of these aforementioned mapping
+schemes. But before that, we need to understand the key variables/terms
that
+are used in this section.
+
+```
+─────────────────────────────────────────────────────────────────────────────
+We define a few key variables:
+ addr: A given address.
+ chan: addr's corresponding channel
+ rank: addr's corresponding rank
+ bank: addr's corresponding bank
+ row : addr's corresponding row
+ col : addr's corresponding col
+
+ intlv_size:
+ intlv_bits:
+
+ ranksPerChannel: the number of ranks per chan
+ banksPerRanks : the number of banks per rank
+ rowsPerBanks : the number of rows per bank
+
+ burstsPerRowBuffer:
+ burstsPerStripe :
+
+ higherOrderColumnBits:
+ lowerOrderColumnBits :
+
+ We determine intlv_bits = lg (intlv_size)
+ The row_buffer size for the memory system is given by:
+ row_buffer_size = device_rowbuffer_size * devices_per_rank
+
+ chan_bits: lg (chan)
+ rank_bits: lg (rank)
+ bank_bits: lg (bank)
+ row_bits : lg (row)
+ col_bits : lg (row_buffer_size)
+
+─────────────────────────────────────────────────────────────────────────────
+
+Now consider the following:
+ 1. Assume that the given address is 0x3940
+ 2. Binary Address (35): 0b00000000000000000000011100101000000
+ 3. The MSB of the intlv\_bits will give us chan
+ 4. The remaining bits of the intlv\_bits gives us the
+ lowerOrderColumnBits.
+ 5. Based on the mapping scheme, the bits for row (Ro), rank (Ra), and,
+ Bank (Ba) will be determined.
+ 6. The remaining bits signify the higherOrderColumnBits.
+ 7. Assume that we are simulating a multi-channel DRAM device
+ (DDR4_2400_8x8) with 2 channels, and, the total size of the DRAM
+ is 32 GiB (16 GiB) per channel. There are 2 ranks per channel.
+ Further, there are 16 banks per rank (4 banks per bank-group, and,
+ there are a total of 4 bank-groups). For a 32 GiB DDR4 2400 MHz
DRAM
+ device (8x8), there are 65536 rows per DRAM bank. This gives us the
+ following information:
+ chan_bits = lg (2) = 1
+ rank_bits = lg (2) = 1
+ bank_bits = lg (16) = 4
+ row_bits = lg (65536) = 16
+ 8. addr and its corresponding chan, rank, bank and row are given by:
+ (a) RoCoRaBaCh
+ chan: 1
+ rank: 1
+ bank: 0010
+ row : 0000000000000000
+ The lowerOrderColumnBits, i.e., 0000000 are interleaved.
+ The higherOrderColumnBits are 000010
+ Visual: 0b00000000000000000000011100101000000
+ └───────┬──────┴───┬───┼─┬──┼──┬──┘
+ │ │ │ │ │ │
+ │ │ │ │ │ └─
lowerOrderColumnBits
+ │ │ │ │ └──── chan
+ │ │ │ └─────── bank
+ │ │ └───────── rank
+ │ └─────────────
higherOrderColumnBits
+ └──────────────────────── row
+ (b) RoRaBaCoCh
+ chan: 1
+ rank: 0
+ bank: 0000
+ row : 0000000000000000
+ The lowerOrderColumnBits, i.e., 0000000 are interleaved.
+ The higherOrderColumnBits are 1110010
+ Visual: 0b00000000000000000000011100101000000
+ └───────┬───────┼──┬─┴───┬──┼──┬──┘
+ │ │ │ │ │ │
+ │ │ │ │ │ └─
lowerOrderColumnBits
+ │ │ │ │ └──── chan
+ │ │ │ └───────
higherOrderColumnBits
+ │ │ └───────────── bank
+ │ └──────────────── rank
+ └──────────────────────── row
+ (c) RoRaBaChCo
+ chan: 1
+ rank: 0
+ bank: 0000
+ row : 0000000000000000
+ The lowerOrderColumnBits and higherOrderColumnBits are merged
+ together in this case, represented by column.
+ Visual: 0b00000000000000000000011100101000000
+ └───────┬───────┼──┬─┼──────┬────┘
+ │ │ │ │ │
+ │ │ │ │ └──── column
+ │ │ │ │
+ │ │ │ └─────────── chan
+ │ │ └───────────── bank
+ │ └──────────────── rank
+ └──────────────────────── row
+
+─────────────────────────────────────────────────────────────────────────────
+```
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec53a11f115a81b30a56c3faf754e2539bf03be6
Gerrit-Change-Number: 51614
Gerrit-PatchSet: 1
Gerrit-Owner: Kaustav Goswami <kggosw...@ucdavis.edu>
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