Andreas Sandberg merged this change by Andreas Sandberg. ( https://gem5-review.googlesource.com/8365 )

Change subject: arch-arm: Add support for secure state in semihosting
......................................................................

arch-arm: Add support for secure state in semihosting

The semihosting component currently issues non-secure memory accesses
using the standard port proxy. This doesn't work when the guest is
running in secure state.

Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6
Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8365
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
2 files changed, 32 insertions(+), 11 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 98b50f4..89e1b2e 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -157,7 +157,7 @@
     }

     std::vector<uint64_t> argv(call->argc64 + 1);
-    PortProxy &proxy = tc->getPhysProxy();
+    PortProxy &proxy = physProxy(tc);
     ByteOrder endian = ArmISA::byteOrder(tc);

DPRINTF(Semihosting, "Semihosting call64: %s(0x%x)\n", call->name, param);
@@ -192,7 +192,7 @@
     }

     std::vector<uint64_t> argv(call->argc32 + 1);
-    PortProxy &proxy = tc->getPhysProxy();
+    PortProxy &proxy = physProxy(tc);
     ByteOrder endian = ArmISA::byteOrder(tc);

DPRINTF(Semihosting, "Semihosting call32: %s(0x%x)\n", call->name, param);
@@ -236,13 +236,30 @@
         files[i] = FileBase::create(*this, cp, csprintf("file%i", i));
 }

+PortProxy &
+ArmSemihosting::physProxy(ThreadContext *tc)
+{
+    if (ArmISA::inSecureState(tc)) {
+        if (!physProxyS) {
+            System *sys = tc->getSystemPtr();
+            physProxyS.reset(new SecurePortProxy(
+                                 sys->getSystemPort(),
+                                 sys->cacheLineSize()));
+        }
+        return *physProxyS;
+    } else {
+        return tc->getPhysProxy();
+    }
+}
+
+
 std::string
 ArmSemihosting::readString(ThreadContext *tc, Addr ptr, size_t len)
 {
     std::vector<char> buf(len + 1);

     buf[len] = '\0';
-    tc->getPhysProxy().readBlob(ptr, (uint8_t *)buf.data(), len);
+    physProxy(tc).readBlob(ptr, (uint8_t *)buf.data(), len);

     return std::string(buf.data());
 }
@@ -302,7 +319,7 @@
 ArmSemihosting::callWriteC(ThreadContext *tc, bool aarch64,
                            std::vector<uint64_t> &argv)
 {
-    const char c = tc->getPhysProxy().read<char>(argv[0]);
+    const char c = physProxy(tc).read<char>(argv[0]);

     DPRINTF(Semihosting, "Semihosting SYS_WRITEC('%c')\n", c);
     std::cout.put(c);
@@ -315,7 +332,7 @@
                            std::vector<uint64_t> &argv)
 {
     DPRINTF(Semihosting, "Semihosting SYS_WRITE0(...)\n");
-    PortProxy &proxy = tc->getPhysProxy();
+    PortProxy &proxy = physProxy(tc);
     for (Addr addr = (Addr)argv[0]; ; ++addr) {
         char data = proxy.read<char>(addr);
         if (data == 0)
@@ -335,7 +352,7 @@
         return RetErrno(argv[3], EBADF);

     std::vector<uint8_t> buffer(argv[3]);
-    tc->getPhysProxy().readBlob(argv[2], buffer.data(), buffer.size());
+    physProxy(tc).readBlob(argv[2], buffer.data(), buffer.size());

     int64_t ret = files[argv[1]]->write(buffer.data(), buffer.size());
     if (ret < 0) {
@@ -362,7 +379,7 @@
     } else {
         panic_if(ret > buffer.size(), "Read longer than buffer size.");

-        tc->getPhysProxy().writeBlob(argv[2], buffer.data(), ret);
+        physProxy(tc).writeBlob(argv[2], buffer.data(), ret);

         // Return the number of bytes not written
         return retOK(argv[3] - ret);
@@ -449,7 +466,7 @@
     if (path_len >= max_len)
         return retError(ENOSPC);

-    tc->getPhysProxy().writeBlob(
+    physProxy(tc).writeBlob(
         guest_buf, (const uint8_t *)path, path_len + 1);
     return retOK(0);
 }
@@ -519,7 +536,7 @@
                                std::vector<uint64_t> &argv)
 {
     if (cmdLine.size() + 1 < argv[2]) {
-        PortProxy &proxy = tc->getPhysProxy();
+        PortProxy &proxy = physProxy(tc);
         ByteOrder endian = ArmISA::byteOrder(tc);
         proxy.writeBlob(
             (Addr)argv[1],
@@ -576,7 +593,7 @@
            heap_base, heap_limit, stack_base, stack_limit);

     Addr base = argv[1];
-    PortProxy &proxy = tc->getPhysProxy();
+    PortProxy &proxy = physProxy(tc);
     ByteOrder endian = ArmISA::byteOrder(tc);
     if (aarch64) {
         proxy.writeHtoG<uint64_t>(base + 0 * 8, heap_base, endian);
@@ -631,7 +648,7 @@
 ArmSemihosting::callElapsed(ThreadContext *tc, bool aarch64,
                             std::vector<uint64_t> &argv)
 {
-    PortProxy &proxy = tc->getPhysProxy();
+    PortProxy &proxy = physProxy(tc);
     ByteOrder endian = ArmISA::byteOrder(tc);
     const uint64_t tick = semiTick(curTick());

diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index a4aa845..14c5f9d 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -48,6 +48,7 @@
 #include "sim/sim_object.hh"

 struct ArmSemihostingParams;
+class PortProxy;
 class SerialDevice;
 class ThreadContext;

@@ -253,8 +254,11 @@
         return tick >> tickShift;
     }
     void semiExit(uint64_t code, uint64_t subcode);
+    PortProxy &physProxy(ThreadContext *tc);
     std::string readString(ThreadContext *tc, Addr ptr, size_t len);

+    std::unique_ptr<PortProxy> physProxyS;
+
   private:
     typedef std::pair<uint64_t, SemiErrno> RetErrno;
     static constexpr RetErrno retError(SemiErrno e) {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6
Gerrit-Change-Number: 8365
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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