Change subject: cpu: check cpu ports status before connecting ...................................................................... cpu: check cpu ports status before connecting Connecting a ComMonitor between cpu port and L1 cache needs to assign this port to the monitor slave. This assignement has to be done before connecting cached ports. However, connecting cached ports does not check if cpu ports are already connected, which raises an error when it is true. This change fixes this assumption by checking the port status before the connection. Change-Id: I77b5b6ee7c8a8910f3f66103f2f6f4df3af2054b Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M src/cpu/BaseCPU.py 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 7b8a615..8bac998 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -12,6 +12,7 @@ # # Copyright (c) 2005-2008 The Regents of The University of Michigan # Copyright (c) 2011 Regents of the University of California +# Copyright (c) 2017 Centre National de la Recherche Scientifique # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -40,6 +41,7 @@ # Authors: Nathan Binkert # Rick Strong # Andreas Hansson +# Pierre-Yves Peneau import sys @@ -282,8 +284,11 @@ def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): self.icache = ic self.dcache = dc - self.icache_port = ic.cpu_side - self.dcache_port = dc.cpu_side + if not self.icache_port: + self.icache_port = ic.cpu_side + if not self.dcache_port: + self.dcache_port = dc.cpu_side + self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: -- To view, visit https://gem5-review.googlesource.com/2223 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I77b5b6ee7c8a8910f3f66103f2f6f4df3af2054b Gerrit-Change-Number: 2223 Gerrit-PatchSet: 2 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Pierre-Yves Péneau has uploaded this change for review. (
https://gem5-review.googlesource.com/2223