Hi Giacomo,
Thank you for the explanation, the base register is indeed SP here. I
will look into how your suggestion (intWidth per register) can be
implemented.
Arthur
On 12/1/21 11:58 AM, Giacomo Travaglini wrote:
Hi Arthur, this is a known issue in disassembling and arises when
Hi Arthur, this is a known issue in disassembling and arises when multiple
register operands have different width. For example your load is likely using
the 64-bit SP as base register and loading the value into 32-bit w1.
Gem5 is not capturing this per-operand-width and it is reporting a single
