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Review request for Default. Repository: gem5 Description ------- Changeset 11425:dd80771f73b0 --------------------------- ruby: add block_size_bits to the testAnd* functions The testAndRead, testAndReadMask, and testAndWrite require block_size_bits to know how to generate line addresses so we pass the block size through the parameter list. Diffs ----- src/mem/protocol/GPU_RfO-TCCdir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-TCP.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER-SQC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER-TCC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER-TCP.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER_Region-TCC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-SQC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-TCC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Three_Level-L0cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Three_Level-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Three_Level-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-L2cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_token-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_token-L2cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_token-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_token-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_hammer-cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_hammer-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_hammer-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/RubySlicc_Exports.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/RubySlicc_MemControl.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/ruby/slicc_interface/RubySlicc_Util.hh cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-probeFilter.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-L2cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MI_example-cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MI_example-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MI_example-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-CorePair.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-L3cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-Region-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-Region-msg.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca Diff: http://reviews.gem5.org/r/3423/diff/ Testing ------- Thanks, Brandon Potter _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
