changeset 0596db108c53 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0596db108c53
description:
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall
emulation.
The multiply, floating point, and atomic memory instructions will be
added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will
implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch
5
will add support for timing, minor, and detailed CPU models that is
missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that
had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are
sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <ja...@lowepower.com>
diffstat:
build_opts/RISCV | 3 +
ext/libelf/elf_common.h | 1 +
src/arch/riscv/RiscvISA.py | 50 ++++
src/arch/riscv/RiscvInterrupts.py | 39 +++
src/arch/riscv/RiscvSystem.py | 37 +++
src/arch/riscv/RiscvTLB.py | 41 +++
src/arch/riscv/SConscript | 72 ++++++
src/arch/riscv/SConsopts | 33 +++
src/arch/riscv/decoder.cc | 38 +++
src/arch/riscv/decoder.hh | 117 ++++++++++
src/arch/riscv/faults.cc | 84 +++++++
src/arch/riscv/faults.hh | 151 +++++++++++++
src/arch/riscv/idle_event.cc | 44 ++++
src/arch/riscv/idle_event.hh | 47 ++++
src/arch/riscv/interrupts.cc | 37 +++
src/arch/riscv/interrupts.hh | 106 +++++++++
src/arch/riscv/isa.cc | 233 +++++++++++++++++++++
src/arch/riscv/isa.hh | 119 ++++++++++
src/arch/riscv/isa/base.isa | 79 +++++++
src/arch/riscv/isa/bitfields.isa | 77 +++++++
src/arch/riscv/isa/decoder.isa | 332 ++++++++++++++++++++++++++++++
src/arch/riscv/isa/formats/basic.isa | 100 +++++++++
src/arch/riscv/isa/formats/formats.isa | 42 +++
src/arch/riscv/isa/formats/mem.isa | 355 ++++++++++++++++++++++++++++++++
src/arch/riscv/isa/formats/type.isa | 319 +++++++++++++++++++++++++++++
src/arch/riscv/isa/formats/unknown.isa | 80 +++++++
src/arch/riscv/isa/includes.isa | 90 ++++++++
src/arch/riscv/isa/main.isa | 63 +++++
src/arch/riscv/isa/operands.isa | 56 +++++
src/arch/riscv/isa_traits.hh | 74 ++++++
src/arch/riscv/kernel_stats.hh | 54 ++++
src/arch/riscv/linux/linux.cc | 37 +++
src/arch/riscv/linux/linux.hh | 199 ++++++++++++++++++
src/arch/riscv/linux/process.cc | 137 ++++++++++++
src/arch/riscv/linux/process.hh | 62 +++++
src/arch/riscv/locked_mem.hh | 77 +++++++
src/arch/riscv/microcode_rom.hh | 41 +++
src/arch/riscv/mmapped_ipr.hh | 50 ++++
src/arch/riscv/pagetable.cc | 79 +++++++
src/arch/riscv/pagetable.hh | 117 ++++++++++
src/arch/riscv/pra_constants.hh | 330 ++++++++++++++++++++++++++++++
src/arch/riscv/process.cc | 238 +++++++++++++++++++++
src/arch/riscv/process.hh | 66 ++++++
src/arch/riscv/pseudo_inst.hh | 45 ++++
src/arch/riscv/registers.hh | 181 ++++++++++++++++
src/arch/riscv/remote_gdb.cc | 71 ++++++
src/arch/riscv/remote_gdb.hh | 68 ++++++
src/arch/riscv/stacktrace.cc | 130 +++++++++++
src/arch/riscv/stacktrace.hh | 140 ++++++++++++
src/arch/riscv/system.cc | 76 ++++++
src/arch/riscv/system.hh | 94 ++++++++
src/arch/riscv/tlb.cc | 361 +++++++++++++++++++++++++++++++++
src/arch/riscv/tlb.hh | 133 ++++++++++++
src/arch/riscv/types.hh | 56 +++++
src/arch/riscv/utility.hh | 121 +++++++++++
src/arch/riscv/vtophys.hh | 65 +++++
src/base/loader/elf_object.cc | 2 +
src/base/loader/object_file.hh | 3 +-
src/cpu/BaseCPU.py | 14 +
src/sim/process.cc | 15 +
60 files changed, 5980 insertions(+), 1 deletions(-)
diffs (truncated from 6272 to 300 lines):
diff -r f15f02d8c79e -r 0596db108c53 build_opts/RISCV
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/build_opts/RISCV Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,3 @@
+TARGET_ISA = 'riscv'
+CPU_MODELS = 'AtomicSimpleCPU'
+PROTOCOL = 'MI_example'
diff -r f15f02d8c79e -r 0596db108c53 ext/libelf/elf_common.h
--- a/ext/libelf/elf_common.h Wed Nov 30 17:10:27 2016 -0500
+++ b/ext/libelf/elf_common.h Wed Nov 30 17:10:28 2016 -0500
@@ -173,6 +173,7 @@
#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices
x86-64 (compat) */
#define EM_AARCH64 183 /* AArch64 64 bit ARM. */
+#define EM_RISCV 243 /* Berkeley RISC-V */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */
diff -r f15f02d8c79e -r 0596db108c53 src/arch/riscv/RiscvISA.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/riscv/RiscvISA.py Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,50 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2014 Sven Karlsson
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+# Sven Karlsson
+# Alec Roelke
+
+from m5.SimObject import SimObject
+
+class RiscvISA(SimObject):
+ type = 'RiscvISA'
+ cxx_class = 'RiscvISA::ISA'
+ cxx_header = "arch/riscv/isa.hh"
diff -r f15f02d8c79e -r 0596db108c53 src/arch/riscv/RiscvInterrupts.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/riscv/RiscvInterrupts.py Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,39 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# Copyright (c) 2014 Sven Karlsson
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+# Sven Karlsson
+# Alec Roelke
+
+from m5.SimObject import SimObject
+
+class RiscvInterrupts(SimObject):
+ type = 'RiscvInterrupts'
+ cxx_class = 'RiscvISA::Interrupts'
+ cxx_header = 'arch/riscv/interrupts.hh'
diff -r f15f02d8c79e -r 0596db108c53 src/arch/riscv/RiscvSystem.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/riscv/RiscvSystem.py Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,37 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2016 RISC-V Foundation
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Alec Roelke
+
+from System import System
+
+class RiscvSystem(System):
+ type = 'RiscvSystem'
+ cxx_header = 'arch/riscv/system.hh'
+ load_addr_mask = 0xFFFFFFFFFFFFFFFF
diff -r f15f02d8c79e -r 0596db108c53 src/arch/riscv/RiscvTLB.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/riscv/RiscvTLB.py Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,41 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jaidev Patwardhan
+# Korey Sewell
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+from BaseTLB import BaseTLB
+
+class RiscvTLB(BaseTLB):
+ type = 'RiscvTLB'
+ cxx_class = 'RiscvISA::TLB'
+ cxx_header = 'arch/riscv/tlb.hh'
+ size = Param.Int(64, "TLB size")
diff -r f15f02d8c79e -r 0596db108c53 src/arch/riscv/SConscript
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/riscv/SConscript Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,72 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# Copyright (c) 2014 Sven Karlsson
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+# Sven Karlsson
+# Alec Roelke
+
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+ Source('decoder.cc')
+ Source('faults.cc')
+ Source('isa.cc')
+ Source('interrupts.cc')
+ Source('process.cc')
+ Source('pagetable.cc')
+ Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('tlb.cc')
+ Source('system.cc')
+
+ Source('linux/process.cc')
+ Source('linux/linux.cc')
+
+ SimObject('RiscvInterrupts.py')
+ SimObject('RiscvISA.py')
+ SimObject('RiscvTLB.py')
+ SimObject('RiscvSystem.py')
+
+ DebugFlag('RiscvMisc')
+ DebugFlag('RiscvTLB')
+
+ # Add in files generated by the ISA description.
+ env.ISADesc('isa/main.isa')
diff -r f15f02d8c79e -r 0596db108c53 src/arch/riscv/SConsopts
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/riscv/SConsopts Wed Nov 30 17:10:28 2016 -0500
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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