changeset b29aca3fcb75 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b29aca3fcb75
description:
        kvm: Adding details to kvm page fault in x86
        Adding details, e.g. rip, rsp etc. to the kvm pagefault exit when in SE 
mode.

diffstat:

 src/arch/x86/pseudo_inst.cc |  21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diffs (40 lines):

diff -r 370d69b00fcf -r b29aca3fcb75 src/arch/x86/pseudo_inst.cc
--- a/src/arch/x86/pseudo_inst.cc       Tue Oct 04 13:04:19 2016 -0400
+++ b/src/arch/x86/pseudo_inst.cc       Tue Oct 04 13:06:05 2016 -0400
@@ -29,8 +29,10 @@
  */
 
 #include "arch/x86/pseudo_inst.hh"
+#include "arch/x86/system.hh"
 #include "debug/PseudoInst.hh"
 #include "sim/process.hh"
+#include "sim/system.hh"
 
 using namespace X86ISA;
 
@@ -62,8 +64,23 @@
 
     Process *p = tc->getProcessPtr();
     if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
-        panic("Page fault at %#x ", tc->readMiscReg(MISCREG_CR2));
-    }
+        SETranslatingPortProxy proxy = tc->getMemProxy();
+        // at this point we should have 6 values on the interrupt stack
+        int size = 6;
+        uint64_t is[size];
+        // reading the interrupt handler stack
+        proxy.readBlob(ISTVirtAddr + PageBytes - size*sizeof(uint64_t),
+                       (uint8_t *)&is, sizeof(is));
+        panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
+                "\tss: %#x\n"
+                "\trsp: %#x\n"
+                "\trflags: %#x\n"
+                "\tcs: %#x\n"
+                "\trip: %#x\n"
+                "\terr_code: %#x\n",
+                tc->readMiscReg(MISCREG_CR2),
+                is[5], is[4], is[3], is[2], is[1], is[0]);
+   }
 }
 
 } // namespace X86ISA
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