changeset df24b9af42c7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=df24b9af42c7
description:
misc: Fix issues flagged by gcc 6
A few warnings (and thus errors) pop up after being added to -Wall:
1. -Wmisleading-indentation
In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.
2. -Wshift-negative-value
gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.
That is all. Porting done.
diffstat:
src/arch/arm/isa/insts/neon.isa | 15 +++++++++------
src/mem/ruby/system/DMASequencer.cc | 2 +-
2 files changed, 10 insertions(+), 7 deletions(-)
diffs (54 lines):
diff -r b31738224fb0 -r df24b9af42c7 src/arch/arm/isa/insts/neon.isa
--- a/src/arch/arm/isa/insts/neon.isa Tue Apr 12 05:28:39 2016 -0400
+++ b/src/arch/arm/isa/insts/neon.isa Wed Apr 13 12:13:44 2016 -0400
@@ -2939,29 +2939,32 @@
twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4,
vrsraCode, True)
vsriCode = '''
- if (imm >= sizeof(Element) * 8)
+ if (imm >= sizeof(Element) * 8) {
destElem = destElem;
- else
+ } else {
destElem = (srcElem1 >> imm) |
(destElem & ~mask(sizeof(Element) * 8 - imm));
+ }
'''
twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2,
vsriCode, True)
twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4,
vsriCode, True)
vshlCode = '''
- if (imm >= sizeof(Element) * 8)
+ if (imm >= sizeof(Element) * 8) {
destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1;
- else
+ } else {
destElem = srcElem1 << imm;
+ }
'''
twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2,
vshlCode)
twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4,
vshlCode)
vsliCode = '''
- if (imm >= sizeof(Element) * 8)
+ if (imm >= sizeof(Element) * 8) {
destElem = destElem;
- else
+ } else {
destElem = (srcElem1 << imm) | (destElem & mask(imm));
+ }
'''
twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2,
vsliCode, True)
twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4,
vsliCode, True)
diff -r b31738224fb0 -r df24b9af42c7 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc Tue Apr 12 05:28:39 2016 -0400
+++ b/src/mem/ruby/system/DMASequencer.cc Wed Apr 13 12:13:44 2016 -0400
@@ -45,7 +45,7 @@
{
RubyPort::init();
m_is_busy = false;
- m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
+ m_data_block_mask = mask(RubySystem::getBlockSizeBits());
for (const auto &s_port : slave_ports)
s_port->sendRangeChange();
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