changeset d2ab6d889fc7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d2ab6d889fc7
description:
ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that
replace
Time with Cycles.This patch further replaces Time with Cycles in
Sequencer,
Profiler, different protocols and related entities.
Though Time has not been completely removed, the places where it is in
use
seem benign as of now.
diffstat:
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 6 +-
src/mem/protocol/MOESI_hammer-cache.sm | 12 ++++--
src/mem/protocol/MOESI_hammer-dir.sm | 2 +-
src/mem/protocol/MOESI_hammer-msg.sm | 14 +++++--
src/mem/protocol/RubySlicc_Exports.sm | 3 +-
src/mem/protocol/RubySlicc_Profiler.sm | 2 +-
src/mem/protocol/RubySlicc_Types.sm | 10 +++-
src/mem/protocol/RubySlicc_Util.sm | 7 +---
src/mem/ruby/common/TypeDefines.hh | 1 -
src/mem/ruby/profiler/Profiler.cc | 30 +++++++-------
src/mem/ruby/profiler/Profiler.hh | 32 +++++----------
src/mem/ruby/slicc_interface/AbstractController.cc | 2 +-
src/mem/ruby/slicc_interface/AbstractController.hh | 2 +-
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 34 +----------------
src/mem/ruby/structures/Prefetcher.cc | 2 +-
src/mem/ruby/system/Sequencer.cc | 34 ++++++++--------
src/mem/ruby/system/Sequencer.hh | 44 +++++++++++-----------
src/mem/ruby/system/TBETable.hh | 3 -
src/mem/ruby/system/TimerTable.cc | 2 +-
src/mem/ruby/system/TimerTable.hh | 2 +-
src/mem/slicc/ast/InfixOperatorExprAST.py | 1 -
21 files changed, 103 insertions(+), 142 deletions(-)
diffs (truncated from 649 to 300 lines):
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Feb 10 21:43:09
2013 -0600
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Feb 10 21:43:10
2013 -0600
@@ -153,7 +153,7 @@
bool IsAtomic, default="false", desc="Request was an atomic request";
AccessType AccessType, desc="Type of request (used for
profiling)";
- Time IssueTime, desc="Time the request was issued";
+ Cycles IssueTime, desc="Time the request was issued";
RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
@@ -183,7 +183,7 @@
void unset_tbe();
void wakeUpAllBuffers();
void wakeUpBuffers(Address a);
- Time curCycle();
+ Cycles curCycle();
TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
@@ -1452,7 +1452,7 @@
// Update average latency
if (tbe.IssueCount <= 1) {
if (tbe.ExternalResponse == true) {
- updateAverageLatencyEstimate(TimeToCycles(curCycle() - tbe.IssueTime));
+ updateAverageLatencyEstimate(curCycle() - tbe.IssueTime);
}
}
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Sun Feb 10 21:43:10 2013 -0600
@@ -161,9 +161,13 @@
bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the
pending msg count reflect the silent acks";
MachineID LastResponder, desc="last machine to send a response for this
request";
MachineID CurOwner, desc="current owner of the block, used for
UnblockS responses";
- Time InitialRequestTime, default="0", desc="time the initial requests was
sent from the L1Cache";
- Time ForwardRequestTime, default="0", desc="time the dir forwarded the
request";
- Time FirstResponseTime, default="0", desc="the time the first response was
received";
+
+ Cycles InitialRequestTime, default="Cycles(0)",
+ desc="time the initial requests was sent from the L1Cache";
+ Cycles ForwardRequestTime, default="Cycles(0)",
+ desc="time the dir forwarded the request";
+ Cycles FirstResponseTime, default="Cycles(0)",
+ desc="the time the first response was received";
}
structure(TBETable, external="yes") {
@@ -181,7 +185,7 @@
void unset_tbe();
void wakeUpAllBuffers();
void wakeUpBuffers(Address a);
- Time curCycle();
+ Cycles curCycle();
Entry getCacheEntry(Address address), return_by_pointer="yes" {
Entry L2cache_entry := static_cast(Entry, "pointer",
L2cacheMemory.lookup(address));
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/MOESI_hammer-dir.sm Sun Feb 10 21:43:10 2013 -0600
@@ -179,7 +179,7 @@
void set_tbe(TBE a);
void unset_tbe();
void wakeUpBuffers(Address a);
- Time curCycle();
+ Cycles curCycle();
// ** OBJECTS **
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/MOESI_hammer-msg.sm
--- a/src/mem/protocol/MOESI_hammer-msg.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/MOESI_hammer-msg.sm Sun Feb 10 21:43:10 2013 -0600
@@ -94,8 +94,11 @@
NetDest Destination, desc="Multicast destination mask";
MessageSizeType MessageSize, desc="size category of the message";
bool DirectedProbe, default="false", desc="probe filter directed probe";
- Time InitialRequestTime, default="0", desc="time the initial requests was
sent from the L1Cache";
- Time ForwardRequestTime, default="0", desc="time the dir forwarded the
request";
+
+ Cycles InitialRequestTime, default="Cycles(0)",
+ desc="time the initial requests was sent from the L1Cache";
+ Cycles ForwardRequestTime, default="Cycles(0)",
+ desc="time the dir forwarded the request";
int SilentAcks, default="0", desc="silent acks from the full-bit directory";
bool functionalRead(Packet *pkt) {
@@ -120,8 +123,11 @@
bool Dirty, desc="Is the data dirty (different than
memory)?";
int Acks, default="0", desc="How many messages this counts as";
MessageSizeType MessageSize, desc="size category of the message";
- Time InitialRequestTime, default="0", desc="time the initial requests was
sent from the L1Cache";
- Time ForwardRequestTime, default="0", desc="time the dir forwarded the
request";
+
+ Cycles InitialRequestTime, default="Cycles(0)",
+ desc="time the initial requests was sent from the L1Cache";
+ Cycles ForwardRequestTime, default="Cycles(0)",
+ desc="time the dir forwarded the request";
int SilentAcks, default="0", desc="silent acks from the full-bit directory";
bool functionalRead(Packet *pkt) {
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Exports.sm Sun Feb 10 21:43:10 2013 -0600
@@ -33,11 +33,10 @@
external_type(std::string, primitive="yes");
external_type(uint32_t, primitive="yes");
external_type(uint64, primitive="yes");
-external_type(Time, primitive="yes", default="0");
external_type(PacketPtr, primitive="yes");
external_type(Packet, primitive="yes");
external_type(Address);
-external_type(Cycles, primitive="yes");
+external_type(Cycles, primitive="yes", default="Cycles(0)");
structure(DataBlock, external = "yes", desc="..."){
void clear();
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/RubySlicc_Profiler.sm
--- a/src/mem/protocol/RubySlicc_Profiler.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Profiler.sm Sun Feb 10 21:43:10 2013 -0600
@@ -47,4 +47,4 @@
void profile_average_latency_estimate(int latency);
// profile the total message delay of a message across a virtual network
-void profileMsgDelay(int virtualNetwork, Time delayCycles);
+void profileMsgDelay(int virtualNetwork, Cycles delayCycles);
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Types.sm Sun Feb 10 21:43:10 2013 -0600
@@ -41,7 +41,7 @@
structure(InPort, external = "yes", primitive="yes") {
bool isReady();
void dequeue();
- Time dequeue_getDelayCycles();
+ Cycles dequeue_getDelayCycles();
void recycle();
bool isEmpty();
}
@@ -97,10 +97,14 @@
structure (Sequencer, external = "yes") {
void readCallback(Address, DataBlock);
void readCallback(Address, GenericMachineType, DataBlock);
- void readCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
+ void readCallback(Address, GenericMachineType, DataBlock,
+ Cycles, Cycles, Cycles);
+
void writeCallback(Address, DataBlock);
void writeCallback(Address, GenericMachineType, DataBlock);
- void writeCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
+ void writeCallback(Address, GenericMachineType, DataBlock,
+ Cycles, Cycles, Cycles);
+
void checkCoherence(Address);
void profileNack(Address, int, int, uint64);
void evictionCallback(Address);
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/protocol/RubySlicc_Util.sm
--- a/src/mem/protocol/RubySlicc_Util.sm Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/protocol/RubySlicc_Util.sm Sun Feb 10 21:43:10 2013 -0600
@@ -32,14 +32,9 @@
void error(std::string msg);
void assert(bool condition);
int random(int number);
-Time zero_time();
-Cycles TimeToCycles(Time t);
+Cycles zero_time();
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
-int time_to_int(Time time);
-Time getTimeModInt(Time time, int modulus);
-Time getTimePlusInt(Time addend1, int addend2);
-Time getTimeMinusTime(Time t1, Time t2);
void procProfileCoherenceRequest(NodeID node, bool needCLB);
void dirProfileCoherenceRequest(NodeID node, bool needCLB);
int max_tokens();
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/ruby/common/TypeDefines.hh
--- a/src/mem/ruby/common/TypeDefines.hh Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/ruby/common/TypeDefines.hh Sun Feb 10 21:43:10 2013 -0600
@@ -31,7 +31,6 @@
#define TYPEDEFINES_H
typedef unsigned long long uint64;
-
typedef long long int64;
typedef int64 Time;
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/ruby/profiler/Profiler.cc
--- a/src/mem/ruby/profiler/Profiler.cc Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/ruby/profiler/Profiler.cc Sun Feb 10 21:43:10 2013 -0600
@@ -270,7 +270,7 @@
double minutes = seconds / 60.0;
double hours = minutes / 60.0;
double days = hours / 24.0;
- Time ruby_cycles = g_system_ptr->getTime()-m_ruby_start;
+ Cycles ruby_cycles = g_system_ptr->getTime()-m_ruby_start;
if (!short_stats) {
out << "Elapsed_time_in_seconds: " << seconds << endl;
@@ -609,7 +609,7 @@
}
void
-Profiler::profilePFWait(Time waitTime)
+Profiler::profilePFWait(Cycles waitTime)
{
m_prefetchWaitHistogram.add(waitTime);
}
@@ -622,7 +622,7 @@
// non-zero cycle demand request
void
-Profiler::missLatency(Time cycles,
+Profiler::missLatency(Cycles cycles,
RubyRequestType type,
const GenericMachineType respondingMach)
{
@@ -633,11 +633,11 @@
}
void
-Profiler::missLatencyWcc(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime)
+Profiler::missLatencyWcc(Cycles issuedTime,
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime,
+ Cycles completionTime)
{
if ((issuedTime <= initialRequestTime) &&
(initialRequestTime <= forwardRequestTime) &&
@@ -659,11 +659,11 @@
}
void
-Profiler::missLatencyDir(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime)
+Profiler::missLatencyDir(Cycles issuedTime,
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime,
+ Cycles completionTime)
{
if ((issuedTime <= initialRequestTime) &&
(initialRequestTime <= forwardRequestTime) &&
@@ -686,13 +686,13 @@
// non-zero cycle prefetch request
void
-Profiler::swPrefetchLatency(Time cycles,
- RubyRequestType type,
+Profiler::swPrefetchLatency(Cycles cycles, RubyRequestType type,
const GenericMachineType respondingMach)
{
m_allSWPrefetchLatencyHistogram.add(cycles);
m_SWPrefetchLatencyHistograms[type].add(cycles);
m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles);
+
if (respondingMach == GenericMachineType_Directory ||
respondingMach == GenericMachineType_NUM) {
m_SWPrefetchL2MissLatencyHistogram.add(cycles);
diff -r f5335ac67f41 -r d2ab6d889fc7 src/mem/ruby/profiler/Profiler.hh
--- a/src/mem/ruby/profiler/Profiler.hh Sun Feb 10 21:43:09 2013 -0600
+++ b/src/mem/ruby/profiler/Profiler.hh Sun Feb 10 21:43:10 2013 -0600
@@ -125,29 +125,23 @@
void startTransaction(int cpu);
void endTransaction(int cpu);
- void profilePFWait(Time waitTime);
+ void profilePFWait(Cycles waitTime);
void controllerBusy(MachineID machID);
void bankBusy();
- void missLatency(Time t,
- RubyRequestType type,
+ void missLatency(Cycles t, RubyRequestType type,
const GenericMachineType respondingMach);
- void missLatencyWcc(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime);
+ void missLatencyWcc(Cycles issuedTime, Cycles initialRequestTime,
+ Cycles forwardRequestTime, Cycles firstResponseTime,
+ Cycles completionTime);
- void missLatencyDir(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime);
+ void missLatencyDir(Cycles issuedTime, Cycles initialRequestTime,
+ Cycles forwardRequestTime, Cycles firstResponseTime,
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