[gem5-dev] fxsave and fxrstor assume 64 bit mode
I just noticed that the fxsave and fxrstor implementations Andreas did (going by the copyright header in the file) incorrectly assume that the CPU is in 64 bit mode and save XMM8-15 unconditionally. I'll likely put together a patch to fix that, but I wanted to mention it here so it didn't slip into the ether. Also that cprintf unit test never got fixed... Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2611: cpu: Tidy up the MemTest and make false sharing more obvious
Hi Nilay, I think the “DMA” bit of this tester was broken and rather pointless. In essence the MemTest is only fit for testing false sharing, and that is what it now does. I do not quite understand what a DMA has to do with any of that. Separately we will now have a tester that actually tests actual sharing, and does so using larger chunks of data being touched (in units of whole cache lines). I think this is a much more sensible strategy. What is the value of the “DMA” bit in MemTest and why does it make sense to keep it there? Andreas On 31/01/2015 15:03, Nilay Vaish ni...@cs.wisc.edu wrote: On Sat, 31 Jan 2015, Andreas Hansson wrote: On Jan. 30, 2015, 9:47 p.m., Nilay Vaish wrote: src/cpu/testers/memtest/MemTest.py, line 55 http://reviews.gem5.org/r/2611/diff/1/?file=43345#file43345line55 Are you sure this should be dropped? I think the coherence protocols that provide a dma controller need this for testing. All regressions work just fine (with stats updates). I am about to post a separate test script that actually shares data (not just false sharing), doing so based on the TrafficGen and MemChecker. Regressions are working probably because we are not testing the DMA controller. I would suggest that we retain the variable. I would change the regressions to test the DMA controller as well. -- Nilay -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all
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