[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: FAILED! *

[gem5-dev] Change in public/gem5[master]: mem-ruby: Remove function that maps responses to a DMA engine

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7162 ) Change subject: mem-ruby: Remove function that maps responses to a DMA engine .. mem-ruby: Remove function that

[gem5-dev] Change in public/gem5[master]: cpu: Make the CPU's TLB parameter a BaseTLB.

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7349 ) Change subject: cpu: Make the CPU's TLB parameter a BaseTLB. .. cpu: Make the CPU's TLB parameter a BaseTLB. This is

[gem5-dev] Change in public/gem5[master]: arm, power: Make the python TLB simobjects inherit from BaseTLB.

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7348 ) Change subject: arm, power: Make the python TLB simobjects inherit from BaseTLB. .. arm, power: Make the python TLB

[gem5-dev] Change in public/gem5[master]: mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7163 ) Change subject: mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol .. mem-ruby: Fix wakeup timeouts for

[gem5-dev] Change in public/gem5[master]: mem-ruby: Add support for multiple DMA engines in MESI_Two_Level

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7161 ) Change subject: mem-ruby: Add support for multiple DMA engines in MESI_Two_Level .. mem-ruby: Add support for

[gem5-dev] RISC-V FS support and custom instructions

Hi all, I have a student who is interested in extending the RISC-V support in gem5 as part of his Master's thesis. The focus would be to enable FS support (at least for bare-metal applications, not necessarily for Linux) and to define an interface for the addition of user defined custom

[gem5-dev] Change in public/gem5[master]: arch-riscv: Don't crash when printing unknown CSRs

Alec Roelke has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/7321 ) Change subject: arch-riscv: Don't crash when printing unknown CSRs .. arch-riscv: Don't crash when printing unknown CSRs This patch

[gem5-dev] Change in public/gem5[master]: util/m5: add Android.mk

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7363 ) Change subject: util/m5: add Android.mk .. util/m5: add Android.mk Add Android.mk so we can build m5 tool in Android tree.

Re: [gem5-dev] closing the loop on the kvm patches

Hi Gabe, I have tested the KVM patches which enable KVM on Intel machines, on an AMD machine in SE mode. It seems they are not breaking KVM for AMD machines. I can review and test on AMD machine both of them as you are updating them. https://gem5-review.googlesource.com/7041

[gem5-dev] Change in public/gem5[master]: kvm, x86: fix the KVM CPU for both Intel and AMD

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/7361 Change subject: kvm,x86: fix the KVM CPU for both Intel and AMD .. kvm,x86: fix the KVM CPU for both Intel and AMD This patch makes

[gem5-dev] Change in public/gem5[master]: kvm: Some various changes to make KVM work

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/7362 Change subject: kvm: Some various changes to make KVM work .. kvm: Some various changes to make KVM work I really have no idea

[gem5-dev] Change in public/gem5[master]: arch-riscv: Don't crash when printing unknown CSRs

Alec Roelke has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7321 ) Change subject: arch-riscv: Don't crash when printing unknown CSRs .. arch-riscv: Don't crash when printing unknown CSRs

Re: [gem5-dev] RISC-V FS support and custom instructions

Hi Christian, I'm getting started implementing FS mode for RISC-V, but I haven't gotten very far yet. So far, I've determined that it comes down to two things in general: support for RISC-V's privileged architecture, and a compatible Linux kernel and disk image. Since you only need to run

[gem5-dev] Change in public/gem5[master]: sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/7364 ) Change subject: sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). .. sim: Allow passing a

[gem5-dev] Change in public/gem5[master]: sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/7364 Change subject: sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). .. sim: Allow passing a user-defined