[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Add a setThreadContext method to the ISA class.

2020-05-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29233 )



Change subject: arch,cpu: Add a setThreadContext method to the ISA class.
..

arch,cpu: Add a setThreadContext method to the ISA class.

Also remove ThreadContext pointer parameters to some of the methods in
the ISA classes.

Change-Id: I8e502b1857d299cb2e759a9734a1df4f65f31efe
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/power/isa.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/ua2005.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/cpu/SConscript
M src/cpu/base.cc
D src/cpu/cpuevent.cc
D src/cpu/cpuevent.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/cpu.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
26 files changed, 243 insertions(+), 597 deletions(-)



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index 70e5fb9..95aa090 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1169,7 +1169,7 @@
 ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
 {
 auto *isa = static_cast(tc->getIsaPtr());
-return isa->getCurSveVecLenInBits(tc);
+return isa->getCurSveVecLenInBits();
 }

 }
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b18bbb0..03a7cf1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -120,19 +120,16 @@
 }

 void
-ISA::clear(ThreadContext *tc)
-{
-clear();
-// Invalidate cached copies of miscregs in the TLBs
-getITBPtr(tc)->invalidateMiscReg();
-getDTBPtr(tc)->invalidateMiscReg();
-}
-
-void
 ISA::clear()
 {
 const Params *p(params());

+// Invalidate cached copies of miscregs in the TLBs
+if (tc) {
+getITBPtr(tc)->invalidateMiscReg();
+getDTBPtr(tc)->invalidateMiscReg();
+}
+
 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
 memset(miscRegs, 0, sizeof(miscRegs));

@@ -421,31 +418,40 @@
 }

 void
-ISA::startup(ThreadContext *tc)
+ISA::startup()
 {
-pmu->setThreadContext(tc);
+BaseISA::startup();

-if (system) {
-Gicv3 *gicv3 = dynamic_cast(system->getGIC());
-if (gicv3) {
- 
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));

-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(tc);
-}
-}
+if (tc)
+setupThreadContext();

 afterStartup = true;
 }

 void
+ISA::setupThreadContext()
+{
+pmu->setThreadContext(tc);
+
+if (!system)
+return;
+
+Gicv3 *gicv3 = dynamic_cast(system->getGIC());
+if (!gicv3)
+return;
+
+if (!gicv3CpuInterface)
+gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+gicv3CpuInterface->setISA(this);
+gicv3CpuInterface->setThreadContext(tc);
+}
+
+void
 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
 {
-pmu->setThreadContext(new_tc);
-
-if (system && gicv3CpuInterface) {
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(new_tc);
-}
+tc = new_tc;
+setupThreadContext();
 }

 RegVal
@@ -473,7 +479,7 @@


 RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+ISA::readMiscReg(int misc_reg)
 {
 CPSR cpsr = 0;
 PCState pc = 0;
@@ -760,12 +766,12 @@
   // Generic Timer registers
   case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
-return getGenericTimer(tc).readMiscReg(misc_reg);
+return getGenericTimer().readMiscReg(misc_reg);

   case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
   case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
   case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
-return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
+return getGICv3CPUInterface().readMiscReg(misc_reg);

   default:
 break;
@@ -797,7 +803,7 @@
 }

 void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val)
 {

 RegVal newVal = val;
@@ -827,7 +833,7 @@
 pc.nextJazelle(cpsr.j);
 pc.illegalExec(cpsr.il == 1);

-tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) -  
1);

+tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);

 // Follow slightly different semantics if a CheckerCPU object
 // is connected
@@ -1132,8 +1138,8 @@
   // TLB Invalidate All
   case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
 {
-assert32(tc);
-scr = readMiscReg(MISCREG_SCR, tc);
+assert32();

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using acquire/release memory flags

2020-05-18 Thread Gerrit
Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27133 )


Change subject: arch-arm: Using acquire/release memory flags
..

arch-arm: Using acquire/release memory flags

Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27133
Tested-by: kokoro 
Maintainer: Giacomo Travaglini 
Reviewed-by: Anthony Gutierrez 
---
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
4 files changed, 12 insertions(+), 4 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index dc1d650..d828fcf 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2019 ARM Limited
+// Copyright (c) 2010-2011,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 # Disambiguate the class name for different flavors of loads
 if self.flavor != "normal":
@@ -256,6 +257,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 def emit(self):
 # Address computation code
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 4f12509..fc4f34f 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")
+
 if self.flavor in ("acex", "exclusive", "exp", "acexp"):
 self.memFlags.append("Request::LLSC")

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f542478..e99f6ad 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2017,2019 ARM Limited
+// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
@@ -271,6 +272,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str64.isa  
b/src/arch/arm/isa/insts/str64.isa

index 22d1456..7ad1cad 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013,2017,2019 ARM Limited
+// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")
+
 if self.flavor in ("relex", "exclusive", "exp", "relexp"):
 self.instFlags.append("IsStoreConditional")
 self.memFlags.append("Request::LLSC")

--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: fix store-release issuing

2020-05-18 Thread Gerrit
Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27135 )


Change subject: cpu-minor: fix store-release issuing
..

cpu-minor: fix store-release issuing

Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.

Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27135
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

---
M src/cpu/minor/lsq.cc
1 file changed, 12 insertions(+), 2 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e50d498..e4a9dc0 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014,2017-2018 ARM Limited
+ * Copyright (c) 2013-2014,2017-2018,2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1029,10 +1029,11 @@

 bool is_load = request->isLoad;
 bool is_llsc = request->request->isLLSC();
+bool is_release = request->request->isRelease();
 bool is_swap = request->request->isSwap();
 bool is_atomic = request->request->isAtomic();
 bool bufferable = !(request->request->isStrictlyOrdered() ||
-is_llsc || is_swap || is_atomic);
+is_llsc || is_swap || is_atomic || is_release);

 if (is_load) {
 if (numStoresInTransfers != 0) {
@@ -1050,6 +1051,15 @@
 }
 }

+// Process store conditionals or store release after all previous
+// stores are completed
+if (((!is_load && is_llsc) || is_release) &&
+!storeBuffer.isDrained()) {
+DPRINTF(MinorMem, "Memory access needs to wait for store buffer"
+  " to drain\n");
+return;
+}
+
 /* Check if this is the head instruction (and so must be executable as
  *  its stream sequence number was checked above) for loads which must
  *  not be speculatively issued and stores which must be issued here */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Gerrit-Change-Number: 27135
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix store-release issuing

2020-05-18 Thread Gerrit
Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27134 )


Change subject: cpu-o3: fix store-release issuing
..

cpu-o3: fix store-release issuing

Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 16 insertions(+), 1 deletion(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f7fb3fe..7383c6f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,6 +1,6 @@

 /*
- * Copyright (c) 2010-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2017-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -753,6 +753,21 @@

 DynInstPtr inst = storeWBIt->instruction();
 LSQRequest* req = storeWBIt->request();
+
+// Process store conditionals or store release after all previous
+// stores are completed
+if ((req->mainRequest()->isLLSC() ||
+ req->mainRequest()->isRelease()) &&
+ (storeWBIt.idx() != storeQueue.head())) {
+DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
+"[sn:%lli] is %s%s and not head of the queue\n",
+storeWBIt.idx(), inst->pcState(),
+req->request()->getPaddr(), inst->seqNum,
+req->mainRequest()->isLLSC() ? "SC" : "",
+req->mainRequest()->isRelease() ? "/Release" : "");
+break;
+}
+
 storeWBIt->committed() = true;

 assert(!inst->memData);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Gerrit-Change-Number: 27134
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: GCN3 Integration

2020-05-18 Thread Daniel Gerzhoy via gem5-dev
Cool! Thanks for the update. Looking forward to the talk.

On Mon, May 18, 2020 at 2:57 PM Poremba, Matthew 
wrote:

> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Daniel,
>
>
> We're in the process of merging it into develop. It should be in gem5
> 20.1. There are a few CLs that need reviews first. Tony and I will be
> giving a talk during the gem5 workshop in 2 weeks.
>
>
> -Matt
>
> -Original Message-
> From: Daniel Gerzhoy via gem5-dev 
> Sent: Monday, May 18, 2020 10:39 AM
> To: gem5 Developer List 
> Cc: Daniel Gerzhoy 
> Subject: [gem5-dev] GCN3 Integration
>
> [CAUTION: External Email]
>
> Hello,
>
> I'm wondering if anyone could give an update on the status of integrating
> the gcn3-staging branch into the main branch?
> (From here:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgem5.googlesource.com%2Famd%2Fgem5data=02%7C01%7Cmatthew.poremba%40amd.com%7Cffbf0f89a0d14ae8a43108d7fb52755e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637254203890939524sdata=hJNYBWzfoQuLtL2TG3m3AtabLX7wJx3OHE1y6wkDhNo%3Dreserved=0
>branch: agutierr/master-gcn3-staging)
>
> I saw some emails on this list about it, so I thought I might update to
> the main branch but just from looking into the apu_se.py in the
> develop/19.0 release/20.0 rc I don't see any mention of GPU_VIPER, and a
> couple of other things like the ROCm environment paths that the
> gcn3-staging branch has.
>
> Just hoping to eventually use the main branch if possible.
>
> Cheers and thanks for all the hard work  (and stay safe),
>
> Dan Gerzhoy
> University of Maryland at College Park
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[gem5-dev] Change in gem5/gem5[develop]: scons: Fix how partial linking is disabled.

2020-05-18 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29303 )



Change subject: scons: Fix how partial linking is disabled.
..

scons: Fix how partial linking is disabled.

Setting disable_partial part way through the checks for various build
targets is incorrect and will affect targets based on the order they're
checked.

This change moves the check earlier, makes it consistent across all
builds whether fast is included or not, and stops passing it in as an
option to makeEnv since it now applies universally.

By disabling partial linking consistently, we avoid missing bugs where
only the "fast" version of gem5 doesn't build correctly because of the
multitude of g++ bugs having to do with combining LTO and partial
linking.

This also simplifies the logic in the SConscript by having fewer
independently moving parts.

Change-Id: Iff69f39868e948d3b9a5b11ea80bbfed19419b59
---
M src/SConscript
1 file changed, 17 insertions(+), 23 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 134e2a5..ce732fd 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1211,11 +1211,22 @@

 gem5_binary = Gem5('gem5')

+# Disable partial linking if mixing it with LTO is broken and LTO is  
enabled.

+disable_partial = (env.get('BROKEN_INCREMENTAL_LTO', False) and
+   GetOption('force_lto'))
+if env['PLATFORM'] == 'darwin':
+# Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial
+# linked objects do not expose symbols that are marked with the
+# hidden visibility and consequently building gem5 on Mac OS
+# fails. As a workaround, we disable partial linking, however, we
+# may want to revisit in the future.
+disable_partial = True
+
 # Function to create a new build environment as clone of current
 # environment 'env' with modified object suffix and optional stripped
 # binary.  Additional keyword arguments are appended to corresponding
 # build environment vars.
-def makeEnv(env, label, objsfx, strip=False, disable_partial=False,  
**kwargs):

+def makeEnv(env, label, objsfx, strip=False, **kwargs):
 # SCons doesn't know to append a library suffix when there is a '.' in  
the

 # name.  Use '_' instead.
 libname = 'gem5_' + label
@@ -1370,54 +1381,37 @@
 if 'all' in needed_envs:
 needed_envs += target_types

-disable_partial = False
-if env['PLATFORM'] == 'darwin':
-# Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial
-# linked objects do not expose symbols that are marked with the
-# hidden visibility and consequently building gem5 on Mac OS
-# fails. As a workaround, we disable partial linking, however, we
-# may want to revisit in the future.
-disable_partial = True
-
 # Debug binary
 if 'debug' in needed_envs:
 makeEnv(env, 'debug', '.do',
 CCFLAGS = Split(ccflags['debug']),
 CPPDEFINES = ['DEBUG', 'TRACING_ON=1'],
-LINKFLAGS = Split(ldflags['debug']),
-disable_partial=disable_partial)
+LINKFLAGS = Split(ldflags['debug']))

 # Optimized binary
 if 'opt' in needed_envs:
 makeEnv(env, 'opt', '.o',
 CCFLAGS = Split(ccflags['opt']),
 CPPDEFINES = ['TRACING_ON=1'],
-LINKFLAGS = Split(ldflags['opt']),
-disable_partial=disable_partial)
+LINKFLAGS = Split(ldflags['opt']))

 # "Fast" binary
 if 'fast' in needed_envs:
-disable_partial = disable_partial or \
-(env.get('BROKEN_INCREMENTAL_LTO', False) and \
-GetOption('force_lto'))
 makeEnv(env, 'fast', '.fo', strip = True,
 CCFLAGS = Split(ccflags['fast']),
 CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'],
-LINKFLAGS = Split(ldflags['fast']),
-disable_partial=disable_partial)
+LINKFLAGS = Split(ldflags['fast']))

 # Profiled binary using gprof
 if 'prof' in needed_envs:
 makeEnv(env, 'prof', '.po',
 CCFLAGS = Split(ccflags['prof']),
 CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'],
-LINKFLAGS = Split(ldflags['prof']),
-disable_partial=disable_partial)
+LINKFLAGS = Split(ldflags['prof']))

 # Profiled binary using google-pprof
 if 'perf' in needed_envs:
 makeEnv(env, 'perf', '.gpo',
 CCFLAGS = Split(ccflags['perf']),
 CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'],
-LINKFLAGS = Split(ldflags['perf']),
-disable_partial=disable_partial)
+LINKFLAGS = Split(ldflags['perf']))

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Gerrit-Owner: Gabe Black 

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc,sim: Fixed std::array bracket compiler error

2020-05-18 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29294 )



Change subject: misc,sim: Fixed std::array bracket compiler error
..

misc,sim: Fixed std::array bracket compiler error

For versions of Clang before 6.0, Clang returns an error if and
std::array initialization is not encompassed in two sets of
encompassing braces. This is a known compiler bug:
https://bugs.llvm.org/show_bug.cgi?id=21629.

As we support Clang 3.9 onwards, we are required to include these
redundant braces to ensure compilation. They do not produce any
ill-effects when using later clang compilers or with any GCC compiler
gem5 presently supports.

Change-Id: Ia512a9b9f583b1cfa28f9fc4c24f6e202e46b4cb
Issue-on: https://gem5.atlassian.net/browse/GEM5-563
---
M src/sim/pseudo_inst.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index b11a5a4..203afc0 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -285,7 +285,7 @@
 char key[len];
 memset(key, '\0', len);

-std::array key_regs = { key_str1, key_str2 };
+std::array key_regs = {{ key_str1, key_str2 }};
 key_regs = letoh(key_regs);
 memcpy(key, key_regs.data(), sizeof(key_regs));


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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Fixed GCN3_X86/HSAIL_X86 compilation errors

2020-05-18 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29293 )



Change subject: misc: Fixed GCN3_X86/HSAIL_X86 compilation errors
..

misc: Fixed GCN3_X86/HSAIL_X86 compilation errors

GCN3_X86 and HSAIL_X86 fail to compile. This patch enables compilation.

Issue-on: https://gem5.atlassian.net/browse/GEM5-556
  https://gem5.atlassian.net/browse/GEM5-561

Change-Id: I663e529622ed90254eaf8be01e23991ed8271b5b
---
M src/SConscript
M src/arch/hsail/gen.py
M src/dev/hsa/HSADevice.py
M src/dev/hsa/HSADriver.py
M src/dev/hsa/hsa_device.cc
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_packet_processor.cc
7 files changed, 9 insertions(+), 9 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 134e2a5..1de8a2d 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -624,7 +624,7 @@
 isas = [ src.get_contents().decode('utf-8') for src in source ]
 target_isa = env['TARGET_ISA']
 def define(isa):
-return isa.upper() + '_ISA'
+return str(isa.upper()) + '_ISA'

 def namespace(isa):
 return isa[0].upper() + isa[1:].lower() + 'ISA'
@@ -669,7 +669,7 @@
 isas = [ src.get_contents() for src in source ]
 target_gpu_isa = env['TARGET_GPU_ISA']
 def define(isa):
-return isa.upper() + '_ISA'
+return str(isa.upper()) + '_ISA'

 def namespace(isa):
 return isa[0].upper() + isa[1:].lower() + 'ISA'
diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py
index 8dcc92c..5640424 100755
--- a/src/arch/hsail/gen.py
+++ b/src/arch/hsail/gen.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2.7
+#!/usr/bin/env python
 #  Copyright (c) 2015 Advanced Micro Devices, Inc.
 #  All rights reserved.
 #
diff --git a/src/dev/hsa/HSADevice.py b/src/dev/hsa/HSADevice.py
index 125d6ee..50e3c6d 100644
--- a/src/dev/hsa/HSADevice.py
+++ b/src/dev/hsa/HSADevice.py
@@ -35,7 +35,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import DmaDevice
+from m5.objects.Device import DmaDevice

 class HSADevice(DmaDevice):
 type = 'HSADevice'
diff --git a/src/dev/hsa/HSADriver.py b/src/dev/hsa/HSADriver.py
index ed742fa..3df22a0 100644
--- a/src/dev/hsa/HSADriver.py
+++ b/src/dev/hsa/HSADriver.py
@@ -35,7 +35,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Process import EmulatedDriver
+from m5.objects.Process import EmulatedDriver

 class HSADriver(EmulatedDriver):
 type = 'HSADriver'
diff --git a/src/dev/hsa/hsa_device.cc b/src/dev/hsa/hsa_device.cc
index 01b7a41..c23639e 100644
--- a/src/dev/hsa/hsa_device.cc
+++ b/src/dev/hsa/hsa_device.cc
@@ -102,7 +102,7 @@
  * grab context zero.
  */
 auto process = sys->getThreadContext(0)->getProcessPtr();
-auto mem_state = process->getMemState();
+auto mem_state = process->memState;

 if (!mem_state->translate(vaddr, paddr)) {
 fatal("failed translation: vaddr 0x%x\n", vaddr);
diff --git a/src/dev/hsa/hsa_driver.cc b/src/dev/hsa/hsa_driver.cc
index 5f30159..08e1db3 100644
--- a/src/dev/hsa/hsa_driver.cc
+++ b/src/dev/hsa/hsa_driver.cc
@@ -74,7 +74,7 @@
 "offset: 0x%x)\n", start, length, offset);

 auto process = tc->getProcessPtr();
-auto mem_state = process->getMemState();
+auto mem_state = process->memState;

 // Extend global mmap region if necessary.
 if (start == 0) {
diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index 76da30e..ad59de5 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -152,7 +152,7 @@
 // new extensions, it will likely be wrong to just arbitrarily grab  
context

 // zero.
 auto process = sys->getThreadContext(0)->getProcessPtr();
-auto mem_state = process->getMemState();
+auto mem_state = process->memState;

 if (!mem_state->translate(vaddr, paddr))
 fatal("failed translation: vaddr 0x%x\n", vaddr);
@@ -396,7 +396,7 @@
  */
 auto tc = sys->getThreadContext(0);
 auto process = tc->getProcessPtr();
-auto mem_state = process->getMemState();
+auto mem_state = process->memState;
 auto _proxy = mem_state->getVirtProxy();
 TypedBufferArg prev_signal(signal_addr);
 prev_signal.copyIn(virt_proxy);

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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: configs: Updates for python3

2020-05-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29047 )


Change subject: configs: Updates for python3
..

configs: Updates for python3

Change-Id: Iab2f83716ea2cb19f06282f037314f2db843327a
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29047
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M configs/common/FSConfig.py
M configs/common/FileSystemConfig.py
M configs/common/HMC.py
M configs/common/ObjectList.py
M configs/common/Options.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/dram/lat_mem_rd.py
M configs/dram/sweep.py
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/read_config.py
M configs/ruby/AMD_Base_Constructor.py
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
30 files changed, 100 insertions(+), 66 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index d49ad78..e154593 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -41,12 +41,17 @@
 from __future__ import print_function
 from __future__ import absolute_import

+import six
+
 import m5
 from m5.objects import *
 from m5.util import *
 from common.Benchmarks import *
 from common import ObjectList

+if six.PY3:
+long = int
+
 # Populate to reflect supported os types per target ISA
 os_types = { 'mips'  : [ 'linux' ],
  'riscv' : [ 'linux' ], # TODO that's a lie
@@ -574,7 +579,7 @@

 # We assume below that there's at least 1MB of memory. We'll require 2
 # just to avoid corner cases.
-phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
+phys_mem_size = sum([r.size() for r in self.mem_ranges])
 assert(phys_mem_size >= 0x20)
 assert(len(self.mem_ranges) <= 2)

diff --git a/configs/common/FileSystemConfig.py  
b/configs/common/FileSystemConfig.py

index 97279f1..ec27656 100644
--- a/configs/common/FileSystemConfig.py
+++ b/configs/common/FileSystemConfig.py
@@ -132,7 +132,7 @@
 file_append((procdir, 'cpuinfo'), one_cpu)

 file_append((procdir, 'stat'), 'cpu 0 0 0 0 0 0 0\n')
-for i in xrange(len(cpus)):
+for i in range(len(cpus)):
 file_append((procdir, 'stat'), 'cpu%d 0 0 0 0 0 0 0\n' % i)

 # Set up /sys
diff --git a/configs/common/HMC.py b/configs/common/HMC.py
index c65b201..c4c0acc 100644
--- a/configs/common/HMC.py
+++ b/configs/common/HMC.py
@@ -432,7 +432,7 @@
   for i in range(numx*(opt.mem_chunk-1))]

 # Buffer iterator
-it = iter(range(len(system.hmc_dev.buffers)))
+it = iter(list(range(len(system.hmc_dev.buffers

 # necesarry to add system_port to one of the xbar
 system.system_port = system.hmc_dev.xbar[3].slave
@@ -443,7 +443,7 @@
 # connect xbar to all other xbars except itself
 if i != j:
 # get the next index of buffer
-index = it.next()
+index = next(it)

 # Change the default values for ranges of bridge
 system.hmc_dev.buffers[index].ranges =  
system.mem_ranges[

diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py
index 8bffa5f..c91ea0c 100644
--- a/configs/common/ObjectList.py
+++ b/configs/common/ObjectList.py
@@ -75,7 +75,7 @@
 print("Available {} classes:".format(self.base_cls))
 doc_wrapper = TextWrapper(initial_indent="\t\t",
 subsequent_indent="\t\t")
-for name, cls in self._sub_classes.items():
+for name, cls in list(self._sub_classes.items()):
 print("\t{}".format(name))

 # Try to extract the class documentation from the class help
@@ -87,7 +87,7 @@

 if self._aliases:
 print("\Aliases:")
-for alias, target in self._aliases.items():
+for alias, target in list(self._aliases.items()):
 print("\t{} => {}".format(alias, target))

 def get_names(self):
@@ -156,7 +156,7 @@
 def _add_objects(self):
 """ Add all enum values to the ObjectList """
 self._sub_classes = {}
-for (key, 

[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: config: improve FileSystemConfig compatibility with Python3

2020-05-18 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29292 )



Change subject: config: improve FileSystemConfig compatibility with Python3
..

config: improve FileSystemConfig compatibility with Python3

Signed-off-by: Hoa Nguyen 
Change-Id: Ie787b47bb2f90839255205a66982fc3dfee13540
---
M configs/common/FileSystemConfig.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/configs/common/FileSystemConfig.py  
b/configs/common/FileSystemConfig.py

index 97279f1..ec27656 100644
--- a/configs/common/FileSystemConfig.py
+++ b/configs/common/FileSystemConfig.py
@@ -132,7 +132,7 @@
 file_append((procdir, 'cpuinfo'), one_cpu)

 file_append((procdir, 'stat'), 'cpu 0 0 0 0 0 0 0\n')
-for i in xrange(len(cpus)):
+for i in range(len(cpus)):
 file_append((procdir, 'stat'), 'cpu%d 0 0 0 0 0 0 0\n' % i)

 # Set up /sys

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[gem5-dev] Re: GCN3 Integration

2020-05-18 Thread Matt Sinclair via gem5-dev
 To add onto what Matt said, Kyle Roarty and I will also be giving a talk
in the gem5 workshop about the docker support we've added for the GPU
model.  We are also working on merging that into develop currently.

Matt S.

On Mon, May 18, 2020 at 1:57 PM Poremba, Matthew via gem5-dev <
gem5-dev@gem5.org> wrote:

> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Daniel,
>
>
> We're in the process of merging it into develop. It should be in gem5
> 20.1. There are a few CLs that need reviews first. Tony and I will be
> giving a talk during the gem5 workshop in 2 weeks.
>
>
> -Matt
>
> -Original Message-
> From: Daniel Gerzhoy via gem5-dev 
> Sent: Monday, May 18, 2020 10:39 AM
> To: gem5 Developer List 
> Cc: Daniel Gerzhoy 
> Subject: [gem5-dev] GCN3 Integration
>
> [CAUTION: External Email]
>
> Hello,
>
> I'm wondering if anyone could give an update on the status of integrating
> the gcn3-staging branch into the main branch?
> (From here:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgem5.googlesource.com%2Famd%2Fgem5data=02%7C01%7Cmatthew.poremba%40amd.com%7Cffbf0f89a0d14ae8a43108d7fb52755e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637254203890939524sdata=hJNYBWzfoQuLtL2TG3m3AtabLX7wJx3OHE1y6wkDhNo%3Dreserved=0
>branch: agutierr/master-gcn3-staging)
>
> I saw some emails on this list about it, so I thought I might update to
> the main branch but just from looking into the apu_se.py in the
> develop/19.0 release/20.0 rc I don't see any mention of GPU_VIPER, and a
> couple of other things like the ROCm environment paths that the
> gcn3-staging branch has.
>
> Just hoping to eventually use the main branch if possible.
>
> Cheers and thanks for all the hard work  (and stay safe),
>
> Dan Gerzhoy
> University of Maryland at College Park
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[gem5-dev] Re: GCN3 Integration

2020-05-18 Thread Poremba, Matthew via gem5-dev
[AMD Official Use Only - Internal Distribution Only]

Hi Daniel,


We're in the process of merging it into develop. It should be in gem5 20.1. 
There are a few CLs that need reviews first. Tony and I will be giving a talk 
during the gem5 workshop in 2 weeks.


-Matt

-Original Message-
From: Daniel Gerzhoy via gem5-dev  
Sent: Monday, May 18, 2020 10:39 AM
To: gem5 Developer List 
Cc: Daniel Gerzhoy 
Subject: [gem5-dev] GCN3 Integration

[CAUTION: External Email]

Hello,

I'm wondering if anyone could give an update on the status of integrating the 
gcn3-staging branch into the main branch?
(From here: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgem5.googlesource.com%2Famd%2Fgem5data=02%7C01%7Cmatthew.poremba%40amd.com%7Cffbf0f89a0d14ae8a43108d7fb52755e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637254203890939524sdata=hJNYBWzfoQuLtL2TG3m3AtabLX7wJx3OHE1y6wkDhNo%3Dreserved=0
   branch: agutierr/master-gcn3-staging)

I saw some emails on this list about it, so I thought I might update to the 
main branch but just from looking into the apu_se.py in the develop/19.0 
release/20.0 rc I don't see any mention of GPU_VIPER, and a couple of other 
things like the ROCm environment paths that the gcn3-staging branch has.

Just hoping to eventually use the main branch if possible.

Cheers and thanks for all the hard work  (and stay safe),

Dan Gerzhoy
University of Maryland at College Park
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: scons: Revert LTO and partial linking for gcc >=8.1

2020-05-18 Thread Bobby R. Bruce (Gerrit) via gem5-dev
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29272 )



Change subject: scons: Revert LTO and partial linking for gcc >=8.1
..

scons: Revert LTO and partial linking for gcc >=8.1

This reverts commit f41abbdb5cf5c67233f3d730885d43517969afda,
"scons: Enable LTO and partial linking with gcc >= 8.1."

LTO and partial linking does not work on GCC 9.3 on Ubuntu 20.04 when
compiling gem5.fast. This error was exposed via the following command:

```
docker run -u $UID:$GID --volume $(pwd):/gem5 -w /gem5 --rm \
gcr.io/gem5-test/ubuntu-20.04_all-dependencies:latest scons \
build/MIPS/gem5.fast
```

The following error was received:

```
usr/bin/ld: cannot find lib.fo.partial.lto.o: No such file or directory
/usr/bin/ld: error: could not unlink output file
collect2: error: ld returned 1 exit status
scons: *** [build/MIPS/mem/ruby/system/lib.fo.partial] Error 1
```

Issue-on: https://gem5.atlassian.net/browse/GEM5-555
Change-Id: Id9e7fc81aec9f94524acc92c05aabdf96bd284cd
---
M SConstruct
1 file changed, 11 insertions(+), 6 deletions(-)



diff --git a/SConstruct b/SConstruct
index 0a18c3d..82fad3b 100755
--- a/SConstruct
+++ b/SConstruct
@@ -404,22 +404,27 @@

 main['GCC_VERSION'] = gcc_version

-if compareVersions(gcc_version, '4.9') >= 0 and \
-   compareVersions(gcc_version, '8.1') < 0:
+if compareVersions(gcc_version, '4.9') >= 0:
 # Incremental linking with LTO is currently broken in gcc versions
-# 4.9 to 8.1.
+# 4.9 and above. A version where everything works completely hasn't
+# yet been identified.
 #
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67548
-#
+main['BROKEN_INCREMENTAL_LTO'] = True
+if compareVersions(gcc_version, '6.0') >= 0:
 # gcc versions 6.0 and greater accept an -flinker-output flag which
 # selects what type of output the linker should generate. This is
 # necessary for incremental lto to work, but is also broken in
-# versions of gcc up to 8.1.
+# current versions of gcc. It may not be necessary in future
+# versions. We add it here since it might be, and as a reminder  
that

+# it exists. It's excluded if lto is being forced.
 #
 # https://gcc.gnu.org/gcc-6/changes.html
 # https://gcc.gnu.org/ml/gcc-patches/2015-11/msg03161.html
 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69866
-main['BROKEN_INCREMENTAL_LTO'] = True
+if not GetOption('force_lto'):
+main.Append(PSHLINKFLAGS='-flinker-output=rel')
+main.Append(PLINKFLAGS='-flinker-output=rel')

 disable_lto = GetOption('no_lto')
 if not disable_lto and main.get('BROKEN_INCREMENTAL_LTO', False) and \

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Id9e7fc81aec9f94524acc92c05aabdf96bd284cd
Gerrit-Change-Number: 29272
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: cpu: fixed unused variable on fast binary

2020-05-18 Thread Andrea Mondelli (Gerrit) via gem5-dev
Andrea Mondelli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29252 )



Change subject: cpu: fixed unused variable on fast binary
..

cpu: fixed unused variable on fast binary

When gem5.fast is compiled, an error on a variable
used only for debug purposes is raised:

build/X86/cpu/o3/mem_dep_unit_impl.hh:262:19: error: unused  
variable 'producing_store' [-Werror=unused-variable]

 for (auto producing_store : producing_stores)

This patch remove the variable when *.fast is used.

Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
---
M src/cpu/o3/mem_dep_unit_impl.hh
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/cpu/o3/mem_dep_unit_impl.hh  
b/src/cpu/o3/mem_dep_unit_impl.hh

index 9a50341..57e90d2 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -259,7 +259,9 @@
 } else {
 // Otherwise make the instruction dependent on the store/barrier.
 DPRINTF(MemDepUnit, "Adding to dependency list\n");
+#if TRACING_ON==1
 for (auto producing_store : producing_stores)
+#endif
 DPRINTF(MemDepUnit, "\tinst PC %s is dependent on  
[sn:%lli].\n",

 inst->pcState(), producing_store);


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Gerrit-Branch: develop
Gerrit-Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
Gerrit-Change-Number: 29252
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Gerrit-Owner: Andrea Mondelli 
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[gem5-dev] GCN3 Integration

2020-05-18 Thread Daniel Gerzhoy via gem5-dev
Hello,

I'm wondering if anyone could give an update on the status of integrating
the gcn3-staging branch into the main branch?
(From here: https://gem5.googlesource.com/amd/gem5
   branch: agutierr/master-gcn3-staging)

I saw some emails on this list about it, so I thought I might update to the
main branch but
just from looking into the apu_se.py in the develop/19.0 release/20.0 rc I
don't see any mention of GPU_VIPER, and a couple of other things like the
ROCm environment paths that the gcn3-staging branch has.

Just hoping to eventually use the main branch if possible.

Cheers and thanks for all the hard work  (and stay safe),

Dan Gerzhoy
University of Maryland at College Park
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[gem5-dev] Change in gem5/gem5[develop]: python: Make DOT config generation optional

2020-05-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29232 )



Change subject: python: Make DOT config generation optional
..

python: Make DOT config generation optional

By default, DOT configs are always generated when pydot is present.
This change allows a user to pass --dot-config= to disable generating
the DOT configuration. This can be useful to save space, or to save
Gem5 startup time when running many small regression tests.

This brings the behavior in-line with --dump_config= and --json_config=

Change-Id: I5bf39fda0409b948a8d14f3afa95db8fc78de6ee
---
M src/python/m5/simulate.py
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 3317ae8..698dfbc 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -107,8 +107,9 @@
 except ImportError:
 pass

-do_dot(root, options.outdir, options.dot_config)
-do_ruby_dot(root, options.outdir, options.dot_config)
+if options.dot_config:
+do_dot(root, options.outdir, options.dot_config)
+do_ruby_dot(root, options.outdir, options.dot_config)

 # Initialize the global statistics
 stats.initSimStats()

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Gerrit-Change-Number: 29232
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Add dockerfile for GCN3 w/machine learning

2020-05-18 Thread Kyle Roarty (Gerrit) via gem5-dev
Kyle Roarty has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29192 )



Change subject: util: Add dockerfile for GCN3 w/machine learning
..

util: Add dockerfile for GCN3 w/machine learning

This dockerfile creates an image that installs the software stack needed to
run both machine learning and non-machine learning applications in the GCN3
staging branch, while also applying patches to the software stack to  
optimize

for APUs, which is the current model in the GCN3 staging branch.

Change-Id: If36c2df1c00c895e27e9d741027fd10c17bf224e
---
A util/dockerfiles/gcn-gpu/Dockerfile
A util/dockerfiles/gcn-gpu/README.md
2 files changed, 159 insertions(+), 0 deletions(-)



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

new file mode 100644
index 000..485a406
--- /dev/null
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -0,0 +1,132 @@
+FROM ubuntu:16.04
+
+# Should be minimal needed packages
+RUN apt-get update && apt-get install -y --no-install-recommends \
+findutils \
+file \
+libunwind8 \
+libunwind-dev \
+pkg-config \
+build-essential \
+gcc-multilib \
+g++-multilib \
+git \
+ca-certificates \
+m4 \
+scons \
+zlib1g \
+zlib1g-dev \
+libprotobuf-dev \
+protobuf-compiler \
+libprotoc-dev \
+libgoogle-perftools-dev \
+python-dev \
+python \
+python-yaml \
+wget \
+libpci3 \
+libelf1 \
+libelf-dev \
+cmake \
+openssl \
+libssl-dev \
+libboost-filesystem-dev \
+libboost-system-dev \
+libboost-dev
+
+ARG gem5_dist=http://dist.gem5.org/dist/current
+
+# Install ROCm 1.6 binaries
+RUN wget -qO- ${gem5_dist}/apt_1.6.2.tar.bz2 \
+| tar -xjv \
+&& cd apt_1.6.2/pool/main/ \
+&& dpkg -i h/hsakmt-roct-dev/* \
+&& dpkg -i h/hsa-ext-rocr-dev/* \
+&& dpkg -i h/hsa-rocr-dev/* \
+&& dpkg -i r/rocm-utils/* \
+&& dpkg -i h/hcc/* \
+&& dpkg -i r/rocm-opencl/* \
+&& dpkg -i r/rocm-opencl-dev/*
+
+# Get ROCm libraries we need to compile from source (and ROCm-profiler)
+RUN git clone --single-branch https://github.com/ROCm-Developer-Tools/HIP/  
&& \
+git clone --single-branch  
https://github.com/ROCmSoftwarePlatform/hipBLAS/ && \
+git clone --single-branch  
https://github.com/ROCmSoftwarePlatform/rocBLAS/ && \
+git clone --single-branch  
https://github.com/ROCmSoftwarePlatform/MIOpenGEMM/ && \
+git clone --single-branch  
https://github.com/ROCmSoftwarePlatform/MIOpen/ && \
+git clone --single-branch  
https://github.com/RadeonOpenCompute/rocm-cmake/ && \
+git clone --single-branch  
https://github.com/rocmarchive/ROCm-Profiler.git

+
+# Apply patches to various repos
+RUN mkdir -p /patch && cd /patch && \
+wget ${gem5_dist}/rocm_patches/hipBLAS.patch && \
+wget ${gem5_dist}/rocm_patches/hip.patch && \
+wget ${gem5_dist}/rocm_patches/miopen.patch && \
+wget ${gem5_dist}/rocm_patches/rocBLAS.patch
+
+RUN git -C /HIP/ checkout 0e3d824e && git -C /HIP/ apply /patch/hip.patch  
&& \
+git -C /hipBLAS/ checkout ee57787e && git -C /hipBLAS/ apply  
/patch/hipBLAS.patch && \
+git -C /rocBLAS/ checkout cbff4b4e && git -C /rocBLAS/ apply  
/patch/rocBLAS.patch && \

+git -C /MIOpenGEMM/ checkout 9547fb9e && \
+git -C /MIOpen/ checkout a9949e30 && git -C /MIOpen/ apply  
/patch/miopen.patch

+
+ENV ROCM_PATH /opt/rocm
+ENV HCC_HOME ${ROCM_PATH}/hcc
+ENV HSA_PATH ${ROCM_PATH}/hsa
+ENV HIP_PATH ${ROCM_PATH}/hip
+ENV HIP_PLATFORM hcc
+ENV PATH  
${ROCM_PATH}/bin:${HCC_HOME}/bin:${HSA_PATH}/bin:${HIP_PATH}/bin:${PATH}

+ENV HCC_AMDGPU_TARGET gfx801
+
+# Create build dirs for machine learning ROCm installs
+RUN mkdir -p /HIP/build && \
+mkdir -p /rocBLAS/build && \
+mkdir -p /hipBLAS/build && \
+mkdir -p /rocm-cmake/build && \
+mkdir -p /MIOpenGEMM/build && \
+mkdir -p /MIOpen/build
+
+# Do the builds, empty build dir to trim image size
+WORKDIR /HIP/build
+RUN cmake .. && make -j$(nproc) && make install && rm -rf *
+
+WORKDIR /rocBLAS/build
+RUN CXX=/opt/rocm/bin/hcc cmake  
-DCMAKE_CXX_FLAGS="--amdgpu-target=gfx801" .. && \

+make -j$(nproc) && make install && rm -rf *
+
+WORKDIR /hipBLAS/build
+RUN CXX=/opt/rocm/bin/hcc cmake  
-DCMAKE_CXX_FLAGS="--amdgpu-target=gfx801" .. && \

+make -j$(nproc) && make install && rm -rf *
+
+WORKDIR /rocm-cmake/build
+RUN cmake .. && cmake --build . --target install && rm -rf *
+
+WORKDIR /MIOpenGEMM/build
+RUN cmake .. && make miopengemm && make install && rm -rf *
+
+# Should link this in as a volume if at all possible
+RUN mkdir -p /.cache/miopen && chmod 777 /.cache/miopen
+
+WORKDIR /MIOpen/build
+RUN CXX=/opt/rocm/hcc/bin/hcc cmake \
+-DCMAKE_BUILD_TYPE=Debug \
+-DCMAKE_INSTALL_PREFIX=/opt/rocm \
+-DMIOPEN_BACKEND=HIP \
+