[gem5-dev] Change in gem5/gem5[develop]: base,scons: Fixed `stats/hdf5.cc` CXXFlags to `-Wno-deprecated`
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31216 )
Change subject: base,scons: Fixed `stats/hdf5.cc` CXXFlags to
`-Wno-deprecated`
..
base,scons: Fixed `stats/hdf5.cc` CXXFlags to `-Wno-deprecated`
`Wno-deprecated-copy` was added to disable a warning in hdf5.cc:
https://gem5-review.googlesource.com/c/public/gem5/+/26325.
This works with GCC but does not work with clang. Clang returns
`error: unknown warning option '-Wno-deprecated-copy'; did you mean
'-Wno-deprecated'? [-Werror,-Wunknown-warning-option]` when this flag
is enabled. This flag has therefore been changed to `Wno-deprecated`.
This works in both GCC and Clang.
Change-Id: I38dd58f3007975ccb60b2eec936c3b200b3df3ca
---
M src/base/SConscript
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/base/SConscript b/src/base/SConscript
index fe4e361..657528c 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -91,7 +91,7 @@
Source('stats/group.cc')
Source('stats/text.cc')
if env['USE_HDF5']:
-Source('stats/hdf5.cc', append={'CXXFLAGS': '-Wno-deprecated-copy'})
+Source('stats/hdf5.cc', append={'CXXFLAGS': '-Wno-deprecated'})
GTest('addr_range.test', 'addr_range.test.cc')
GTest('addr_range_map.test', 'addr_range_map.test.cc')
--
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Gerrit-Change-Id: I38dd58f3007975ccb60b2eec936c3b200b3df3ca
Gerrit-Change-Number: 31216
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Added missing `break` to miscregs.cc
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31215 )
Change subject: arch-arm: Added missing `break` to miscregs.cc
..
arch-arm: Added missing `break` to miscregs.cc
Later GCC compilers >=9 fail with a `this statement may fall through`
error due to this missing break.
Change-Id: I44b3386930a0b71b842a3a9b4837e4d6ad588f9d
---
M src/arch/arm/miscregs.cc
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 86b3aaa..e6b979e 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -216,6 +216,7 @@
}
break;
}
+break;
case 6:
switch (crm) {
case 0:
--
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Gerrit-Change-Id: I44b3386930a0b71b842a3a9b4837e4d6ad588f9d
Gerrit-Change-Number: 31215
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[gem5-dev] Change in gem5/gem5[develop]: sim: Added M5_VAR_USED to unused `cpu` var
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31214 )
Change subject: sim: Added M5_VAR_USED to unused `cpu` var
..
sim: Added M5_VAR_USED to unused `cpu` var
The `BaseCPU cpu` variable unused when compiling gem5.fast. This
causes the compilation to fail. Adding the M5_VAR_USED resolves this
issue.
Change-Id: I62588563e9cde384e30755742d6bc754e819d7f4
---
M src/sim/system.cc
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 6e5975e..0c78170 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -45,6 +45,7 @@
#include "arch/remote_gdb.hh"
#include "arch/utility.hh"
+#include "base/compiler.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/str.hh"
@@ -179,7 +180,7 @@
{
auto = thread(id);
# if THE_ISA != NULL_ISA
-BaseCPU *cpu = t.context->getCpuPtr();
+BaseCPU M5_VAR_USED *cpu = t.context->getCpuPtr();
DPRINTFS(Quiesce, cpu, "quiesce()\n");
# endif
t.quiesce();
--
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Gerrit-Change-Id: I62588563e9cde384e30755742d6bc754e819d7f4
Gerrit-Change-Number: 31214
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Relax size contraint on AMBA ID registers
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31175 )
Change subject: dev-arm: Relax size contraint on AMBA ID registers
..
dev-arm: Relax size contraint on AMBA ID registers
This patch is allowing non word sized accesses to the AMBA ID
registers.
Change-Id: I61a7163a3b4120e8dbcdbd6d9b83d33a7996f979
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/amba_device.cc
M src/dev/arm/kmi.cc
M src/dev/arm/pl011.cc
M src/dev/arm/pl111.cc
M src/dev/arm/rtc_pl031.cc
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/dev/arm/amba_device.cc b/src/dev/arm/amba_device.cc
index 31a21b7..7843384 100644
--- a/src/dev/arm/amba_device.cc
+++ b/src/dev/arm/amba_device.cc
@@ -80,7 +80,7 @@
DPRINTF(AMBA, "Returning %#x for offset %#x(%d)\n",
(amba_id >> byte) & 0xFF,
pkt->getAddr() - pio_addr, byte);
-assert(pkt->getSize() == 4);
-pkt->setLE((amba_id >> byte) & 0xFF);
+
+pkt->setUintX((amba_id >> byte) & 0xFF, LittleEndianByteOrder);
return true;
}
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 732398e..23be8b6 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -95,7 +95,7 @@
default:
if (readId(pkt, ambaId, pioAddr)) {
// Hack for variable size accesses
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
}
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index f24cb61..2315370 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -137,7 +137,7 @@
default:
if (readId(pkt, AMBA_ID, pioAddr)) {
// Hack for variable size accesses
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
}
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 369..b733bf7 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -182,7 +182,7 @@
default:
if (readId(pkt, AMBA_ID, pioAddr)) {
// Hack for variable size accesses
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
} else if (daddr >= CrsrImage && daddr <= 0xBFC) {
// CURSOR IMAGE
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index e09ddbe..7d45f8d 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -90,7 +90,7 @@
default:
if (readId(pkt, ambaId, pioAddr)) {
// Hack for variable sized access
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
}
panic("Tried to read PL031 at offset %#x that doesn't exist\n",
daddr);
--
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Gerrit-Owner: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Avoid code duplication in Pl111
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31176 )
Change subject: dev-arm: Avoid code duplication in Pl111
..
dev-arm: Avoid code duplication in Pl111
Change-Id: I17af93459ace0e4ef82693622a4135c3e831aaf5
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/pl111.cc
1 file changed, 2 insertions(+), 31 deletions(-)
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index b733bf7..b864621 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -203,21 +203,7 @@
}
}
-switch(pkt->getSize()) {
- case 1:
-pkt->setLE(data);
-break;
- case 2:
-pkt->setLE(data);
-break;
- case 4:
-pkt->setLE(data);
-break;
- default:
-panic("CLCD controller read size too big?\n");
-break;
-}
-
+pkt->setUintX(data, LittleEndianByteOrder);
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -229,22 +215,7 @@
// use a temporary data since the LCD registers are read/written with
// different size operations
//
-uint32_t data = 0;
-
-switch(pkt->getSize()) {
- case 1:
-data = pkt->getLE();
-break;
- case 2:
-data = pkt->getLE();
-break;
- case 4:
-data = pkt->getLE();
-break;
- default:
-panic("PL111 CLCD controller write size too big?\n");
-break;
-}
+const uint32_t data = pkt->getUintX(LittleEndianByteOrder);
assert(pkt->getAddr() >= pioAddr &&
pkt->getAddr() < pioAddr + pioSize);
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix pmc == on SelfDebug
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31080 )
Change subject: arch-arm: Fix pmc == on SelfDebug
..
arch-arm: Fix pmc == on SelfDebug
The Assignment operator was used instead of the Equal-To
Change-Id: Ibf5a0006bce79b67d662fd1f8942699582956d58
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31080
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/self_debug.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 96c7822..c964b11 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -429,7 +429,7 @@
break;
case EL2:
v = (ssc == 0x3) ||
-((hmc == 0x1) && !((ssc==0x2) && (pmc = 0x0)));
+((hmc == 0x1) && !((ssc==0x2) && (pmc == 0x0)));
if (v && pmc == 0x2)
panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
break;
--
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Gerrit-Change-Id: Ibf5a0006bce79b67d662fd1f8942699582956d58
Gerrit-Change-Number: 31080
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove getters/setters from SelfDebug class
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31081 )
Change subject: arch-arm: Remove getters/setters from SelfDebug class
..
arch-arm: Remove getters/setters from SelfDebug class
Change-Id: I63e5ed25e453cb8fcb2c39ba0728cc81c499c166
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31081
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 13 insertions(+), 40 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index c964b11..63ddb45 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -90,13 +90,13 @@
Addr pc = vaddr;
if (pcst.itstate() != 0x0)
pc = pcst.pc();
-if (p.getEnable() && p.isActive(pc) &&(!to32 || !p.isSet())){
+if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
const DBGBCR ctr = p.getControlReg(tc);
if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
bool debug = p.test(tc, pc, el, ctr, false);
if (debug){
if (to32)
-p.setOnUse();
+p.onUse = true;
return triggerException(tc, pc);
}
}
@@ -109,7 +109,7 @@
Fault
SelfDebug::triggerException(ThreadContext * tc, Addr vaddr)
{
-if (isTo32()) {
+if (to32) {
return std::make_shared(vaddr,
ArmFault::DebugEvent, false,
ArmFault::UnknownTran,
@@ -134,8 +134,7 @@
int idxtmp = -1;
for (auto : arWatchPoints){
idxtmp ++;
-if (p.getEnable())
-{
+if (p.enable) {
bool debug = p.test(tc, vaddr, el, write, atomic, size);
if (debug){
return triggerWatchpointException(tc, vaddr, write, cm);
@@ -149,7 +148,7 @@
SelfDebug::triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm)
{
-if (isTo32()) {
+if (to32) {
ArmFault::DebugType d = cm? ArmFault::WPOINT_CM:
ArmFault::WPOINT_NOCM;
return std::make_shared(vaddr,
@@ -211,7 +210,7 @@
{
bool debug = false;
const DBGBCR ctr = getControlReg(tc);
-if ((ctr.bt & 0x1) && getEnable()){
+if ((ctr.bt & 0x1) && enable) {
debug = test(tc, vaddr, el, ctr, true);
}
return debug;
@@ -527,7 +526,6 @@
uint8_t mask, unsigned size)
{
Addr addr_tocmp = getAddrfromReg(tc);
-int maxAddrSize = getMaxAddrSize();
int maxbits = isDoubleAligned(addr_tocmp) ? 4: 8;
int bottom = isDoubleAligned(addr_tocmp) ? 2: 3;
Addr addr = bits(in_addr, maxAddrSize, 0);
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 121ddde..c185223 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -68,6 +68,8 @@
bool onUse;
public:
+friend class SelfDebug;
+
BrkPoint(MiscRegIndex _ctrlIndex, MiscRegIndex _valIndex,
MiscRegIndex _xIndex, SelfDebug* _conf, bool _ctxAw, bool lva,
bool vmid16, bool aarch32):
@@ -77,20 +79,9 @@
{
maxAddrSize = lva ? 52: 48 ;
maxAddrSize = aarch32 ? 31 : maxAddrSize;
-onUse=false;
-}
-void setOnUse()
-{
-onUse = true;
-}
-void unsetOnUse()
-{
onUse = false;
}
-bool isSet()
-{
-return onUse;
-}
+
bool testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el);
bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr,
bool from_link);
@@ -138,11 +129,6 @@
{
enable = val.e == 0x1;
}
-bool getEnable()
-{
-return enable;
-}
-
};
class WatchPoint
@@ -154,13 +140,9 @@
bool enable;
int maxAddrSize;
-inline int getMaxAddrSize()
-{
-return maxAddrSize;
-}
-
-
public:
+friend class SelfDebug;
+
WatchPoint(MiscRegIndex _ctrlIndex, MiscRegIndex _valIndex,
SelfDebug* _conf, bool lva, bool aarch32):
ctrlRegIndex(_ctrlIndex),
@@ -188,10 +170,6 @@
{
enable = val.e == 0x1;
}
-bool getEnable()
-{
-return enable;
-}
bool isEnabled(ThreadContext* tc, ExceptionLevel el, bool hmc,
uint8_t ssc, uint8_t pac);
@@ -368,7 +346,7 @@
void activateDebug()
{
for (auto : arBrkPoints){
-p.unsetOnUse();
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding style in self_debug.[cc, hh]
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31082 )
Change subject: arch-arm: Fix coding style in self_debug.[cc, hh]
..
arch-arm: Fix coding style in self_debug.[cc, hh]
Change-Id: I67be98af412b745ea9e16d4e8c6d422c9fbb29fc
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31082
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 229 insertions(+), 209 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 63ddb45..94d2f23 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -107,7 +107,7 @@
Fault
-SelfDebug::triggerException(ThreadContext * tc, Addr vaddr)
+SelfDebug::triggerException(ThreadContext *tc, Addr vaddr)
{
if (to32) {
return std::make_shared(vaddr,
@@ -164,15 +164,17 @@
SelfDebug::isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el,
bool secure, bool mask)
{
-bool route_to_el2 = ArmSystem::haveEL(tc, EL2)
- && !secure && enableTdeTge;
-ExceptionLevel target_el = route_to_el2? EL2 : EL1;
-if (oslk || (bSDD && secure && ArmSystem::haveEL(tc, EL3))){
+bool route_to_el2 = ArmSystem::haveEL(tc, EL2) &&
+!secure && enableTdeTge;
+
+ExceptionLevel target_el = route_to_el2 ? EL2 : EL1;
+if (oslk || (bSDD && secure && ArmSystem::haveEL(tc, EL3))) {
return false;
}
-if (el == target_el){
+
+if (el == target_el) {
return bKDE && !mask;
-}else{
+} else {
return target_el > el;
}
}
@@ -181,15 +183,16 @@
SelfDebug::isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el,
bool secure, bool mask)
{
-if (el==EL0 && !ELStateUsingAArch32(tc, EL1, secure)){
+if (el == EL0 && !ELStateUsingAArch32(tc, EL1, secure)) {
return isDebugEnabledForEL64(tc, el, secure, mask);
}
-if (oslk){
+
+if (oslk) {
return false;
}
bool enabled;
-if (secure && ArmSystem::haveEL(tc, EL3)){
+if (secure && ArmSystem::haveEL(tc, EL3)) {
// We ignore the check for invasive External debug checking SPIDEN
// and DBGEN signals. They are not implemented
bool spd32 = bits(tc->readMiscReg(MISCREG_MDCR_EL3), 14);
@@ -197,9 +200,7 @@
bool suiden = bits(tc->readMiscReg(MISCREG_SDER), 0);
enabled = el == EL0 ? (enabled || suiden) : enabled;
-}
-else
-{
+} else {
enabled = el != EL2;
}
return enabled;
@@ -306,6 +307,61 @@
return v;
}
+void
+SelfDebug::init(ThreadContext *tc)
+{
+if (initialized)
+return;
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+aarch32 = cpsr.width == 1;
+
+const AA64DFR0 dfr = tc->readMiscReg(MISCREG_ID_AA64DFR0_EL1);
+const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
+const AA64MMFR1 mm_fr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+
+for (int i = 0; i <= dfr.brps; i++) {
+const bool isctxaw = i >= (dfr.brps - dfr.ctx_cmps);
+
+BrkPoint bkp = BrkPoint((MiscRegIndex)(MISCREG_DBGBCR0_EL1 + i),
+(MiscRegIndex)(MISCREG_DBGBVR0_EL1 + i),
+this, isctxaw, (bool)mm_fr2.varange,
+mm_fr1.vmidbits, aarch32);
+const DBGBCR ctr = tc->readMiscReg(MISCREG_DBGBCR0_EL1 + i);
+
+bkp.updateControl(ctr);
+arBrkPoints.push_back(bkp);
+}
+
+for (int i = 0; i <= dfr.wrps; i++) {
+WatchPoint wtp = WatchPoint((MiscRegIndex)(MISCREG_DBGWCR0 + i),
+(MiscRegIndex)(MISCREG_DBGWVR0 + i),
+this, (bool)mm_fr2.varange, aarch32);
+const DBGWCR ctr = tc->readMiscReg(MISCREG_DBGWCR0 + i);
+
+wtp.updateControl(ctr);
+arWatchPoints.push_back(wtp);
+}
+
+initialized = true;
+
+RegVal oslar_el1 = tc->readMiscReg(MISCREG_OSLAR_EL1);
+updateOSLock(oslar_el1);
+// Initialize preloaded control booleans
+uint64_t mdscr_el1 = tc->readMiscReg(MISCREG_MDSCR_EL1);
+setMDSCRvals(mdscr_el1);
+
+const uint64_t mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
+setbSDD(mdcr_el3);
+
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
+setenableTDETGE(hcr, mdcr);
+
+// Enable Vector Catch Exceptions
+const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
+vcExcpt = new
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Move breakpoint/watchpoint check out of the TLB
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31079 )
Change subject: arch-arm: Move breakpoint/watchpoint check out of the TLB
..
arch-arm: Move breakpoint/watchpoint check out of the TLB
The breakpoint, watchpoint, vector catch and software step checks
have been moved from the TLB to the SelfDebug class.
This is cleaningup the TLB model which is simply asking the SelfDebug
class if there is a pending debug fault
Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31079
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
3 files changed, 35 insertions(+), 19 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 9a60aab..96c7822 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -45,6 +45,31 @@
using namespace std;
Fault
+SelfDebug::testDebug(ThreadContext *tc, const RequestPtr ,
+ BaseTLB::Mode mode)
+{
+Fault fault = NoFault;
+
+if (mode == BaseTLB::Execute) {
+const bool d_step = softStep->advanceSS(tc);
+if (!d_step) {
+fault = testVectorCatch(tc, req->getVaddr(), nullptr);
+if (fault == NoFault)
+fault = testBreakPoints(tc, req->getVaddr());
+}
+} else if (!req->isCacheMaintenance() ||
+ (req->isCacheInvalidate() && !req->isCacheClean())) {
+bool md = mode == BaseTLB::Write ? true: false;
+fault = testWatchPoints(tc, req->getVaddr(), md,
+req->isAtomic(),
+req->getSize(),
+req->isCacheMaintenance());
+}
+
+return fault;
+}
+
+Fault
SelfDebug::testBreakPoints(ThreadContext *tc, Addr vaddr)
{
if (!enableFlag)
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 67654d2..121ddde 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -44,6 +44,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/types.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/tlb.hh"
#include "cpu/thread_context.hh"
class ThreadContext;
@@ -322,14 +323,19 @@
delete vcExcpt;
}
+Fault testDebug(ThreadContext *tc, const RequestPtr ,
+BaseTLB::Mode mode);
+
+ protected:
Fault testBreakPoints(ThreadContext *tc, Addr vaddr);
Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
bool atomic, unsigned size, bool cm);
-Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
Fault triggerException(ThreadContext * tc, Addr vaddr);
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm);
+ public:
+Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
inline BrkPoint* getBrkPoint(uint8_t index)
{
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f007f93..db0d55c 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1213,24 +1213,9 @@
//Check for Debug Exceptions
if (fault == NoFault) {
auto *isa = static_cast(tc->getIsaPtr());
-SelfDebug * sd = isa->getSelfDebug();
-if (mode == Execute)
-{
-const bool d_step = sd->getSstep()->advanceSS(tc);
-if (!d_step) {
-fault = sd->testVectorCatch(tc, req->getVaddr(), nullptr);
-if (fault == NoFault)
-fault = sd->testBreakPoints(tc, req->getVaddr());
-}
-}
-else if (!req->isCacheMaintenance() ||
- (req->isCacheInvalidate() && !req->isCacheClean())) {
-bool md = mode == Write ? true: false;
-fault = sd->testWatchPoints(tc, req->getVaddr(), md,
-req->isAtomic(),
-req->getSize(),
-req->isCacheMaintenance());
-}
+SelfDebug *sd = isa->getSelfDebug();
+
+fault = sd->testDebug(tc, req, mode);
}
return fault;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31079
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Gerrit-Change-Number: 31079
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer:
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: fix bits that SDWA selects
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29931 )
Change subject: arch-gcn3: fix bits that SDWA selects
..
arch-gcn3: fix bits that SDWA selects
This commit fixes a bug in 200f2408 where the SDWA support was selecting
bits
backwards. As part of this commit, to help resolve this problem in the
future, I have added asserts in the helper functions in bitfield.hh to
ensure
that the number of bits aren't negative.
Change-Id: I4b0ecb0e7c110600c0b5063101b75f9adcc512ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29931
Tested-by: kokoro
Reviewed-by: Anthony Gutierrez
Reviewed-by: Matt Sinclair
Maintainer: Anthony Gutierrez
---
M src/arch/gcn3/insts/inst_util.hh
M src/base/bitfield.hh
2 files changed, 37 insertions(+), 30 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/gcn3/insts/inst_util.hh
b/src/arch/gcn3/insts/inst_util.hh
index 292e3ba..433ccbe 100644
--- a/src/arch/gcn3/insts/inst_util.hh
+++ b/src/arch/gcn3/insts/inst_util.hh
@@ -551,7 +551,7 @@
const SDWASelVals sel, const bool signExt)
{
// local variables
-int first_bit = 0, last_bit = 0;
+int low_bit = 0, high_bit = 0;
bool signExt_local = signExt;
T retVal = 0;
@@ -566,17 +566,19 @@
of byte 0, or makes the bits of the selected byte be byte 0
(and
next either sign extends or zero's out upper bits).
*/
-first_bit = (sel * Gcn3ISA::BITS_PER_BYTE);
-last_bit = first_bit + Gcn3ISA::MSB_PER_BYTE;
-retVal = bits(currOperVal, first_bit, last_bit);
+low_bit = (sel * Gcn3ISA::BITS_PER_BYTE);
+high_bit = low_bit + Gcn3ISA::MSB_PER_BYTE;
+retVal = bits(currOperVal, high_bit, low_bit);
// make sure update propagated, since used next
-assert(bits(retVal, Gcn3ISA::MSB_PER_BYTE) ==
- bits(origOperVal, (sel * Gcn3ISA::BITS_PER_BYTE) +
-Gcn3ISA::MSB_PER_BYTE));
+fatal_if(bits(retVal, Gcn3ISA::MSB_PER_BYTE) !=
+ bits(origOperVal, high_bit),
+ "ERROR: SDWA byte update not propagated: retVal: %d, "
+ "orig: %d\n", bits(retVal, Gcn3ISA::MSB_PER_BYTE),
+ bits(origOperVal, high_bit));
// sign extended value depends on upper-most bit of the new
byte 0
signExt_local = (signExt &&
- (bits(retVal, 0, Gcn3ISA::MSB_PER_BYTE) &
0x80));
+ (bits(retVal, Gcn3ISA::MSB_PER_BYTE, 0) &
0x80));
// process all other bytes -- if sign extending, make them 1,
else
// all 0's so leave as is
@@ -589,17 +591,20 @@
of word 0, or makes the bits of the selected word be word 0
(and
next either sign extends or zero's out upper bits).
*/
-first_bit = (sel & 1) * Gcn3ISA::BITS_PER_WORD;
-last_bit = first_bit + Gcn3ISA::MSB_PER_WORD;
-retVal = bits(currOperVal, first_bit, last_bit);
+low_bit = (sel & 1) * Gcn3ISA::BITS_PER_WORD;
+high_bit = low_bit + Gcn3ISA::MSB_PER_WORD;
+retVal = bits(currOperVal, high_bit, low_bit);
// make sure update propagated, since used next
-assert(bits(retVal, Gcn3ISA::MSB_PER_WORD) ==
- bits(origOperVal, ((sel & 1) * Gcn3ISA::BITS_PER_WORD) +
-Gcn3ISA::MSB_PER_WORD));
+fatal_if(bits(retVal, Gcn3ISA::MSB_PER_WORD) !=
+ bits(origOperVal, high_bit),
+ "ERROR: SDWA word update not propagated: retVal: %d, "
+ "orig: %d\n",
+ bits(retVal, Gcn3ISA::MSB_PER_WORD),
+ bits(origOperVal, high_bit));
// sign extended value depends on upper-most bit of the new
word 0
signExt_local = (signExt &&
- (bits(retVal, 0, Gcn3ISA::MSB_PER_WORD) &
+ (bits(retVal, Gcn3ISA::MSB_PER_WORD, 0) &
0x8000));
// process other word -- if sign extending, make them 1, else
all
@@ -659,7 +664,7 @@
const SDWADstVals unusedBits_format)
{
// local variables
-int first_bit = 0, last_bit = 0;
+int low_bit = 0, high_bit = 0;
bool signExt = (unusedBits_format == SDWA_UNUSED_SEXT);
//bool pad = (unusedBits_format == SDWA_UNUSED_PAD);
bool preserve = (unusedBits_format == SDWA_UNUSED_PRESERVE);
@@ -679,11 +684,11
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Fix VOP2 dissasembly prints
Anthony Gutierrez has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/29936 ) Change subject: arch-gcn3: Fix VOP2 dissasembly prints .. arch-gcn3: Fix VOP2 dissasembly prints VOP2 prints VSRC1 register index as hex instead of decimal if the instruction contains a literal operand. This patch resets the format specifiers in the stream to print the register correctly. Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29936 Tested-by: kokoro Reviewed-by: Anthony Gutierrez Maintainer: Anthony Gutierrez --- M src/arch/gcn3/insts/op_encodings.cc 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/gcn3/insts/op_encodings.cc b/src/arch/gcn3/insts/op_encodings.cc index 2eb4042..fe501f2 100644 --- a/src/arch/gcn3/insts/op_encodings.cc +++ b/src/arch/gcn3/insts/op_encodings.cc @@ -763,7 +763,8 @@ << extData.imm_u32 << ", "; } -dis_stream << "v" << instData.VSRC1; +dis_stream << std::resetiosflags(std::ios_base::basefield) << "v" +<< instData.VSRC1; if (readsVCC()) dis_stream << ", vcc"; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29936 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f Gerrit-Change-Number: 29936 Gerrit-PatchSet: 9 Gerrit-Owner: Anthony Gutierrez Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Michael LeBeane Gerrit-Reviewer: Tony Gutierrez Gerrit-Reviewer: Tuan Ta Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Dropping fetchs when no entry is reserved in the buffer
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29932 )
Change subject: gpu-compute: Dropping fetchs when no entry is reserved in
the buffer
..
gpu-compute: Dropping fetchs when no entry is reserved in the buffer
This changeset drops fetches if there is no entry reserved in the
fetch buffer for that instruction. This can happen due to a fetch
attempted to be issued in the same cycle where a branch instruction
flushed the fetch buffer, while an ITLB or I-cache request is still
pending.
Change-Id: I3b80dbd71af27ccf790b543bd5c034bb9b02624a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29932
Tested-by: kokoro
Reviewed-by: Anthony Gutierrez
Reviewed-by: Onur Kayıran
Maintainer: Anthony Gutierrez
---
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
2 files changed, 22 insertions(+), 0 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
Onur Kayıran: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index fb04cd2..447ff12 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -235,6 +235,16 @@
delete oldPkt;
/**
+ * if we have not reserved an entry in the fetch buffer,
+ * stop fetching. this can happen due to a branch instruction
+ * flushing the fetch buffer while an ITLB or I-cache request is still
+ * pending, in the same cycle another instruction is trying to fetch.
+ */
+if
(!fetchBuf.at(wavefront->wfSlotId).isReserved(pkt->req->getVaddr())) {
+return;
+}
+
+/**
* we should have reserved an entry in the fetch buffer
* for this cache line. here we get the pointer to the
* entry used to buffer this request's line data.
diff --git a/src/gpu-compute/fetch_unit.hh b/src/gpu-compute/fetch_unit.hh
index 2cfe3f0..798c264 100644
--- a/src/gpu-compute/fetch_unit.hh
+++ b/src/gpu-compute/fetch_unit.hh
@@ -120,6 +120,18 @@
return reserved_pc->second;
}
+/**
+ * returns true if there is an entry reserved for this address,
+ * and false otherwise
+ */
+bool
+isReserved(Addr vaddr) const
+{
+auto reserved_pc = reservedPCs.find(vaddr);
+bool is_reserved = (reserved_pc != reservedPCs.end());
+return is_reserved;
+}
+
void fetchDone(Addr vaddr);
/**
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29932
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3b80dbd71af27ccf790b543bd5c034bb9b02624a
Gerrit-Change-Number: 29932
Gerrit-PatchSet: 9
Gerrit-Owner: Anthony Gutierrez
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Onur Kayıran
Gerrit-Reviewer: Tony Gutierrez
Gerrit-Reviewer: Tuan Ta
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Fix writelane src0,src1 usage
Anthony Gutierrez has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/29933 ) Change subject: arch-gcn3: Fix writelane src0,src1 usage .. arch-gcn3: Fix writelane src0,src1 usage Src1 should only be used for lane select. The data should come from src0. Change-Id: Ibe960df2e56d351a3819b40194104d2972a5cd4c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29933 Tested-by: kokoro Maintainer: Anthony Gutierrez Reviewed-by: Anthony Gutierrez Reviewed-by: Matt Sinclair --- M src/arch/gcn3/insts/instructions.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved Matt Sinclair: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc index 0256d46..b923eae 100644 --- a/src/arch/gcn3/insts/instructions.cc +++ b/src/arch/gcn3/insts/instructions.cc @@ -30181,7 +30181,7 @@ assert(!(extData.NEG & 0x2)); assert(!(extData.NEG & 0x4)); -vdst[src1.rawData() & 0x3f] = src1.rawData(); +vdst[src1.rawData() & 0x3f] = src0.rawData(); vdst.write(); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29933 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibe960df2e56d351a3819b40194104d2972a5cd4c Gerrit-Change-Number: 29933 Gerrit-PatchSet: 9 Gerrit-Owner: Anthony Gutierrez Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Michael LeBeane Gerrit-Reviewer: Tony Gutierrez Gerrit-Reviewer: Tuan Ta Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3, gpu-compute: Implement out-of-range accesses
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29935 )
Change subject: arch-gcn3, gpu-compute: Implement out-of-range accesses
..
arch-gcn3, gpu-compute: Implement out-of-range accesses
Certain buffer out-of-range memory accesses should be special
cased and not generate memory accesses. This patch implements
those special cases and supresses lanes from accessing memory
when the calculated address falls in an ISA-specified out-of-range
condition.
Change-Id: I8298f861c6b59587789853a01e503ba7d98cb13d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29935
Tested-by: kokoro
Reviewed-by: Anthony Gutierrez
Reviewed-by: Matt Sinclair
Maintainer: Anthony Gutierrez
---
M src/arch/gcn3/insts/instructions.cc
M src/arch/gcn3/insts/op_encodings.hh
M src/gpu-compute/global_memory_pipeline.cc
3 files changed, 96 insertions(+), 6 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index b923eae..2e39bf5 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -34453,8 +34453,12 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
-vdst[lane] = (VecElemU32)((reinterpret_cast(
-gpuDynInst->d_data))[lane]);
+if (!oobMask[lane]) {
+vdst[lane] =
(VecElemU32)((reinterpret_cast(
+gpuDynInst->d_data))[lane]);
+} else {
+vdst[lane] = 0;
+}
}
}
@@ -34580,8 +34584,12 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
-vdst[lane] = (VecElemU32)((reinterpret_cast(
-gpuDynInst->d_data))[lane]);
+if (!oobMask[lane]) {
+vdst[lane] =
(VecElemU32)((reinterpret_cast(
+gpuDynInst->d_data))[lane]);
+} else {
+vdst[lane] = 0;
+}
}
}
@@ -34707,8 +34715,12 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
-vdst[lane] = (reinterpret_cast(
-gpuDynInst->d_data))[lane];
+if (!oobMask[lane]) {
+vdst[lane] = (reinterpret_cast(
+gpuDynInst->d_data))[lane];
+} else {
+vdst[lane] = 0;
+}
}
}
diff --git a/src/arch/gcn3/insts/op_encodings.hh
b/src/arch/gcn3/insts/op_encodings.hh
index 308560a..22c146a 100644
--- a/src/arch/gcn3/insts/op_encodings.hh
+++ b/src/arch/gcn3/insts/op_encodings.hh
@@ -40,6 +40,7 @@
#include "arch/gcn3/gpu_mem_helpers.hh"
#include "arch/gcn3/insts/gpu_static_inst.hh"
#include "arch/gcn3/operand.hh"
+#include "debug/GCN3.hh"
#include "debug/GPUExec.hh"
#include "mem/ruby/system/RubySystem.hh"
@@ -489,14 +490,26 @@
void
initMemRead(GPUDynInstPtr gpuDynInst)
{
+// temporarily modify exec_mask to supress memory accesses to
oob
+// regions. Only issue memory requests for lanes that have
their
+// exec_mask set and are not out of bounds.
+VectorMask old_exec_mask = gpuDynInst->exec_mask;
+gpuDynInst->exec_mask &= ~oobMask;
initMemReqHelper(gpuDynInst, MemCmd::ReadReq);
+gpuDynInst->exec_mask = old_exec_mask;
}
template
void
initMemWrite(GPUDynInstPtr gpuDynInst)
{
+// temporarily modify exec_mask to supress memory accesses to
oob
+// regions. Only issue memory requests for lanes that have
their
+// exec_mask set and are not out of bounds.
+VectorMask old_exec_mask = gpuDynInst->exec_mask;
+gpuDynInst->exec_mask &= ~oobMask;
initMemReqHelper(gpuDynInst, MemCmd::WriteReq);
+gpuDynInst->exec_mask = old_exec_mask;
}
void
@@ -566,6 +579,42 @@
buf_off = v_off[lane] + inst_offset;
+
+/**
+ * Range check behavior causes out of range accesses to
+ * to be treated differently. Out of range accesses
return
+ * 0 for loads and are ignored for stores. For
+ * non-formatted accesses, this is done on a per-lane
+ * basis.
+ */
+if (rsrc_desc.stride == 0 ||
[gem5-dev] Change in gem5/gem5[develop]: tests: Add realview64-kvm.py testing platform
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31218 ) Change subject: tests: Add realview64-kvm.py testing platform .. tests: Add realview64-kvm.py testing platform Change-Id: If9952563413b4c7462a3ddf46c40358023d5bc60 Signed-off-by: Giacomo Travaglini --- A tests/configs/realview64-kvm.py 1 file changed, 42 insertions(+), 0 deletions(-) diff --git a/tests/configs/realview64-kvm.py b/tests/configs/realview64-kvm.py new file mode 100644 index 000..f69008d --- /dev/null +++ b/tests/configs/realview64-kvm.py @@ -0,0 +1,42 @@ +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects import * +from arm_generic import * + +root = LinuxArmFSSystemUniprocessor(mem_mode='atomic_noncaching', +machine_type='VExpress_GEM5_V1', +mem_class=SimpleMemory, +cpu_class=ArmV8KvmCPU).create_root() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31218 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If9952563413b4c7462a3ddf46c40358023d5bc60 Gerrit-Change-Number: 31218 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Add realview64-kvm.py test to quick regressions
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31219 ) Change subject: tests: Add realview64-kvm.py test to quick regressions .. tests: Add realview64-kvm.py test to quick regressions By using the valid_host parameter we can make sure the test is run on a aarch64 host only Signed-off-by: Giacomo Travaglini Change-Id: I3cdb35967e85377f26adf73ad147cb2479162ca1 --- M tests/gem5/fs/linux/arm/test.py 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tests/gem5/fs/linux/arm/test.py b/tests/gem5/fs/linux/arm/test.py index 39cb011..c15bd8b 100644 --- a/tests/gem5/fs/linux/arm/test.py +++ b/tests/gem5/fs/linux/arm/test.py @@ -41,6 +41,10 @@ from testlib import * +arm_fs_kvm_tests = [ +'realview64-kvm', +] + arm_fs_quick_tests = [ 'realview64-simple-atomic', 'realview64-simple-atomic-dual', @@ -49,7 +53,7 @@ 'realview64-simple-timing-dual', 'realview64-switcheroo-atomic', 'realview64-switcheroo-timing', -] +] + arm_fs_kvm_tests arm_fs_long_tests = [ 'realview-simple-atomic', @@ -87,6 +91,12 @@ arm_fs_binaries = DownloadedArchive(url, path, tarball) for name in arm_fs_quick_tests: +if name in arm_fs_kvm_tests: +# Run KVM test if we are on an arm host only +valid_hosts = (constants.host_arm_tag,) +else: +valid_hosts = constants.supported_hosts + args = [ joinpath(config.base_dir, 'tests', 'configs', name + '.py'), path @@ -98,6 +108,7 @@ config_args=args, valid_isas=(constants.arm_tag,), length=constants.quick_tag, +valid_hosts=valid_hosts, fixtures=(arm_fs_binaries,) ) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31219 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3cdb35967e85377f26adf73ad147cb2479162ca1 Gerrit-Change-Number: 31219 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: System is expecting a kvm_vm param for KvmVM
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31217 ) Change subject: tests: System is expecting a kvm_vm param for KvmVM .. tests: System is expecting a kvm_vm param for KvmVM Signed-off-by: Giacomo Travaglini Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16 --- M tests/configs/base_config.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index b124a13..a4b2cc4 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -134,7 +134,7 @@ Arguments: system -- System to work on. """ -system.vm = KvmVM() +system.kvm_vm = KvmVM() def init_system(self, system): """Initialize a system. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31217 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16 Gerrit-Change-Number: 31217 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional WriteMask methods
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31257 )
Change subject: mem-ruby: additional WriteMask methods
..
mem-ruby: additional WriteMask methods
Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index 0ba6989..e0eac5a 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2012-15 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -68,18 +80,18 @@
}
bool
-test(int offset)
+test(int offset) const
{
assert(offset < mSize);
return mMask[offset];
}
void
-setMask(int offset, int len)
+setMask(int offset, int len, bool val = true)
{
assert(mSize >= (offset + len));
for (int i = 0; i < len; i++) {
-mMask[offset + i] = true;
+mMask[offset + i] = val;
}
}
void
@@ -162,6 +174,33 @@
}
}
+void
+invMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = !writeMask.mMask.at(i);
+}
+}
+
+int
+firstBitSet(bool val, int offset = 0) const
+{
+for (int i = offset; i < mSize; ++i)
+if (mMask[i] == val)
+return i;
+return mSize;
+}
+
+int
+count(int offset = 0) const
+{
+int count = 0;
+for (int i = offset; i < mSize; ++i)
+count += mMask[i];
+return count;
+}
+
void print(std::ostream& out) const;
void
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index f1d17c8..077e76d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -58,7 +58,16 @@
bool isFull();
bool isOverlap(WriteMask);
void orMask(WriteMask);
+ void invMask(WriteMask);
void fillMask();
+ void setMask(int,int);
+ bool getMask(int,int);
+ void setMask(int,int,bool);
+ int firstBitSet(bool);
+ int firstBitSet(bool,int);
+ int count();
+ int count(int);
+ bool test(int);
}
structure(DataBlock, external = "yes", desc="..."){
--
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Gerrit-Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Gerrit-Change-Number: 31257
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix include dependency
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31258 )
Change subject: mem-ruby: fix include dependency
..
mem-ruby: fix include dependency
Removed include dependency between WriteMask and RubySystem.
Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/WriteMask.cc
M src/mem/ruby/common/WriteMask.hh
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/common/WriteMask.cc
b/src/mem/ruby/common/WriteMask.cc
index 4585077..54ba8ff 100644
--- a/src/mem/ruby/common/WriteMask.cc
+++ b/src/mem/ruby/common/WriteMask.cc
@@ -32,6 +32,11 @@
#include "mem/ruby/system/RubySystem.hh"
+WriteMask::WriteMask()
+: mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
+ mAtomic(false)
+{}
+
void
WriteMask::print(std::ostream& out) const
{
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index e0eac5a..47705a0 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -46,16 +46,14 @@
#include
#include
+#include "base/amo.hh"
+#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
-#include "mem/ruby/system/RubySystem.hh"
class WriteMask
{
public:
-WriteMask()
- : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
-mAtomic(false)
-{}
+WriteMask();
WriteMask(int size)
: mSize(size), mMask(size, false), mAtomic(false)
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Sequencer can be used without cache
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31267 ) Change subject: mem-ruby: Sequencer can be used without cache .. mem-ruby: Sequencer can be used without cache Moved the dcache check to the LLSC functions that use it. This allows a Sequencer to be coupled with a gem5 object that does not need a cache (as long as it doesn't issue LLSC instructions). Also, icache was not used at all so it was removed. Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1 Signed-off-by: Tiago Mück --- M configs/learning_gem5/part3/msi_caches.py M configs/learning_gem5/part3/ruby_caches_MI_example.py M configs/learning_gem5/part3/test_caches.py M configs/ruby/AMD_Base_Constructor.py M configs/ruby/GPU_RfO.py M configs/ruby/GPU_VIPER.py M configs/ruby/GPU_VIPER_Baseline.py M configs/ruby/GPU_VIPER_Region.py M configs/ruby/Garnet_standalone.py M configs/ruby/MESI_Three_Level.py M configs/ruby/MESI_Two_Level.py M configs/ruby/MI_example.py M configs/ruby/MOESI_AMD_Base.py M configs/ruby/MOESI_CMP_directory.py M configs/ruby/MOESI_CMP_token.py M configs/ruby/MOESI_hammer.py M src/mem/ruby/system/Sequencer.cc M src/mem/ruby/system/Sequencer.hh M src/mem/ruby/system/Sequencer.py 19 files changed, 24 insertions(+), 40 deletions(-) diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py index f899426..d718a6b 100644 --- a/configs/learning_gem5/part3/msi_caches.py +++ b/configs/learning_gem5/part3/msi_caches.py @@ -82,7 +82,6 @@ # and other controllers, too. self.sequencers = [RubySequencer(version = i, # I/D cache is combined and grab from ctrl -icache = self.controllers[i].cacheMemory, dcache = self.controllers[i].cacheMemory, clk_domain = self.controllers[i].clk_domain, ) for i in range(len(cpus))] diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py b/configs/learning_gem5/part3/ruby_caches_MI_example.py index 29b66a6..8c0e563 100644 --- a/configs/learning_gem5/part3/ruby_caches_MI_example.py +++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py @@ -82,7 +82,6 @@ # and other controllers, too. self.sequencers = [RubySequencer(version = i, # I/D cache is combined and grab from ctrl -icache = self.controllers[i].cacheMemory, dcache = self.controllers[i].cacheMemory, clk_domain = self.controllers[i].clk_domain, ) for i in range(len(cpus))] diff --git a/configs/learning_gem5/part3/test_caches.py b/configs/learning_gem5/part3/test_caches.py index 855bf17..cdf5d19 100644 --- a/configs/learning_gem5/part3/test_caches.py +++ b/configs/learning_gem5/part3/test_caches.py @@ -76,7 +76,6 @@ self.sequencers = [RubySequencer(version = i, # I/D cache is combined and grab from ctrl - icache = self.controllers[i].cacheMemory, dcache = self.controllers[i].cacheMemory, clk_domain = self.clk_domain, ) for i in range(num_testers)] diff --git a/configs/ruby/AMD_Base_Constructor.py b/configs/ruby/AMD_Base_Constructor.py index a347f43..6f13c1e 100644 --- a/configs/ruby/AMD_Base_Constructor.py +++ b/configs/ruby/AMD_Base_Constructor.py @@ -78,7 +78,6 @@ self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() -self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -86,7 +85,6 @@ self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() -self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py index 58711ea..6705fc1 100644 --- a/configs/ruby/GPU_RfO.py +++ b/configs/ruby/GPU_RfO.py @@ -118,7 +118,6 @@ self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() -self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -126,7 +125,6 @@ self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() -self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: sequencer callback for unique writes
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31269 )
Change subject: mem-ruby: sequencer callback for unique writes
..
mem-ruby: sequencer callback for unique writes
A controller may complete a write without obtaining a full copy of
the line. This patch adds a specific callback for this purpose that
prevents reads to be coalesced with a write on a potentially incomplete
line.
Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index adbe06e..cb24d3a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -129,6 +129,7 @@
void writeCallback(Addr, DataBlock, bool, MachineType);
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ void writeUniqueCallback(Addr, DataBlock);
// ll/sc support
void writeCallbackScFail(Addr, DataBlock);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index b6b1ae3..d7c3e15 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -340,7 +340,8 @@
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime)
+ const Cycles firstResponseTime,
+ const bool noCoales)
{
//
// Free the whole list as we assume we have had the exclusive access
@@ -358,6 +359,15 @@
int aliased_loads = 0;
while (!seq_req_list.empty()) {
SequencerRequest _req = seq_req_list.front();
+
+if (noCoales && !ruby_request) {
+// Do not process follow-up requests
+// (e.g. if full line no present)
+// Reissue to the cache hierarchy
+issueRequest(seq_req.pkt, seq_req.m_second_type);
+break;
+}
+
if (ruby_request) {
assert(seq_req.m_type != RubyRequestType_LD);
assert(seq_req.m_type != RubyRequestType_Load_Linked);
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 594b4f7..b4da03f 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -103,7 +103,15 @@
const MachineType mach = MachineType_NUM,
const Cycles initialRequestTime = Cycles(0),
const Cycles forwardRequestTime = Cycles(0),
- const Cycles firstResponseTime = Cycles(0));
+ const Cycles firstResponseTime = Cycles(0),
+ const bool noCoales = false);
+
+// Write callback that prevents coalescing
+void writeUniqueCallback(Addr address, DataBlock& data)
+{
+writeCallback(address, data, true, MachineType_NUM, Cycles(0),
+ Cycles(0), Cycles(0), true);
+}
void readCallback(Addr address,
DataBlock& data,
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: able to define resource stalls handlers
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31265 )
Change subject: mem-ruby: able to define resource stalls handlers
..
mem-ruby: able to define resource stalls handlers
Input ports can specify a custom handler that is called
on resource stalls. The handler should return 'true' to
indicate the stall was handled and new messages from that
queue can be processed on that cycle. When it returns
'false' or no handler is defined, a resource stall is
generated.
Change-Id: I3481d130d5eb411e6760a54d098d3da5de511c86
Signed-off-by: Tiago Mück
---
M src/mem/slicc/ast/FuncCallExprAST.py
M src/mem/slicc/ast/InPortDeclAST.py
2 files changed, 66 insertions(+), 5 deletions(-)
diff --git a/src/mem/slicc/ast/FuncCallExprAST.py
b/src/mem/slicc/ast/FuncCallExprAST.py
index b3cc9f1..b5ef38c 100644
--- a/src/mem/slicc/ast/FuncCallExprAST.py
+++ b/src/mem/slicc/ast/FuncCallExprAST.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# Copyright (c) 2013 Advanced Micro Devices, Inc.
@@ -148,18 +160,53 @@
TransitionResult result = doTransition(${{cvec[0]}}, ${{cvec[1]}});
''')
+curr_in_port = machine.curr_in_port_code_gen
+assert(curr_in_port != None)
+
code('''
if (result == TransitionResult_Valid) {
counter++;
continue; // Check the first port again
-}
-
-if (result == TransitionResult_ResourceStall ||
-result == TransitionResult_ProtocolStall) {
+} else if (result == TransitionResult_ResourceStall) {
+''')
+if 'rsc_stall_handler' in curr_in_port.pairs:
+stall_func_name = curr_in_port.pairs['rsc_stall_handler']
+code('''
+if (${{stall_func_name}}()) {
+counter++;
+continue; // Check the first port again
+} else {
+scheduleEvent(Cycles(1));
+// Cannot do anything with this transition, go check next
doable transition (mostly likely of next port)
+}
+''')
+else:
+code('''
scheduleEvent(Cycles(1));
-
// Cannot do anything with this transition, go check next doable
transition (mostly likely of next port)
+''')
+code('''
+} else if (result == TransitionResult_ProtocolStall) {
+''')
+if 'prot_stall_handler' in curr_in_port.pairs:
+stall_func_name = curr_in_port.pairs['prot_stall_handler']
+code('''
+if (${{stall_func_name}}()) {
+counter++;
+continue; // Check the first port again
+} else {
+scheduleEvent(Cycles(1));
+// Cannot do anything with this transition, go check next
doable transition (mostly likely of next port)
+}
+''')
+else:
+code('''
+scheduleEvent(Cycles(1));
+// Cannot do anything with this transition, go check next doable
transition (mostly likely of next port)
+''')
+code('''
}
+
}
''')
elif self.proc_name == "error":
diff --git a/src/mem/slicc/ast/InPortDeclAST.py
b/src/mem/slicc/ast/InPortDeclAST.py
index e0aa252..a3fdd5e 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -118,7 +130,9 @@
rcode = self.slicc.codeFormatter()
rcode.indent()
rcode.indent()
+
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Expose MessageBuffer methods
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31271 )
Change subject: mem-ruby: Expose MessageBuffer methods
..
mem-ruby: Expose MessageBuffer methods
SLICC interface for checking the capacity of MessageBuffers
Change-Id: I28e2d22a405d33fcbe6a183dffc31bd936fa26c4
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index cb24d3a..86895fc 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -48,7 +48,11 @@
// undefined declaration error.
//
-external_type(MessageBuffer, buffer="yes", inport="yes", outport="yes");
+structure(MessageBuffer, buffer="yes", inport="yes", outport="yes",
external = "yes", primitive="yes") {
+ bool areNSlotsAvailable(int n, Tick curTime);
+ int getSize(Tick curTime);
+}
+
external_type(Scalar, primitive="yes");
structure(OutPort, external = "yes", primitive="yes") {
--
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Gerrit-Change-Number: 31271
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MessageBuffer capacity check
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31254 ) Change subject: mem-ruby: MessageBuffer capacity check .. mem-ruby: MessageBuffer capacity check Trip assert if call enqueue on a full message buffer. Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Signed-off-by: Tiago Mück --- M src/mem/ruby/network/MessageBuffer.cc 1 file changed, 3 insertions(+), 0 deletions(-) diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc index 3db8515..fb1d734 100644 --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -225,6 +225,9 @@ // Increment the number of messages statistic m_buf_msgs++; +assert((m_max_size == 0) || + ((m_prio_heap.size() + m_stall_map_size) <= m_max_size)); + DPRINTF(RubyQueue, "Enqueue arrival_time: %lld, Message: %s\n", arrival_time, *(message.get())); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31254 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Gerrit-Change-Number: 31254 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: missing method in NetDest interface
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31262 ) Change subject: mem-ruby: missing method in NetDest interface .. mem-ruby: missing method in NetDest interface Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Signed-off-by: Tiago Mück --- M src/mem/ruby/protocol/RubySlicc_Types.sm 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm index 71716f9..adbe06e 100644 --- a/src/mem/ruby/protocol/RubySlicc_Types.sm +++ b/src/mem/ruby/protocol/RubySlicc_Types.sm @@ -111,6 +111,7 @@ bool isEmpty(); bool intersectionIsEmpty(Set); bool intersectionIsEmpty(NetDest); + MachineID smallestElement(); MachineID smallestElement(MachineType); NetDest OR(NetDest); NetDest AND(NetDest); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31262 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Gerrit-Change-Number: 31262 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: TBE table supports multiple entries
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31261 )
Change subject: mem-ruby: TBE table supports multiple entries
..
mem-ruby: TBE table supports multiple entries
allocateNext allows a new TBE to be allocated for the same address
before deallocating the current one. New entries are visible and
returned by lookup after the previous one is deallocated.
Change-Id: Ia97b1b328e1fa23b300b38402bdf381ee48b6ec7
Signed-off-by: Tiago Mück
---
M src/mem/ruby/structures/TBETable.hh
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/src/mem/ruby/structures/TBETable.hh
b/src/mem/ruby/structures/TBETable.hh
index b4a723b..1505743 100644
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -42,6 +42,7 @@
#define __MEM_RUBY_STRUCTURES_TBETABLE_HH__
#include
+#include
#include
#include "mem/ruby/common/Address.hh"
@@ -51,17 +52,18 @@
{
public:
TBETable(int number_of_TBEs)
-: m_number_of_TBEs(number_of_TBEs)
+: m_size(0), m_number_of_TBEs(number_of_TBEs)
{
}
bool isPresent(Addr address) const;
+ENTRY* allocateNext(Addr address);
void allocate(Addr address);
void deallocate(Addr address);
bool
areNSlotsAvailable(int n, Tick current_time) const
{
-return (m_number_of_TBEs - m_map.size()) >= n;
+return (m_number_of_TBEs - m_size) >= n;
}
ENTRY *getNullEntry();
@@ -76,7 +78,8 @@
TBETable& operator=(const TBETable& obj);
// Data Members (m_prefix)
-std::unordered_map m_map;
+int m_size;
+std::unordered_map> m_map;
private:
int m_number_of_TBEs;
@@ -96,8 +99,8 @@
TBETable::isPresent(Addr address) const
{
assert(address == makeLineAddress(address));
-assert(m_map.size() <= m_number_of_TBEs);
-return !!m_map.count(address);
+assert(m_size <= m_number_of_TBEs);
+return m_map.count(address) > 0;
}
template
@@ -105,8 +108,17 @@
TBETable::allocate(Addr address)
{
assert(!isPresent(address));
-assert(m_map.size() < m_number_of_TBEs);
-m_map[address] = ENTRY();
+allocateNext(address);
+}
+
+template
+inline ENTRY*
+TBETable::allocateNext(Addr address)
+{
+assert(m_size < m_number_of_TBEs);
+m_map[address].emplace();
+++m_size;
+return &(m_map[address].back());
}
template
@@ -114,8 +126,12 @@
TBETable::deallocate(Addr address)
{
assert(isPresent(address));
-assert(m_map.size() > 0);
-m_map.erase(address);
+assert(m_size > 0);
+auto iter = m_map.find(address);
+iter->second.pop();
+if (iter->second.empty())
+ m_map.erase(iter);
+--m_size;
}
template
@@ -130,7 +146,8 @@
inline ENTRY*
TBETable::lookup(Addr address)
{
- if (m_map.find(address) != m_map.end()) return
&(m_map.find(address)->second);
+ if (m_map.find(address) != m_map.end())
+return &(m_map.find(address)->second.front());
return NULL;
}
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Network can use custom data msg size
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31256 )
Change subject: mem-ruby: Network can use custom data msg size
..
mem-ruby: Network can use custom data msg size
The size for network data messages can be set using a configuration
parameter. This is necessary so line transfers may be split in multiple
messages at the protocol level.
Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Signed-off-by: Tiago Mück
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.py
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/network/Network.cc
b/src/mem/ruby/network/Network.cc
index ba847e5..2f3a8a0 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -152,7 +152,9 @@
void
Network::init()
{
-m_data_msg_size = RubySystem::getBlockSizeBytes() + m_control_msg_size;
+fatal_if(params()->data_msg_size > RubySystem::getBlockSizeBytes(),
+ "Invalid network data message size");
+m_data_msg_size = params()->data_msg_size + m_control_msg_size;
}
uint32_t
diff --git a/src/mem/ruby/network/Network.py
b/src/mem/ruby/network/Network.py
index 5acad60..4e6ed25 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
+from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject
from m5.objects.BasicLink import BasicLink
@@ -51,3 +52,8 @@
slave = VectorSlavePort("CPU slave port")
master = VectorMasterPort("CPU master port")
+
+data_msg_size = Param.Int(Parent.block_size_bytes,
+"Size of data messages. Defaults to the
parent "
+"RubySystem cache line size.")
+
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added %(mod) operator to SLICC
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31260 )
Change subject: mem-ruby: added %(mod) operator to SLICC
..
mem-ruby: added %(mod) operator to SLICC
Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Signed-off-by: Tiago Mück
---
M src/mem/slicc/ast/OperatorExprAST.py
M src/mem/slicc/parser.py
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mem/slicc/ast/OperatorExprAST.py
b/src/mem/slicc/ast/OperatorExprAST.py
index 7752e9c..cab1369 100644
--- a/src/mem/slicc/ast/OperatorExprAST.py
+++ b/src/mem/slicc/ast/OperatorExprAST.py
@@ -64,7 +64,7 @@
elif self.op in ("<<", ">>"):
expected_types = [("int", "int", "int"),
("Cycles", "int", "Cycles")]
-elif self.op in ("+", "-", "*", "/"):
+elif self.op in ("+", "-", "*", "/", "%"):
expected_types = [("int", "int", "int"),
("Cycles", "Cycles", "Cycles"),
("Tick", "Tick", "Tick"),
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 721ca58..51a68d0 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -140,7 +140,7 @@
tokens = [ 'EQ', 'NE', 'LT', 'GT', 'LE', 'GE',
'LEFTSHIFT', 'RIGHTSHIFT',
'NOT', 'AND', 'OR',
- 'PLUS', 'DASH', 'STAR', 'SLASH',
+ 'PLUS', 'DASH', 'STAR', 'SLASH', 'MOD',
'INCR', 'DECR',
'DOUBLE_COLON', 'SEMI',
'ASSIGN', 'DOT',
@@ -165,6 +165,7 @@
t_AMP = r'&'
t_CONST = r'const'
t_SLASH = r'/'
+t_MOD = r'%'
t_DOUBLE_COLON = r'::'
t_SEMI = r';'
t_ASSIGN = r':='
@@ -180,7 +181,7 @@
('left', 'LT', 'GT', 'LE', 'GE'),
('left', 'RIGHTSHIFT', 'LEFTSHIFT'),
('left', 'PLUS', 'DASH'),
-('left', 'STAR', 'SLASH'),
+('left', 'STAR', 'SLASH', 'MOD'),
('right', 'NOT', 'UMINUS'),
)
@@ -718,6 +719,7 @@
def p_expr__binary_op(self, p):
"""expr : expr STAR expr
| expr SLASH expr
+| expr MOD expr
| expr PLUS expr
| expr DASH expr
| expr LTexpr
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Additional TBE table methods
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31272 )
Change subject: mem-ruby: Additional TBE table methods
..
mem-ruby: Additional TBE table methods
Allows checking the capacity and current size of the TBE table
Change-Id: I2f9bdfb50e2cee19d7fd8ea9c62d1dc8307b58e6
Signed-off-by: Tiago Mück
---
M src/mem/ruby/structures/TBETable.hh
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/structures/TBETable.hh
b/src/mem/ruby/structures/TBETable.hh
index 1505743..7419c58 100644
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -72,6 +72,10 @@
// Print cache contents
void print(std::ostream& out) const;
+int size() const { return m_size; }
+
+int capacity() const { return m_number_of_TBEs; }
+
private:
// Private copy constructor and assignment operator
TBETable(const TBETable& obj);
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: move AddrRange propagation to RubyPort
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31268 )
Change subject: mem-ruby: move AddrRange propagation to RubyPort
..
mem-ruby: move AddrRange propagation to RubyPort
Doing the master address range notification from the RubyPort.
This allows us the DMASequencer to be replaced by Sequencer in future
protocols.
Change-Id: I95edb54b39a8adf0cac5caf2b58e4a2efb573f56
Signed-off-by: Tiago Mück
---
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/RubyPort.cc
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/system/DMASequencer.cc
b/src/mem/ruby/system/DMASequencer.cc
index bad49c9..4c61dd2 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -56,9 +56,6 @@
{
RubyPort::init();
m_data_block_mask = mask(RubySystem::getBlockSizeBits());
-
-for (const auto _port : slave_ports)
-s_port->sendRangeChange();
}
RequestStatus
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 0526e65..0a713b0 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -85,6 +85,8 @@
{
assert(m_controller != NULL);
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
+for (const auto _port : slave_ports)
+s_port->sendRangeChange();
}
Port &
--
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove support for checking out as a mercurial repo.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31174 ) Change subject: misc: Remove support for checking out as a mercurial repo. .. misc: Remove support for checking out as a mercurial repo. This will still be technically possible with the right converters, but this removes the tags, ignore file, and style checking hooks related to mercurial. We no longer maintain a mercurial mirror of the main git repository, and this support adds clutter and could diverge from the git style hooks, etc, over time. Change-Id: Icf4833c4f0fda51ea98989d1d741432ae3ddc6dd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31174 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Gabe Black Maintainer: Andreas Sandberg Tested-by: kokoro --- D .hgignore D .hgtags M site_scons/site_tools/default.py D site_scons/site_tools/mercurial.py D util/hgfilesize.py D util/hgstyle.py M util/style.py M util/style/file_types.py M util/style/repo.py M util/style/style.py 10 files changed, 1 insertion(+), 507 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/.hgignore b/.hgignore deleted file mode 100644 index 03dead6..000 --- a/.hgignore +++ /dev/null @@ -1,17 +0,0 @@ -syntax: glob -build -parser.out -parsetab.py -cscope.files -cscope.out -*.pyc -*~ -.*.swp -m5out -src/doxygen -ext/dramsim2/DRAMSim2 -ext/mcpat/regression/*/*.out -util/m5/*.o -util/m5/*.a -util/m5/m5 -system/arm/dt/*.dtb diff --git a/.hgtags b/.hgtags deleted file mode 100644 index 124eac9..000 --- a/.hgtags +++ /dev/null @@ -1,30 +0,0 @@ -6b99127531fd692ff0f202e327d0826ed2bfcf5f m5_1.0_beta1 -1a40e60270c11ec24f11c783e70367e2740cdc56 m5_1.0_beta1 -069849384988e553b6edae71ecaf1fb6e918d738 m5_1.0_beta2 -4cfa92eca35d532b339507f1c631e1986d87b258 m5_1.0_tutorial -ffe1942d845c67fb3fd04692420c9433638eba13 m5_1.0_web -af8bf5e4e85ba1a773183cc3f6c43bcdf0ce146a m5_1.1 -1c0eeb0dae9b6a2a5479faf3ab52fb1ed0ce703f m5_1.1 -c486924ed90eb6805e8cf44ddee5ad5435c79051 m5_1.1 -01e679b66ca9474f10f8f96d391693adf76fc73a m5_1.1 -2608cd7def85c9fdc84251295c8023fab990d530 m5_1.1 -cdd48642d9bf584bd445b40abec9e7f934a5900b m5_1.1 -8d690c7c2efced99f7991b7ace56d769bae7cfdd m5_2.0_beta1 -d83885ad2b41777c97b94882aa8f07e761e55ac1 m5_2.0_beta1_patch1 -1906dcace7c27b2153bfb95ca1218660e1cc1f70 m5_2.0_beta2 -b174ae14f007ba0c341f8df77d36f57f48369cc8 m5_2.0_beta2 -91a9ac67662aa3a79315ade29b17a85961fecd88 m5_2.0_beta3 -dce5a8655829b7d2e24ce40cafc9c8873a71671f m5_2.0_beta5 -1ac44b6c87ec71a8410c9a9c219269eca71f8077 m5_2.0_beta4 -60a931b03fb165807f02b4f7d0fd705a67a9 copyright_update -d8b246a665c160a31751b4091f097022cde16dd7 m5_2.0_beta6 -5de565c4b7bdf46670611858b709c1eb50ad7c5c Calvin_Submission -549b72de8f725bd411a9c73ee0d15ccbdf47bb0f stable_2012_02_02 -f75ee4849c404a0c7d93413f443cec640b721f2f stable_2012_06_28 -07352f119e489452b3c0bbf6d4f70e21e80e17e3 stable_2013_06_16 -6a043adb1e8d67fbb03ac5cee58dd26f75663714 stable_2013_10_14 -459491344fcf7f9e29250e71f33a7c7150f54d64 stable_2014_02_15 -cb2e6950956d475da97b04c41f19769ce2e8541a stable_2014_08_26 -bdb307e8be54a5808a9af2537e9261d88de6ed1b stable_2014_12_14 -e1794974515011f81f8d0fda7543ba3360a12c9b stable_2015_04_15 -60eb3fef9c2d51cf98cdb5501ee0c4ac0efe6eae stable_2015_09_03 diff --git a/site_scons/site_tools/default.py b/site_scons/site_tools/default.py index 08736f0..8e8e863 100644 --- a/site_scons/site_tools/default.py +++ b/site_scons/site_tools/default.py @@ -80,7 +80,6 @@ gem5_tool_list = [ 'git', -'mercurial', ] def generate(env): diff --git a/site_scons/site_tools/mercurial.py b/site_scons/site_tools/mercurial.py deleted file mode 100644 index 3c91b38..000 --- a/site_scons/site_tools/mercurial.py +++ /dev/null @@ -1,147 +0,0 @@ -# Copyright (c) 2013, 2015-2017 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Copyright (c) 2011 Advanced Micro Devices, Inc. -# Copyright (c) 2009 The Hewlett-Packard Development Company -# Copyright (c) 2004-2005 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: support for template types in structs
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31264 )
Change subject: mem-ruby: support for template types in structs
..
mem-ruby: support for template types in structs
Templated types can now be used within structures defined in SLICC.
Usage is similar to the TBETable: the templated type must have all
possible methods in it's SLICC definition. Eg.:
structure(Map, desc="Template map definition") {
MachineID lookup(Addr);
MachineID lookup(int);
}
structure(SomeType, desc="Some other struct definition") {
MachineID addrMap, template="";
MachineID intMap, template="";
}
Change-Id: I02a621cea5e4a89302762334651c6534c6574e9d
Signed-off-by: Tiago Mück
---
M src/mem/slicc/symbols/Type.py
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index fa5e79a..ee319cb 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -37,6 +49,9 @@
super(DataMember, self).__init__(symtab, ident, location, type,
code, pairs, machine)
self.init_code = init_code
+self.real_c_type = self.type.c_ident
+if "template" in pairs:
+self.real_c_type += pairs["template"]
class Enumeration(PairContainer):
def __init__(self, ident, pairs):
@@ -235,8 +250,9 @@
code('m_$ident = ${{dm["default"]}}; // default for
this field')
elif "default" in dm.type:
# Look for the type default
-tid = dm.type.c_ident
-code('m_$ident = ${{dm.type["default"]}}; // default
value of $tid')
+tid = dm.real_c_type
+code('m_$ident = ${{dm.type["default"]}};')
+code(' // default value of $tid')
else:
code('// m_$ident has no default')
code.dedent()
@@ -268,7 +284,7 @@
# Full init constructor
if not self.isGlobal:
-params = [ 'const %s& local_%s' % (dm.type.c_ident, dm.ident) \
+params = [ 'const %s& local_%s' % (dm.real_c_type, dm.ident) \
for dm in self.data_members.values() ]
params = ', '.join(params)
@@ -318,7 +334,7 @@
/** \\brief Const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-const ${{dm.type.c_ident}}&
+const ${{dm.real_c_type}}&
get${{dm.ident}}() const
{
return m_${{dm.ident}};
@@ -332,7 +348,7 @@
/** \\brief Non-const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-${{dm.type.c_ident}}&
+${{dm.real_c_type}}&
get${{dm.ident}}()
{
return m_${{dm.ident}};
@@ -345,7 +361,7 @@
code('''
/** \\brief Mutator method for ${{dm.ident}} field */
void
-set${{dm.ident}}(const ${{dm.type.c_ident}}& local_${{dm.ident}})
+set${{dm.ident}}(const ${{dm.real_c_type}}& local_${{dm.ident}})
{
m_${{dm.ident}} = local_${{dm.ident}};
}
@@ -375,7 +391,7 @@
if "desc" in dm:
code('/** ${{dm["desc"]}} */')
-code('$const${{dm.type.c_ident}} m_${{dm.ident}}$init;')
+code('$const${{dm.real_c_type}} m_${{dm.ident}}$init;')
# Prototypes for methods defined for the Type
for item in self.methods:
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I02a621cea5e4a89302762334651c6534c6574e9d
Gerrit-Change-Number: 31264
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: int to Cycle converter
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31266 )
Change subject: mem-ruby: int to Cycle converter
..
mem-ruby: int to Cycle converter
Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index f509d09..b8b005a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -32,6 +32,7 @@
void error(std::string msg);
void assert(bool condition);
Cycles zero_time();
+Cycles intToCycles(int c);
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index e3d4f0b..eec598a 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -46,6 +46,8 @@
inline Cycles zero_time() { return Cycles(0); }
+inline Cycles intToCycles(int c) { return Cycles(c); }
+
inline NodeID
intToID(int nodenum)
{
--
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Gerrit-Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add addressOffset util
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31270 )
Change subject: mem-ruby: add addressOffset util
..
mem-ruby: add addressOffset util
Returns the offset of an address with respect to a base address.
Looks unnecessary, but SLICC doesn't support casting and the '-'
operator for Addr types, so the alternative to this would be to add
more some helpers like 'addrToUint64' and 'uint64ToInt'.
Change-Id: I90480cec4c8b2e6bb9706f8b94ed33abe3c93e78
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index b8b005a..70648ec 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -37,6 +37,7 @@
int IDToInt(NodeID id);
int addressToInt(Addr addr);
Addr intToAddress(int addr);
+int addressOffset(Addr addr, Addr base);
int max_tokens();
Addr makeLineAddress(Addr addr);
int getOffset(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index eec598a..d805e8f 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -87,6 +99,15 @@
return 1024;
}
+inline int
+addressOffset(Addr addr, Addr base)
+{
+assert(addr >= base);
+Addr offset = addr - base;
+assert(!(offset & 0x));
+return offset;
+}
+
/**
* This function accepts an address, a data block and a packet. If the
address
* range for the data block contains the address which the packet needs to
--
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: enable kernel-end WB functionality
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29938 )
Change subject: gpu-compute: enable kernel-end WB functionality
..
gpu-compute: enable kernel-end WB functionality
Change-Id: Ib17e1d700586d1aa04d408e7b924270f0de82efe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29938
Maintainer: Anthony Gutierrez
Tested-by: kokoro
Reviewed-by: Xianwei Zhang
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/shader.cc
M src/mem/request.hh
3 files changed, 27 insertions(+), 18 deletions(-)
Approvals:
Xianwei Zhang: Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index b0616d6..178fd6e 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1218,23 +1218,25 @@
schedule(mem_req_event, curTick() + req_tick_latency);
} else {
-assert(gpuDynInst->isEndOfKernel());
+ // kernel end release must be enabled
+ assert(shader->impl_kern_end_rel);
+ assert(gpuDynInst->isEndOfKernel());
-req->setCacheCoherenceFlags(Request::RELEASE);
-req->setReqInstSeqNum(gpuDynInst->seqNum());
-req->setFlags(Request::KERNEL);
-pkt = new Packet(req, MemCmd::MemSyncReq);
-pkt->pushSenderState(
- new ComputeUnit::DataPort::SenderState(gpuDynInst, 0,
nullptr));
+ req->setCacheCoherenceFlags(Request::WB_L2);
+ req->setReqInstSeqNum(gpuDynInst->seqNum());
+ req->setFlags(Request::KERNEL);
+ pkt = new Packet(req, MemCmd::MemSyncReq);
+ pkt->pushSenderState(
+ new ComputeUnit::DataPort::SenderState(gpuDynInst, 0,
nullptr));
-EventFunctionWrapper *mem_req_event =
- memPort[0]->createMemReqEvent(pkt);
+ EventFunctionWrapper *mem_req_event =
+memPort[0]->createMemReqEvent(pkt);
-DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x
scheduling "
-"a release\n", cu_id, gpuDynInst->simdId,
-gpuDynInst->wfSlotId, 0, pkt->req->getPaddr());
+ DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x
scheduling "
+ "a release\n", cu_id, gpuDynInst->simdId,
+ gpuDynInst->wfSlotId, 0, pkt->req->getPaddr());
-schedule(mem_req_event, curTick() + req_tick_latency);
+ schedule(mem_req_event, curTick() + req_tick_latency);
}
} else {
gpuDynInst->setRequestFlags(req);
diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index f5e9444..59ce239 100644
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -223,11 +223,11 @@
// flush has never been started, performed only once at kernel end
assert(_dispatcher.getOutstandingWbs(kernId) == 0);
-// iterate all cus, managed by the shader, to perform flush.
-for (int i_cu = 0; i_cu < n_cu; ++i_cu) {
-_dispatcher.updateWbCounter(kernId, +1);
-cuList[i_cu]->doFlush(gpuDynInst);
-}
+// the first cu, managed by the shader, performs flush operation,
+// assuming that L2 cache is shared by all cus in the shader
+int i_cu = 0;
+_dispatcher.updateWbCounter(kernId, +1);
+cuList[i_cu]->doFlush(gpuDynInst);
}
bool
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 4e0ba97..718d5fa 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -225,6 +225,9 @@
* See the AMD GCN3 ISA Architecture Manual for more
* details.
*
+ * INV_L1: L1 cache invalidation
+ * WB_L2: L2 cache writeback
+ *
* SLC: System Level Coherent. Accesses are forced to miss in
* the L2 cache and are coherent with system memory.
*
@@ -237,6 +240,10 @@
* between atomic return/no-return operations.
*/
enum : CacheCoherenceFlagsType {
+/** mem_sync_op flags */
+INV_L1 = 0x0001,
+WB_L2 = 0x0020,
+/** user-policy flags */
/** user-policy flags */
SLC_BIT = 0x0080,
GLC_BIT = 0x0100,
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ib17e1d700586d1aa04d408e7b924270f0de82efe
Gerrit-Change-Number: 29938
Gerrit-PatchSet: 9
Gerrit-Owner: Anthony Gutierrez
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Tony Gutierrez
Gerrit-Reviewer: Tuan Ta
Gerrit-Reviewer: Xianwei Zhang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Implementation of flat atomic swap instruction
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/29937 )
Change subject: arch-gcn3: Implementation of flat atomic swap instruction
..
arch-gcn3: Implementation of flat atomic swap instruction
Change-Id: I9b9042899e65e8c9848b31c509eb2e3b13293e52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29937
Maintainer: Anthony Gutierrez
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/gcn3/insts/instructions.cc
M src/arch/gcn3/insts/instructions.hh
2 files changed, 78 insertions(+), 4 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 2e39bf5..607e3c6 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -39231,8 +39231,80 @@
void
Inst_FLAT__FLAT_ATOMIC_SWAP::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
-}
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (wf->execMask().none()) {
+wf->wrGmReqsInPipe--;
+wf->rdGmReqsInPipe--;
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->exec_mask = wf->execMask();
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+addr.read();
+
+calcAddr(gpuDynInst, addr);
+
+if (gpuDynInst->executedAs() == Enums::SC_GLOBAL ||
+gpuDynInst->executedAs() == Enums::SC_PRIVATE) {
+// TODO: additional address computation required for scratch
+panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE,
+ "Flats to private aperture not tested yet\n");
+gpuDynInst->computeUnit()->globalMemoryPipe.
+issueRequest(gpuDynInst);
+wf->wrGmReqsInPipe--;
+wf->outstandingReqsWrGm++;
+wf->rdGmReqsInPipe--;
+wf->outstandingReqsRdGm++;
+} else {
+fatal("Non global flat instructions not implemented yet.\n");
+}
+
+gpuDynInst->wavefront()->outstandingReqs++;
+gpuDynInst->wavefront()->validateRequestCounters();
+
+ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+
+data.read();
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+} // execute
+
+void
+Inst_FLAT__FLAT_ATOMIC_SWAP::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+initAtomicAccess(gpuDynInst);
+} // initiateAcc
+
+void
+Inst_FLAT__FLAT_ATOMIC_SWAP::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+if (isAtomicRet()) {
+VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] = (reinterpret_cast(
+gpuDynInst->d_data))[lane];
+}
+}
+
+vdst.write();
+}
+} // completeAcc
+
+// --- Inst_FLAT__FLAT_ATOMIC_CMPSWAP class methods ---
Inst_FLAT__FLAT_ATOMIC_CMPSWAP
::Inst_FLAT__FLAT_ATOMIC_CMPSWAP(InFmt_FLAT *iFmt)
diff --git a/src/arch/gcn3/insts/instructions.hh
b/src/arch/gcn3/insts/instructions.hh
index ff0cfea..b0cc37e 100644
--- a/src/arch/gcn3/insts/instructions.hh
+++ b/src/arch/gcn3/insts/instructions.hh
@@ -79949,9 +79949,9 @@
case 0: //vgpr_addr
return 8;
case 1: //vgpr_src
-return 32;
+return 4;
case 2: //vgpr_dst
-return 32;
+return 4;
default:
fatal("op idx %i out of bounds\n", opIdx);
return -1;
@@ -79991,6 +79991,8 @@
} // isDstOperand
void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+void completeAcc(GPUDynInstPtr) override;
}; // Inst_FLAT__FLAT_ATOMIC_SWAP
class Inst_FLAT__FLAT_ATOMIC_CMPSWAP : public Inst_FLAT
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9b9042899e65e8c9848b31c509eb2e3b13293e52
Gerrit-Change-Number: 29937
Gerrit-PatchSet: 9
Gerrit-Owner: Anthony Gutierrez
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Anthony Gutierrez
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: allow qualifiers in SLICC functions
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31259 )
Change subject: mem-ruby: allow qualifiers in SLICC functions
..
mem-ruby: allow qualifiers in SLICC functions
All parameters in functions defined within SLICC are const& by default
(except for the implicit types, e.g. TBE). This allow us to specify
if we want to pass parameters as & or const&. Default behavior is
maintained.
A use case is to allow refactoring of common code in actions that
enqueue messages. Messages can be passed as a non-const ref. to
to functions with common initialization. E.g.:
void initRequestMsg(RequestMsg & out_msg) {
// Common msg init code
}
action(sendRequest1, ...) {
enqueue(...) {
initRequestMsg(out_msg);
// Request1 specific code
}
}
action(sendRequest2, ...) {
enqueue(...) {
initRequestMsg(out_msg);
// Request2 specific code
}
}
Change-Id: Ic6a18169a661b3e36710b2a9f8a0e6bc5fce40f8
Signed-off-by: Tiago Mück
---
M src/mem/slicc/ast/FormalParamAST.py
M src/mem/slicc/parser.py
2 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/src/mem/slicc/ast/FormalParamAST.py
b/src/mem/slicc/ast/FormalParamAST.py
index 778b5c1..57f5c94 100644
--- a/src/mem/slicc/ast/FormalParamAST.py
+++ b/src/mem/slicc/ast/FormalParamAST.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -29,12 +41,12 @@
from slicc.symbols import Var
class FormalParamAST(AST):
-def __init__(self, slicc, type_ast, ident, default = None, pointer =
False):
+def __init__(self, slicc, type_ast, ident, default = None,
qualifier=""):
super(FormalParamAST, self).__init__(slicc)
self.type_ast = type_ast
self.ident = ident
self.default = default
-self.pointer = pointer
+self.qualifier = qualifier
def __repr__(self):
return "[FormalParamAST: %s]" % self.ident
@@ -52,11 +64,26 @@
self.pairs)
self.symtab.newSymbol(v)
-if self.pointer or str(type) == "TBE" or (
-# Check whether type is entry by checking the interface since
-# in protocol files, entries use AbstractCacheEntry as interfaces.
+# Qualifier is always a pointer for TBE table and Cache entries.
+# It's expected to be left unspecified or specified as ptr.
+qualifier = self.qualifier
+if str(type) == "TBE" or (
"interface" in type and (
type["interface"] == "AbstractCacheEntry")):
+if qualifier not in ["", "PTR"] :
+self.warning("Parameter \'%s\' is always pointer. "
+ "%s qualifier ignored" % (self.ident,
qualifier))
+qualifier = "PTR"
+
+# default
+if qualifier == "":
+qualifier = "CONST_REF"
+
+if qualifier == "PTR":
return type, "%s* %s" % (type.c_ident, param)
-else:
+elif qualifier == "REF":
+return type, "%s& %s" % (type.c_ident, param)
+elif qualifier == "CONST_REF":
return type, "const %s& %s" % (type.c_ident, param)
+else:
+self.error("Invalid qualifier for param \'%s\'" % self.ident)
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 643eec6..721ca58 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 The Hewlett-Packard Development Company
# Copyright (c) 2017 Google Inc.
# All rights reserved.
@@ -132,7 +144,8 @@
'INCR', 'DECR',
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow same-cycle enqueue
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31255 )
Change subject: mem-ruby: Allow same-cycle enqueue
..
mem-ruby: Allow same-cycle enqueue
Messages may be enqueued and be ready in the same cycle.
Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Signed-off-by: Tiago Mück
---
M src/mem/ruby/network/MessageBuffer.cc
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index fb1d734..f2c952e 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -172,7 +172,6 @@
// Calculate the arrival time of the message, that is, the first
// cycle the message can be dequeued.
-assert(delta > 0);
Tick arrival_time = 0;
// random delays are inserted if either RubySystem level randomization
flag
@@ -193,7 +192,7 @@
}
// Check the arrival time
-assert(arrival_time > current_time);
+assert(arrival_time >= current_time);
if (m_strict_fifo) {
if (arrival_time < m_last_arrival_time) {
panic("FIFO ordering violated: %s name: %s current time: %d "
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Gerrit-Change-Number: 31255
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added function to check addr range
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31263 )
Change subject: mem-ruby: added function to check addr range
..
mem-ruby: added function to check addr range
respondsTo checks if a controller address ranges includes a given
address.
Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Signed-off-by: Tiago Mück
---
M src/mem/ruby/slicc_interface/AbstractController.hh
1 file changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 750a620..5b43165 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -153,6 +153,13 @@
Stats::Histogram& getDelayVCHist(uint32_t index)
{ return *(m_delayVCHistogram[index]); }
+bool respondsTo(Addr addr)
+{
+for (auto : addrRanges)
+if (range.contains(addr)) return true;
+return false;
+}
+
/**
* Map an address to the correct MachineID
*
--
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Gerrit-Change-Number: 31263
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