[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email ) Change subject: arch-arm: Generalize SCTLR_RST behaviour .. arch-arm: Generalize SCTLR_RST behaviour This

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email ) Change subject: arch-arm: Move MISCREG init logic from ISA to reset field .. arch-arm: Move MISCREG init

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email ) Change subject: arch-arm: Map CTR_EL0 to AArch32 version .. arch-arm: Map CTR_EL0 to AArch32 version

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email ) Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset value .. arch-arm: Replace

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email ) Change subject: arch-arm: Rewrite ISA::initID32 using BitUnions .. arch-arm: Rewrite ISA::initID32 using

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email ) Change subject: arch-arm: Map MPIDR_EL1 to AArch32 version .. arch-arm: Map MPIDR_EL1 to AArch32 version

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email ) Change subject: arch-arm: Map MIDR_EL1 to AArch32 version .. arch-arm: Map MIDR_EL1 to AArch32 version

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email ) Change subject: arch-arm: Remove ISA::initID32 .. arch-arm: Remove ISA::initID32 Signed-off-by: Giacomo

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email ) Change subject: arch-arm: Fix read redirection for MIDR register .. arch-arm: Fix read redirection for

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Make MISCREGs reset value configurable

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email ) Change subject: arch-arm: Make MISCREGs reset value configurable .. arch-arm: Make MISCREGs reset value

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add missing zbkb instructions

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email ) Change subject: arch-riscv: Add missing zbkb instructions .. arch-riscv: Add missing zbkb instructions

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email ) Change subject: arch-arm: Remove clear32/64 methods .. arch-arm: Remove clear32/64 methods Change-Id:

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email ) Change subject: arch-arm: Remove ISA::initID64 .. arch-arm: Remove ISA::initID64 Signed-off-by: Giacomo

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70468?usp=email ) Change subject: arch-arm: Rewrite ISA::initID64 using BitUnions .. arch-arm: Rewrite ISA::initID64 using

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: VMPIDR_EL2 can be

[gem5-dev] Re: GEM5-GCN-DNNMark get Invalid filter channel number when running: dnnmark_test_VGG, dnnmark_test_alexnet, dnnmark_test_fwd_conv

I have not tried running these specific benchmarks in gem5 personally, so I cannot say for certain what the error is or even if they are expected to run to completion in gem5. But, normally the error you're seeing happens because you have not created the appropriate "cache" files for the GPU

[gem5-dev] GEM5-GCN-DNNMark get Invalid filter channel number when running: dnnmark_test_VGG, dnnmark_test_alexnet, dnnmark_test_fwd_conv

DearMatt, When i run the benchmarks:dnnmark_test_VGG, dnnmark_test_alexnet, dnnmark_test_fwd_conv, and i got the same error like this (get Invalid filter channel number)?? build/GCN3_X86/sim/syscall_emul.cc:74: warn: ignoring syscall fdatasync(...) build/GCN3_X86/sim/syscall_emul.cc:74:

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70358?usp=email ) Change subject: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2 .. arch-riscv: Refactor

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fc...

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70377?usp=email ) Change subject: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fcvt_d_lu .. arch-riscv:

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Treat RVC HINT as nops rather than trap

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70357?usp=email ) Change subject: arch-riscv: Treat RVC HINT as nops rather than trap .. arch-riscv: Treat RVC HINT as nops rather

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add missing zbkb instructions

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email ) Change subject: arch-riscv: Add missing zbkb instructions .. arch-riscv: Add missing zbkb instructions Add the