Hi Steve,
The 00.hello tests are below 10 seconds and have too high SNR to even make
it into my report :-), so yes you are right in that they are included in
the ‘short’ regressions.
This is definitely an intermediate step, but in any case we benefit from
having a more sensible classification.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
passed.
*
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Ship it!
Looks fine. Could you mark the issues that are fixed as fixed
changeset ae5582819481 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ae5582819481
description:
arm: Add support for filtering in the PMU
This patch adds support for filtering events in the PMU. In order to
do so, it updates the ISADevice base class
changeset 5fae03bd840a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5fae03bd840a
description:
arm: Clean up and document decoder API
This changeset adds more documentation to the ArmISA::Decoder class
and restructures it slightly to make API groups
changeset 9d0aef7a9b2e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9d0aef7a9b2e
description:
config: Add --memchecker option
This patch adds the --memchecker option, to denote that a MemChecker
should be instantiated for the system. The exact
changeset 6332c9d471a8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6332c9d471a8
description:
mem: Add MemChecker and MemCheckerMonitor
This patch adds the MemChecker and MemCheckerMonitor classes. While
MemChecker can be integrated anywhere in the
changeset da37aec3ed1a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=da37aec3ed1a
description:
mem: Add a stack distance calculator
This patch adds a stand-alone stack distance calculator. The stack
distance calculator is a passive SimObject that
changeset 3bba9f2d0c7d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3bba9f2d0c7d
description:
arm: Raise an alignment fault if a PC has illegal alignment
We currently don't handle unaligned PCs correctly. There is one check
for unaligned PCs in the
changeset 427f988fe6e5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=427f988fe6e5
description:
config: Add options to take/resume from SimPoint checkpoints
More documentation at http://gem5.org/Simpoints
Steps to profile, generate, and use
changeset 6dd27a0e0d23 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6dd27a0e0d23
description:
mem: Ensure DRAM controller is idle when in atomic mode
This patch addresses an issue seen with the KVM CPU where the refresh
events scheduled by the DRAM
changeset b9646f4546ad in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b9646f4546ad
description:
mem: Rework the structuring of the prefetchers
Re-organizes the prefetcher class structure. Previously the
BasePrefetcher forced multiple assumptions on
changeset bb665366cc00 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bb665366cc00
description:
mem: Add rank-wise refresh to the DRAM controller
This patch adds rank-wise refresh to the controller, as opposed to the
channel-wide refresh currently in
changeset 471d390943f0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=471d390943f0
description:
mem: Fix a bug in the DRAM controller arbitration
Fix a minor issue that affects multi-rank systems.
diffstat:
src/mem/dram_ctrl.cc | 12 +---
1 files
changeset b7bc5b1084a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b7bc5b1084a4
description:
arm: Add stats to table walker
This patch adds table walker stats for:
- Walk events
- Instruction vs Data
- Page size histogram
-
changeset 00965520c9f5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=00965520c9f5
description:
mem: Fix event scheduling issue for prefetches
The cache's MemSidePacketQueue schedules a sendEvent based upon
nextMSHRReadyTime() which is the time when
changeset 6d4da9dc90a1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6d4da9dc90a1
description:
tests: Add a regression for the stack distance calculator
Re-use the existing traffic generator regression, and enable the stack
distance calculation in
changeset 0b969a35781f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0b969a35781f
description:
mem: Add parameter to reserve MSHR entries for demand access
Adds a new parameter that reserves some number of MSHR entries for
demand
accesses. This
changeset 7982e539d003 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7982e539d003
description:
mem: Hide WriteInvalidate requests from prefetchers
Without this tweak, a prefetcher will happily prefetch data that will
promptly be invalidated and
changeset 74834c49fbbe in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=74834c49fbbe
description:
config: Expose the DRAM ranks as a command-line option
This patch gives the user direct influence over the number of DRAM
ranks to make it easier to tune
changeset c9b7e0c69f88 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c9b7e0c69f88
description:
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats,
changeset 63edd4a1243f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=63edd4a1243f
description:
mem: Change prefetcher to use random_mt
Prefechers has used rand() to generate random numers previously.
diffstat:
src/mem/cache/prefetch/stride.cc | 3 ++-
1
changeset 97aa1ee1c2d9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=97aa1ee1c2d9
description:
mem: Fix bug relating to writebacks and prefetches
Previously the code commented about an unhandled case where it might be
possible for a writeback to
Thanks for the clarification, Andreas. Yes, it's a good step; thanks for
doing it.
Steve
On Tue, Dec 23, 2014 at 12:55 AM, Andreas Hansson via gem5-dev
gem5-dev@gem5.org wrote:
Hi Steve,
The 00.hello tests are below 10 seconds and have too high SNR to even make
it into my report :-), so
On Dec. 22, 2014, 9:19 p.m., Steve Reinhardt wrote:
Fine with me, assuming that our implementations of those features are
indeed complete.
Gabe Black wrote:
They aren't, but I think the bits that are missing will trigger warnings.
OK, good enough. Thanks.
- Steve
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Review request for Default.
Repository: gem5
Description
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Changeset
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I think we settled on syscall_emul
- Andreas Hansson
On Dec. 23,
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