Éder F. Zulian has uploaded a new patch set (#4). (
https://gem5-review.googlesource.com/4120 )
Change subject: config, mem, hmc: fix HMC test script
..
config, mem, hmc: fix HMC test script
This patch removes parameters
Éder F. Zulian has uploaded a new patch set (#3). (
https://gem5-review.googlesource.com/4120 )
Change subject: config, mem, hmc: fix HMC test script
..
config, mem, hmc: fix HMC test script
This patch removes parameters
Éder F. Zulian has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/4120 )
Change subject: config, mem, hmc: fix HMC test script
..
config, mem, hmc: fix HMC test script
This patch removes parameters
Hi,
You don't need something extra. Just instantiate one sim_control, one slave and
one master and bind slave and master to the sim_control. That's all.
For more details have a look on the paper:
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/4140
Change subject: cpu: Add missing rename of vector registers in the O3 CPU
..
cpu: Add missing rename of vector registers in
Hi,
In GEM5-TLM, there are two separate examples for master_port and slave_port. I
am thinking to combine, so that in the same simulation we have both the
master_port as well as slave_port in the TLM world. When looking into this, I
realized we have this sim_control, to which I can either bind
Hello Jason Lowe-Power, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/4001
to look at the new patch set (#9).
Change subject: cpu, config: Add setFutureCPU to BaseCPU
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic:
FAILED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing:
FAILED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic:
FAILED!
*
