date:20180302

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove mumBlock redundant initialiation from FALRU

2018-03-02 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8281 )


Change subject: mem-cache: Remove mumBlock redundant initialiation from  
FALRU

..

mem-cache: Remove mumBlock redundant initialiation from FALRU

Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/8281
Reviewed-by: Daniel Carvalho 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/fa_lru.cc
2 files changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 2c528a9..9714d9a 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -91,7 +91,7 @@
 bool warmedUp;

 /** the number of blocks in the cache */
-unsigned numBlocks;
+const unsigned numBlocks;

 // Statistics
 /**
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index dfd4c40..1ee34b7 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -73,8 +73,6 @@
 cacheMask = 0;
 }

-numBlocks = size/blkSize;
-
 blks = new FALRUBlk[numBlocks];
 head = &(blks[0]);
 tail = &(blks[numBlocks-1]);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Gerrit-Change-Number: 8281
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: mem-cache: Remove mumBlock redundant initialiation from FALRU

2018-03-02 Thread Nikos Nikoleris (Gerrit)


Hello Gabe Black, Jason Lowe-Power, Daniel Carvalho, Curtis Dunham,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8281

to look at the new patch set (#2).

Change subject: mem-cache: Remove mumBlock redundant initialiation from  
FALRU

..

mem-cache: Remove mumBlock redundant initialiation from FALRU

Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Reviewed-by: Curtis Dunham 
---
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/fa_lru.cc
2 files changed, 1 insertion(+), 3 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Gerrit-Change-Number: 8281
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Populate whenReady for blocks filled from writebacks

2018-03-02 Thread Nikos Nikoleris (Gerrit)


Hello Gabe Black, Curtis Dunham, Giacomo Travaglini, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8285

to look at the new patch set (#2).

Change subject: mem-cache: Populate whenReady for blocks filled from  
writebacks

..

mem-cache: Populate whenReady for blocks filled from writebacks

Writebacks write data to either an existing block or a newly allocated
block. In either case we need to populate the whenReady field of the
block which will determine when the new value can be used.

Change-Id: I5788fad0b8086a1be96714639bf6a9470b334926
Reviewed-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/mem/cache/cache.cc
1 file changed, 3 insertions(+), 0 deletions(-)


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Gerrit-Branch: master
Gerrit-Change-Id: I5788fad0b8086a1be96714639bf6a9470b334926
Gerrit-Change-Number: 8285
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Adopt a more sensible cache class hierarchy

2018-03-02 Thread Nikos Nikoleris (Gerrit)


Hello Gabe Black, Jason Lowe-Power, Daniel Carvalho,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8290

to look at the new patch set (#2).

Change subject: mem-cache: Adopt a more sensible cache class hierarchy
..

mem-cache: Adopt a more sensible cache class hierarchy

This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.

This is a modified version of a changeset put together by Andreas
Hansson 

Change-Id: I56cef203728e500f74e9e7599fe307f366dfb753
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
9 files changed, 449 insertions(+), 447 deletions(-)


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Gerrit-Branch: master
Gerrit-Change-Id: I56cef203728e500f74e9e7599fe307f366dfb753
Gerrit-Change-Number: 8290
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Add a non-coherent cache

2018-03-02 Thread Nikos Nikoleris (Gerrit)


Hello Gabe Black, Jason Lowe-Power, Daniel Carvalho,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8291

to look at the new patch set (#3).

Change subject: mem-cache: Add a non-coherent cache
..

mem-cache: Add a non-coherent cache

The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.

This is a modified version of a changeset put together by Andreas
Hansson 

Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
---
M configs/example/memtest.py
M src/mem/cache/Cache.py
M src/mem/cache/SConscript
A src/mem/cache/noncoherent_cache.cc
A src/mem/cache/noncoherent_cache.hh
M src/mem/cache/queue.hh
M tests/configs/base_config.py
7 files changed, 1,522 insertions(+), 12 deletions(-)


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Gerrit-Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Gerrit-Change-Number: 8291
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Populate the secure bit when the temp block is filled

2018-03-02 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8284 )


Change subject: mem-cache: Populate the secure bit when the temp block is  
filled

..

mem-cache: Populate the secure bit when the temp block is filled

The secure bit should be set when we fill a block with data from a
secure location, as indicated by the packet that triggers the fill.
This patch fixes a bug in which the cache wouldn't populate the secure
bit when filling the temp block.

Change-Id: I95c706146449804ff42b205b25dd79750f3e882a
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/8284
Maintainer: Nikos Nikoleris 
Reviewed-by: Daniel Carvalho 
---
M src/mem/cache/cache.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 622f0f7..64438c1 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1902,7 +1902,9 @@
 blk = tempBlock;
 tempBlock->set = tags->extractSet(addr);
 tempBlock->tag = tags->extractTag(addr);
-// @todo: set security state as well...
+if (is_secure) {
+tempBlock->status |= BlkSecure;
+}
 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
 is_secure ? "s" : "ns");
 } else {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I95c706146449804ff42b205b25dd79750f3e882a
Gerrit-Change-Number: 8284
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: mem-cache: Remove unnecessary block initialization on writeback

2018-03-02 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8283 )


Change subject: mem-cache: Remove unnecessary block initialization on  
writeback

..

mem-cache: Remove unnecessary block initialization on writeback

Change-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/8283
Maintainer: Nikos Nikoleris 
Reviewed-by: Daniel Carvalho 
---
M src/mem/cache/cache.cc
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 1821f18..622f0f7 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1662,8 +1662,6 @@
 req->setFlags(Request::SECURE);

 req->taskId(blk->task_id);
-blk->task_id= ContextSwitchTaskId::Unknown;
-blk->tickInserted = curTick();

 PacketPtr pkt =
 new Packet(req, blk->isDirty() ?
@@ -1742,8 +1740,6 @@
 req->setFlags(Request::SECURE);

 req->taskId(blk->task_id);
-blk->task_id = ContextSwitchTaskId::Unknown;
-blk->tickInserted = curTick();

 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict);
 pkt->allocate();

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Gerrit-Branch: master
Gerrit-Change-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a
Gerrit-Change-Number: 8283
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: configs: Fix L3Cache instantiation in lat_mem_rd.py

2018-03-02 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8288 )


Change subject: configs: Fix L3Cache instantiation in lat_mem_rd.py
..

configs: Fix L3Cache instantiation in lat_mem_rd.py

This changeset updates the lat_mem_rd.py to configure the L3Cache
using the split tag_latency, data_latency parameters.

Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5
Reviewed-on: https://gem5-review.googlesource.com/8288
Maintainer: Nikos Nikoleris 
Reviewed-by: Daniel Carvalho 
---
M configs/dram/lat_mem_rd.py
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index ddc44e2..dc0cfcb 100644
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -264,7 +264,9 @@
 # a starting point for an L3 cache
 class L3Cache(Cache):
 assoc = 16
-hit_latency = 40
+tag_latency = 20
+data_latency = 20
+sequential_access = True
 response_latency = 40
 mshrs = 32
 tgts_per_mshr = 12

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Gerrit-Branch: master
Gerrit-Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5
Gerrit-Change-Number: 8288
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
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Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: mem-cache: Split array indexing and replacement policies.

2018-03-02 Thread Daniel Carvalho (Gerrit)


Hello Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8501

to look at the new patch set (#5).

Change subject: mem-cache: Split array indexing and replacement policies.
..

mem-cache: Split array indexing and replacement policies.

Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:

- Array indexers determine the possible locations for block allocation.
  This information is used to generate replacement candidates when
  conflicts happen.
- Replacement policies determine which of the replacement candidates
  should be evicted to make room for new allocations.

For this reason, they were split into different classes. Advantages:

- Easier and more straightforward to implement other replacement
  policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes

As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).

Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
---
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
A src/mem/cache/replacement_policies/ReplacementPolicies.py
A src/mem/cache/replacement_policies/SConscript
C src/mem/cache/replacement_policies/base.cc
A src/mem/cache/replacement_policies/base.hh
A src/mem/cache/replacement_policies/lru_rp.cc
A src/mem/cache/replacement_policies/lru_rp.hh
A src/mem/cache/replacement_policies/random_rp.cc
R src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/tags/SConscript
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
D src/mem/cache/tags/lru.cc
D src/mem/cache/tags/lru.hh
D src/mem/cache/tags/random_repl.cc
26 files changed, 590 insertions(+), 418 deletions(-)


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Gerrit-Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Gerrit-Change-Number: 8501
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Nikos Nikoleris 
Gerit-CC: Jason Lowe-Power 
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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-03-02 Thread Cron Daemon

* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
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build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
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* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
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* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
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build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
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build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
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build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
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* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
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* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
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* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: 
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build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby:
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* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby:
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build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic: 
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* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic: 
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build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby:
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* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: 
CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing: 
CHANGED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby:
 CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic: 
CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby:
 CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: 
CHANGED!
*

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove mumBlock redundant initialiation from FALRU

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove mumBlock redundant initialiation from FALRU

[gem5-dev] Change in public/gem5[master]: mem-cache: Populate whenReady for blocks filled from writebacks

[gem5-dev] Change in public/gem5[master]: mem-cache: Adopt a more sensible cache class hierarchy

[gem5-dev] Change in public/gem5[master]: mem-cache: Add a non-coherent cache

[gem5-dev] Change in public/gem5[master]: mem-cache: Populate the secure bit when the temp block is filled

[gem5-dev] Change in public/gem5[master]: mem-cache: Remove unnecessary block initialization on writeback

[gem5-dev] Change in public/gem5[master]: configs: Fix L3Cache instantiation in lat_mem_rd.py

[gem5-dev] Change in public/gem5[master]: mem-cache: Split array indexing and replacement policies.

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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