Re: [gem5-dev] register API thoughts

Hi folks. Could you please confirm you can open this document now? Some feedback would be appreciated! Gabe On Tue, Feb 5, 2019 at 5:57 PM Gabe Black wrote: > Bump > > On Fri, Feb 1, 2019 at 1:27 AM Gabe Black wrote: > >> Apparently I can't share things publicly from my work account, so

Re: [gem5-dev] Panic when trying to run SPEC2017 on GEM5

The x86 implementation has always supported SSE, and support for decoding AVX instructions was added a while ago. This particular instruction is SHLX which is part of the BMI2 instruction set which was introduced with Intel's Haswell microarchitecture (according to wikipedia) which makes it only

[gem5-dev] Change in gem5/gem5[master]: systemc: Add a systemc_home directory which maps to the ext headers.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16263 Change subject: systemc: Add a systemc_home directory which maps to the ext headers. .. systemc: Add a

[gem5-dev] Change in gem5/gem5[master]: cpu: Proposal for changing the indirect branch predictor interface

Pau Cabre has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15318 ) Change subject: cpu: Proposal for changing the indirect branch predictor interface .. cpu: Proposal for

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Copy over flags to forwarded response

Hello Jason Lowe-Power, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16182 to look at the new patch set (#2). Change subject: mem-cache: Copy over flags to forwarded response

Re: [gem5-dev] Status of automated CI on Gerrit reviews before merging

Hi Ciro, We're planning on using the Google Jenkins server. Google has graciously said they will donate the needed CPU cycles :). See https://gem5.googlesource.com/testing/jenkins-gem5-prod/ for the current state of the CI testing. I'll start looking into this again, soon. Cheers, Jason On Fri,

Re: [gem5-dev] Status of automated CI on Gerrit reviews before merging

On 2/8/19 3:13 PM, Jason Lowe-Power wrote: > Hi Ciro, > > Yeah, I've been working on this for a while, albeit slowly. The main thing > you could do to help is to test and review the new testing infrastructure > changes: > https://gem5-review.googlesource.com/q/owner:yazakram%2540ucdavis.edu. >

[gem5-dev] Change in gem5/gem5[master]: riscv: fix AMO, LR and SC instructions

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/8189 ) Change subject: riscv: fix AMO, LR and SC instructions .. riscv: fix AMO, LR and SC instructions (1) Atomic

[gem5-dev] Change in gem5/gem5[master]: cpu: support atomic memory request type with AtomicOpFunctor

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/8188 ) Change subject: cpu: support atomic memory request type with AtomicOpFunctor .. cpu: support atomic memory

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: initialize RISC-V's thread pointer register in clone syscall

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9622 ) Change subject: arch-riscv: initialize RISC-V's thread pointer register in clone syscall .. arch-riscv:

[gem5-dev] Change in gem5/gem5[master]: cpu: stop scheduling suspended threads in all stages of MinorCPU

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9625 ) Change subject: cpu: stop scheduling suspended threads in all stages of MinorCPU .. cpu: stop scheduling

[gem5-dev] Change in gem5/gem5[master]: sim, cpu: make exit_group halt all threads in a group

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9623 ) Change subject: sim,cpu: make exit_group halt all threads in a group .. sim,cpu: make exit_group halt all

[gem5-dev] Change in gem5/gem5[master]: kern, sim: implement FUTEX_WAKE_OP

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9630 ) Change subject: kern,sim: implement FUTEX_WAKE_OP .. kern,sim: implement FUTEX_WAKE_OP This patch implements

[gem5-dev] Change in gem5/gem5[master]: riscv: ignore nanosleep syscall

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9624 ) Change subject: riscv: ignore nanosleep syscall .. riscv: ignore nanosleep syscall Change-Id:

[gem5-dev] Change in gem5/gem5[master]: sim: handle the case when there're not enough HW thread contexts

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9628 ) Change subject: sim: handle the case when there're not enough HW thread contexts .. sim: handle the case

[gem5-dev] Change in gem5/gem5[master]: sim, kern: support FUTEX_CMP_REQUEUE

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9629 ) Change subject: sim, kern: support FUTEX_CMP_REQUEUE .. sim, kern: support FUTEX_CMP_REQUEUE This patch

[gem5-dev] Change in gem5/gem5[master]: riscv: fixed syscall return value

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9627 ) Change subject: riscv: fixed syscall return value .. riscv: fixed syscall return value In case of failure, a

[gem5-dev] Change in gem5/gem5[master]: cpu: fix how branching is handled when a thread is suspended in MinorCPU

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9626 ) Change subject: cpu: fix how branching is handled when a thread is suspended in MinorCPU .. cpu: fix how

[gem5-dev] Change in gem5/gem5[master]: cpu: fixed how O3 CPU executes an exit system call

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/8184 ) Change subject: cpu: fixed how O3 CPU executes an exit system call .. cpu: fixed how O3 CPU executes an exit

[gem5-dev] Change in gem5/gem5[master]: sim, kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/9621 ) Change subject: sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops .. sim,kern: support

Re: [gem5-dev] Panic when trying to run SPEC2017 on GEM5

Hey Dan, There are probably a couple of issues you're seeing: 1) The invalid instruction is likely an SSE or AVX instruction that gem5 doesn't implement. You *could* solve this by using something like -march=athlon64, but there are downsides to compiling for a 20 year old processor 2) Running

Re: [gem5-dev] Status of automated CI on Gerrit reviews before merging

Hi Ciro, Yeah, I've been working on this for a while, albeit slowly. The main thing you could do to help is to test and review the new testing infrastructure changes: https://gem5-review.googlesource.com/q/owner:yazakram%2540ucdavis.edu. Another huge help would be to convert the old tests in

[gem5-dev] Panic when trying to run SPEC2017 on GEM5

Hello, While trying to run perlbench from SPEC2017 with se.py config on top of Ubuntu 18 and perlbench compiled in Ubuntu 18 as well, it's seems that compilation generated modern instruction that are not supported by Gem5. log: command line: ./build/X86/gem5.opt configs/example/se.py -c

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix Virtual interrupts in AArch64

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16202 ) Change subject: arch-arm: Fix Virtual interrupts in AArch64 .. arch-arm: Fix Virtual interrupts in

[gem5-dev] Status of automated CI on Gerrit reviews before merging

Hi people, I really feel the need for a CI system that tests the build and posts some kind of comment on Gerrit before we merge, to help preventing breaking the build. I've been told someone might be working on it already. If that is the case, what are you looking into, and what is the status of

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16242 ) Change subject: arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 ..

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16242 Change subject: arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 .. arch-arm: Fix

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher

Javier Bueno Hedo has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/16223 ) Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Allow ArmPPI usage for PMU

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16204 ) Change subject: arch-arm: Allow ArmPPI usage for PMU .. arch-arm: Allow ArmPPI usage for PMU

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix initialization of PMU counters

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16203 ) Change subject: arch-arm: Fix initialization of PMU counters .. arch-arm: Fix initialization of

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! *