Hi,
I try to play with gem5 for ARM device simulation. Saddly, I get a
segfault when I try to checkoint.
I don't know what to report or what to do, so here a lot of info.
The gdb session is still active.
last gem5 commit is 91195ae7f637d1d4879cc3bf0860147333846e75
Many thanks in advance.
Best
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17488
Change subject: base,python: Fix to allow multiple --debug-ignore values.
..
base,python: Fix to allow
Hi Andrew,
There is a fairly lengthy commit message for 51becd2 ("O3 LSQ Generalisation")
which explains briefly the main ideas behind the rewrite.
Regarding the particular assertion, the reason is likely to be that the X86 tlb
code does not call
'translation->markDelayed()' when the
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16423 )
Change subject: mem-cache: Added the STeMS prefetcher
..
mem-cache: Added the STeMS prefetcher
Hello Jason Lowe-Power, Daniel Carvalho,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/11850
to look at the new patch set (#5).
Change subject: configs: Remove default kernel value from system creation
Hello Jason Lowe-Power, Daniel Carvalho,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/11850
to look at the new patch set (#4).
Change subject: configs: Add kernel parameter to system creation