Hi Andrew,
There is a fairly lengthy commit message for 51becd2 ("O3 LSQ Generalisation")
which explains briefly the main ideas behind the rewrite.
Regarding the particular assertion, the reason is likely to be that the X86 tlb
code does not call
'translation->markDelayed()' when the translation triggers hardware page
walks. Adding markDelayed() to src/arch/x86/tlb.cc should fix the issue. (You
can look at src/arch/arm/tlb.cc for to see how this is done for Arm.)
Cheers,
- Gabor
On 19/03/2019, 19:48, "gem5-dev on behalf of Zigerelli, Andrew D"
<[email protected] on behalf of [email protected]> wrote:
Dear Giacomo Travaglini, Gabor Dozsa,
Regarding your LSQ rewrite commit in January:
51becd2475748fb5515f261254c48827b3b5c2ba
Because this is a substantial rewrite, is there any documentation related
to how things work now?
I'm trying to debug an assert I get with X86 and O3 cpu in lsq_impl.hh.
LSQ<Impl>::SplitDataRequest::finish(const Fault &fault, const RequestPtr
&req,
ThreadContext* tc, BaseTLB::Mode mode)
_fault.push_back(fault);
assert(req == _requests[numTranslatedFragments] || this->isDelayed());
I'm interested in the fix, but I'd also like to know how the new LSQ works
because it's related to my work.
I can bypass by using the gem5 before the rewrite, but I assume this is
something that should be fixed anyway.
Thank you,
Andrew Zigerelli
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