[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: FAILED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: FAILED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: FAILED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: FAILED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: FAILED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: FAILED! * build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: FAILED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: FAILED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: FAILED! * build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic: FAILED! * build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing: FAILED! * build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED!*** diff[smred.out]: SKIPPED * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! *
[gem5-dev] Change in gem5/gem5[master]: cpu: Remove hwrei from the generic interfaces.
Hello Andreas Sandberg, kokoro, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18432 to look at the new patch set (#3). Change subject: cpu: Remove hwrei from the generic interfaces. .. cpu: Remove hwrei from the generic interfaces. This mechanism is specific to Alpha and doesn't belong sprinkled around the CPU's generic mechanisms. Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1 --- M src/arch/alpha/ev5.cc M src/cpu/checker/cpu.hh M src/cpu/exec_context.hh M src/cpu/minor/exec_context.hh M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/o3/dyn_inst.hh M src/cpu/o3/dyn_inst_impl.hh M src/cpu/simple/exec_context.hh M src/cpu/simple_thread.cc M src/cpu/simple_thread.hh 11 files changed, 0 insertions(+), 103 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18432 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1 Gerrit-Change-Number: 18432 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: alpha: Delete all occurrances of the simPalCheck function.
Hello Andreas Sandberg, kokoro, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18434 to look at the new patch set (#2). Change subject: cpu: alpha: Delete all occurrances of the simPalCheck function. .. cpu: alpha: Delete all occurrances of the simPalCheck function. This is now handled within the ISA description. Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32 --- M src/arch/alpha/ev5.cc M src/cpu/checker/cpu.hh M src/cpu/exec_context.hh M src/cpu/minor/exec_context.hh M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/o3/dyn_inst.hh M src/cpu/o3/dyn_inst_impl.hh M src/cpu/simple/exec_context.hh M src/cpu/simple_thread.cc M src/cpu/simple_thread.hh 11 files changed, 0 insertions(+), 120 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18434 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32 Gerrit-Change-Number: 18434 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: use DPRINTF_SYSCALL for ioctl/wait4
Brandon Potter has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/12124 ) Change subject: sim-se: use DPRINTF_SYSCALL for ioctl/wait4 .. sim-se: use DPRINTF_SYSCALL for ioctl/wait4 Change-Id: I4fbaf1a0653f13ae964a2574cc26bbaac2dc0686 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12124 Maintainer: Brandon Potter Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- M src/sim/syscall_emul.hh 1 file changed, 3 insertions(+), 4 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Brandon Potter: Looks good to me, approved kokoro: Regressions pass diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index 892d9d7..7996027 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -754,7 +754,7 @@ int tgt_fd = p->getSyscallArg(tc, index); unsigned req = p->getSyscallArg(tc, index); -DPRINTF(SyscallVerbose, "ioctl(%d, 0x%x, ...)\n", tgt_fd, req); +DPRINTF_SYSCALL(Verbose, "ioctl(%d, 0x%x, ...)\n", tgt_fd, req); if (OS::isTtyReq(req)) return -ENOTTY; @@ -2741,10 +2741,9 @@ Addr rusagePtr = p->getSyscallArg(tc, index); if (rusagePtr) -DPRINTFR(SyscallVerbose, - "%d: %s: syscall wait4: rusage pointer provided however " +DPRINTF_SYSCALL(Verbose, "wait4: rusage pointer provided %lx, however " "functionality not supported. Ignoring rusage pointer.\n", - curTick(), tc->getCpuPtr()->name()); + rusagePtr); /** * Currently, wait4 is only implemented so that it will wait for children -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12124 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4fbaf1a0653f13ae964a2574cc26bbaac2dc0686 Gerrit-Change-Number: 12124 Gerrit-PatchSet: 23 Gerrit-Owner: Brandon Potter Gerrit-Reviewer: Alexandru Duțu Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: John Alsop Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: bugfix for 54c77aa055e
Brandon Potter has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18448 )
Change subject: sim-se: bugfix for 54c77aa055e
..
sim-se: bugfix for 54c77aa055e
54c77aa055e introduced a bug which manifests as cyclical
dependency on a member initialization for the Process
class.
The current working directory (cwd) parameter is passed into
Process to initialize both the target and host versions of the
cwd. (The target and host versions may differ if the faux
filesystem is used.) The host cwd init invoked methods which
rely on the host cwd already being initialized. To avoid the
bug, the code will now rely on using the targets cwd version,
but will issue checks against the redirect paths.
Change-Id: I4ab644a3e00737dbf249f5d6faf20a26ceb04248
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18448
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/process.cc
1 file changed, 15 insertions(+), 18 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 10c68fe..d400b5d 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -456,19 +456,16 @@
std::string
Process::checkPathRedirect(const std::string )
{
-// If the input parameter contains a relative path, convert it. Note,
-// the return value for this method should always return an absolute
-// path on the host filesystem. The return value will be used to
-// open and manipulate the path specified by the input parameter. Since
-// all filesystem handling in syscall mode is passed through to the
host,
-// we deal only with host paths.
-auto host_fs_abs_path = absolutePath(filename, true);
+// If the input parameter contains a relative path, convert it.
+// The target version of the current working directory is fine since
+// we immediately convert it using redirect paths into a host version.
+auto abs_path = absolutePath(filename, false);
for (auto path : system->redirectPaths) {
// Search through the redirect paths to see if a starting
substring of
// our path falls into any buckets which need to redirected.
-if (startswith(host_fs_abs_path, path->appPath())) {
-std::string tail =
host_fs_abs_path.substr(path->appPath().size());
+if (startswith(abs_path, path->appPath())) {
+std::string tail = abs_path.substr(path->appPath().size());
// If this path needs to be redirected, search through a list
// of targets to see if we can match a valid file (or
directory).
@@ -486,7 +483,7 @@
}
// The path does not need to be redirected.
-return host_fs_abs_path;
+return abs_path;
}
void
@@ -543,17 +540,17 @@
if (filename.empty() || startswith(filename, "/"))
return filename;
-// Verify that the current working directories are initialized
properly.
-// These members should be set initially via params from 'Process.py',
-// although they may change over time depending on what the application
-// does during simulation.
-assert(!tgtCwd.empty());
-assert(!hostCwd.empty());
-
// Construct the absolute path given the current working directory for
// either the host filesystem or target filesystem. The distinction
only
// matters if filesystem redirection is utilized in the simulation.
-auto path_base = host_filesystem ? hostCwd : tgtCwd;
+auto path_base = std::string();
+if (host_filesystem) {
+path_base = hostCwd;
+assert(!hostCwd.empty());
+} else {
+path_base = tgtCwd;
+assert(!tgtCwd.empty());
+}
// Add a trailing '/' if the current working directory did not have
one.
normalize(path_base);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18448
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4ab644a3e00737dbf249f5d6faf20a26ceb04248
Gerrit-Change-Number: 18448
Gerrit-PatchSet: 2
Gerrit-Owner: Brandon Potter
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch: cpu: Track kernel stats using the base ISA agnostic type.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18429 )
Change subject: arch: cpu: Track kernel stats using the base ISA agnostic
type.
..
arch: cpu: Track kernel stats using the base ISA agnostic type.
Then cast to the ISA specific type when necessary. This removes
(mostly) an ISA specific aspect to some of the interfaces. The ISA
specific version of the kernel stats still needs to be constructed and
stored in a few places which means that kernel_stats.hh still needs to
be a switching arch header, for instance.
In the future, I'd like to make the kernel its own object like the
Process objects in SE mode, and then it would be able to instantiate
and maintain its own stats.
Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/alpha/ev5.cc
M src/arch/alpha/idle_event.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple/base.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/kern/kernel_stats.hh
M src/sim/pseudo_inst.cc
15 files changed, 53 insertions(+), 46 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index bac8e8d..e3e025e 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -219,6 +219,9 @@
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
+auto *stats = dynamic_cast(
+tc->getKernelStats());
+assert(stats || !tc->getKernelStats());
switch (idx) {
case IPR_PALtemp0:
case IPR_PALtemp1:
@@ -267,8 +270,8 @@
case IPR_PALtemp23:
// write entire quad w/ no side-effect
-if (tc->getKernelStats())
-tc->getKernelStats()->context(ipr[idx], val, tc);
+if (stats)
+stats->context(ipr[idx], val, tc);
ipr[idx] = val;
break;
@@ -291,17 +294,17 @@
case IPR_IPLR:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
-if (tc->getKernelStats())
-tc->getKernelStats()->swpipl(ipr[idx]);
+if (stats)
+stats->swpipl(ipr[idx]);
break;
case IPR_DTB_CM:
if (val & 0x18) {
-if (tc->getKernelStats())
-tc->getKernelStats()->mode(Kernel::user, tc);
+if (stats)
+stats->mode(Kernel::user, tc);
} else {
-if (tc->getKernelStats())
-tc->getKernelStats()->mode(Kernel::kernel, tc);
+if (stats)
+stats->mode(Kernel::kernel, tc);
}
M5_FALLTHROUGH;
@@ -485,6 +488,9 @@
Fault
SimpleThread::hwrei()
{
+auto *stats = dynamic_cast*>(kernelStats);
+assert(stats || !kernelStats);
+
PCState pc = pcState();
if (!(pc.pc() & 0x3))
return std::make_shared();
@@ -494,8 +500,8 @@
CPA::cpa()->swAutoBegin(this, pc.npc());
-if (kernelStats)
-kernelStats->hwrei();
+if (stats)
+stats->hwrei();
// FIXME: XXX check for interrupts? XXX
return NoFault;
@@ -508,8 +514,11 @@
bool
SimpleThread::simPalCheck(int palFunc)
{
-if (kernelStats)
-kernelStats->callpal(palFunc, this);
+auto *stats = dynamic_cast*>(kernelStats);
+assert(stats || !kernelStats);
+
+if (stats)
+stats->callpal(palFunc, this);
switch (palFunc) {
case PAL::halt:
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 080dcb2..df8a0c6 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -41,7 +41,10 @@
{
if (tc->getKernelStats()) {
RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
-tc->getKernelStats()->setIdleProcess(val, tc);
+auto *stats = dynamic_cast(
+tc->getKernelStats());
+assert(stats);
+stats->setIdleProcess(val, tc);
}
remove();
}
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index fe1c3d4..7f8eada 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -47,7 +47,6 @@
#include
#include "arch/generic/tlb.hh"
-#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 26973cd..ed8add6 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -52,10 +52,10 @@
#include "debug/Checker.hh"
class EndQuiesceEvent;
[gem5-dev] Change in gem5/gem5[master]: alpha: Add some control registers to the ISA operands list.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18430 )
Change subject: alpha: Add some control registers to the ISA operands list.
..
alpha: Add some control registers to the ISA operands list.
These will be used in the in-ISA HWREI implementation.
Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18430
Reviewed-by: Andreas Sandberg
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/alpha/isa/main.isa
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 6462866..f77b1f9 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -76,6 +76,7 @@
#include
#include "arch/alpha/decoder.hh"
+#include "arch/alpha/kernel_stats.hh"
#include "arch/alpha/registers.hh"
#include "arch/alpha/regredir.hh"
#include "arch/generic/memhelpers.hh"
@@ -198,6 +199,8 @@
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
+'LockFlag': ('ControlReg', 'uq', 'MISCREG_LOCKFLAG', None, 1),
+'IprExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18430
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62
Gerrit-Change-Number: 18430
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: alpha: Implement HWREI in the ISA.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18431 )
Change subject: alpha: Implement HWREI in the ISA.
..
alpha: Implement HWREI in the ISA.
This moves it out of generic interfaces and the CPU implementations.
Change-Id: I6767d6b26d0ae128b5bdad5830dce838be74e256
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18431
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/alpha/isa/decoder.isa
1 file changed, 18 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 8789fa9..5635d38 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -930,7 +930,24 @@
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
format BasicOperate {
- 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
+ 1: hw_rei({{
+Addr pc = PC;
+if (!(pc & 0x3))
+return std::make_shared();
+
+LockFlag = false;
+NPC = IprExcAddr;
+
+ThreadContext *tc = xc->tcBase();
+auto *base_stats = tc->getKernelStats();
+auto *stats = dynamic_cast(
+base_stats);
+assert(stats || !base_stats);
+if (stats)
+stats->hwrei();
+
+CPA::cpa()->swAutoBegin(tc, IprExcAddr);
+ }}, IsSerializing, IsSerializeBefore);
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6767d6b26d0ae128b5bdad5830dce838be74e256
Gerrit-Change-Number: 18431
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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Re: [gem5-dev] gerrit pickiness interacting with kokoro
Hello again. I asked the gurus, and they say we probably want to set content merging to true. Any objections? I'd like to flip that switch before I go on my trip, so by the end of the week. Gabe On Sat, Apr 27, 2019 at 5:09 PM Gabe Black wrote: > Hi folks. It's historically been an issue with gerrit as we have it set up > for use in gem5 that it seems to be pretty picky about when a change can be > submitted, and I've had to fairly often (but not always) perform a trivial > rebase through the gerrit UI so that it's happy and will let me submit a > CL. In the past this has been annoying, but not a big deal since it just > takes a few clicks to placate gerrit. > > Now that we have kokoro running and verifying CLs (which is a very good > thing), rebases have the unfortunate side effect of clearing the verified > bit which necessitates running the CI again on essentially the same CL, > including a several hour wait. So far this has been a bigger annoyance than > before with the added latency getting a CL submitted, but since there > haven't (yet) been any series with a lot of those delays stack on top of > each other it hasn't been a huge problem. > > What I'd like to know is what people think about making gerrit less picky > (not sure how that translates to settings TBH) so that these trivial > rebases aren't as necessary. Looking at the settings, I see that the > "Submit type" is "Rebase Always" and the "Allow content merges" setting is > false. There are other settings, but these seem like the most relevant ones. > > This page takes a bit about the philosophy behind the submit type setting: > > > https://gerrit-review.googlesource.com/Documentation/intro-project-owner.html > > With a more complete description of all the submit types over here: > > > https://gerrit-review.googlesource.com/Documentation/config-project-config.html#submit-type > > If people agree that this is something we should try to change, we can > probably ask the gerrit gurus here at Google what settings we can adjust to > get the desired effect. > > Gabe > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch: Stop using TheISA within the ISAs.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18488
Change subject: arch: Stop using TheISA within the ISAs.
..
arch: Stop using TheISA within the ISAs.
We know for sure what the ISA is, so there's no need for the
indirection.
Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
---
M src/arch/alpha/utility.cc
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_base.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/tracers/tarmac_record_v8.hh
M src/arch/arm/tracers/tarmac_tracer.cc
M src/arch/arm/tracers/tarmac_tracer.hh
M src/arch/mips/utility.cc
M src/arch/power/stacktrace.hh
M src/arch/riscv/stacktrace.hh
M src/arch/sparc/utility.cc
M src/arch/x86/process.cc
20 files changed, 58 insertions(+), 62 deletions(-)
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index c03e7b0..c644911 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -100,7 +100,7 @@
void
skipFunction(ThreadContext *tc)
{
-TheISA::PCState newPC = tc->pcState();
+PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}
diff --git a/src/arch/arm/isa/insts/fp64.isa
b/src/arch/arm/isa/insts/fp64.isa
index 26803e7..7decbac 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -45,7 +45,7 @@
exec_output = ""
zeroSveVecRegUpperPartCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen(xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/insts/ldr64.isa
b/src/arch/arm/isa/insts/ldr64.isa
index fe7eaf0..56112a7 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -185,7 +185,7 @@
accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
elif self.flavor == "fp":
accEpilogCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmStaticInst::getCurSveVecLen(
xc->tcBase()));
'''
@@ -239,10 +239,10 @@
# Code that actually handles the access
if self.flavor == "fp":
accEpilogCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmStaticInst::getCurSveVecLen(
xc->tcBase()));
-TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
+ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
ArmStaticInst::getCurSveVecLen(
xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa
b/src/arch/arm/isa/insts/neon64_mem.isa
index 8f53369..03ad294 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -45,7 +45,7 @@
exec_output = ''
zeroSveVecRegUpperPartCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen(xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index e5e9e24..c46a34d 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1555,7 +1555,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen(
xc->tcBase());
-TheISA::VecRegContainer tmpVecC;
+ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -1616,7 +1616,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen(
xc->tcBase());
-TheISA::VecRegContainer tmpVecC;
+ArmISA::VecRegContainer tmpVecC;
auto tmpVec = tmpVecC.as();
int ePow2Count = 1;
while (ePow2Count < eCount) {
@@ -1761,7 +1761,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen(
xc->tcBase());
-TheISA::VecRegContainer tmpVecC;
+ArmISA::VecRegContainer tmpVecC;
auto auxOp2 = tmpVecC.as();
for (unsigned i = 0; i < eCount; i++) {
auxOp2[i] = AA64FpOp2_ud[i];
@@ -1917,7 +1917,7 @@
[gem5-dev] Change in gem5/gem5[master]: sim-se: add socket ioctls
Brandon Potter has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/12123 )
Change subject: sim-se: add socket ioctls
..
sim-se: add socket ioctls
The OpenMPI 1.8.2 runtime needs the ioctl code
included in this patch to issue socket operations
on the host machine.
Change-Id: I687b31f375a846f0bab2debd9b9472605a4d2c7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12123
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/sim/syscall_emul.hh
1 file changed, 57 insertions(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 1d14af9..892d9d7 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -78,14 +78,19 @@
#endif
#include
+#include
#include
+#include
#include
#include
#include
+
#if (NO_STATFS == 0)
#include
+
#else
#include
+
#endif
#include
#include
@@ -755,17 +760,59 @@
return -ENOTTY;
auto dfdp =
std::dynamic_pointer_cast((*p->fds)[tgt_fd]);
-if (!dfdp)
-return -EBADF;
+if (dfdp) {
+EmulatedDriver *emul_driver = dfdp->getDriver();
+if (emul_driver)
+return emul_driver->ioctl(p, tc, req);
+}
-/**
- * If the driver is valid, issue the ioctl through it. Otherwise,
- * there's an implicit assumption that the device is a TTY type and we
- * return that we do not have a valid TTY.
- */
-EmulatedDriver *emul_driver = dfdp->getDriver();
-if (emul_driver)
-return emul_driver->ioctl(p, tc, req);
+auto sfdp =
std::dynamic_pointer_cast((*p->fds)[tgt_fd]);
+if (sfdp) {
+int status;
+
+switch (req) {
+ case SIOCGIFCONF: {
+Addr conf_addr = p->getSyscallArg(tc, index);
+BufferArg conf_arg(conf_addr, sizeof(ifconf));
+conf_arg.copyIn(tc->getMemProxy());
+
+ifconf *conf = (ifconf*)conf_arg.bufferPtr();
+Addr ifc_buf_addr = (Addr)conf->ifc_buf;
+BufferArg ifc_buf_arg(ifc_buf_addr, conf->ifc_len);
+ifc_buf_arg.copyIn(tc->getMemProxy());
+
+conf->ifc_buf = (char*)ifc_buf_arg.bufferPtr();
+
+status = ioctl(sfdp->getSimFD(), req, conf_arg.bufferPtr());
+if (status != -1) {
+conf->ifc_buf = (char*)ifc_buf_addr;
+ifc_buf_arg.copyOut(tc->getMemProxy());
+conf_arg.copyOut(tc->getMemProxy());
+}
+
+return status;
+ }
+ case SIOCGIFFLAGS:
+#ifdef __linux__
+ case SIOCGIFINDEX:
+#endif
+ case SIOCGIFNETMASK:
+ case SIOCGIFADDR:
+#ifdef __linux__
+ case SIOCGIFHWADDR:
+#endif
+ case SIOCGIFMTU: {
+Addr req_addr = p->getSyscallArg(tc, index);
+BufferArg req_arg(req_addr, sizeof(ifreq));
+req_arg.copyIn(tc->getMemProxy());
+
+status = ioctl(sfdp->getSimFD(), req, req_arg.bufferPtr());
+if (status != -1)
+req_arg.copyOut(tc->getMemProxy());
+return status;
+ }
+}
+}
/**
* For lack of a better return code, return ENOTTY. Ideally, we should
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I687b31f375a846f0bab2debd9b9472605a4d2c7d
Gerrit-Change-Number: 12123
Gerrit-PatchSet: 25
Gerrit-Owner: Brandon Potter
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: systemc: Add a distinct async_request_update mechanism.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18288 )
Change subject: systemc: Add a distinct async_request_update mechanism.
..
systemc: Add a distinct async_request_update mechanism.
This mechanism had just been plumbed into the regular request_update,
but that doesn't have any thread safety which is the whole point of
async_request_update. This new mechanism puts async update requests
into their own list which is checked any time normal updates happen.
The delta cycle which triggers those updates must happen through some
other means which will usually be ok. The exact timing of the update
is undefined, so it would be legal for it to either not be recognized
before the impending end of the simulation, or for it to get picked up
by subsequent activity. If there isn't subsequent activity but the
simulation also doesn't end, for instance if there are only gem5 events
left, then that update could be lost. That is an unresolved issue.
It would be nice to schedule a "ready" event if async updates were
added which would ensure they wouldn't starve. Unfortunately that
requires the event queue lock, and in practice it's been found that a
systemc process might block, effectively holding the event queue lock,
while it waits for some asyncrhonous update to give it something to do.
This effectively deadlocks the system since the update is blocked on
the lock the main thread holds, and the main thread is blocked waiting
for the update.
Change-Id: I580303db01673faafc2e63545b6a69b3327a521c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18288
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/core/channel.cc
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
3 files changed, 20 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/core/channel.cc b/src/systemc/core/channel.cc
index 04f158b..4c73171 100644
--- a/src/systemc/core/channel.cc
+++ b/src/systemc/core/channel.cc
@@ -54,8 +54,7 @@
void
Channel::asyncRequestUpdate()
{
-//TODO This should probably not request an update directly.
-scheduler.requestUpdate(this);
+scheduler.asyncRequestUpdate(this);
}
std::set allChannels;
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index d06ddfb..f1a7819 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -258,6 +258,13 @@
}
void
+Scheduler::asyncRequestUpdate(Channel *c)
+{
+std::lock_guard lock(asyncListMutex);
+asyncUpdateList.pushLast(c);
+}
+
+void
Scheduler::scheduleReadyEvent()
{
// Schedule the evaluate and update phases.
@@ -321,6 +328,12 @@
Scheduler::runUpdate()
{
status(StatusUpdate);
+{
+std::lock_guard lock(asyncListMutex);
+Channel *channel;
+while ((channel = asyncUpdateList.getNext()) != nullptr)
+updateList.pushLast(channel);
+}
try {
Channel *channel = updateList.getNext();
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 63f6ac3..b576bec 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -32,6 +32,7 @@
#include
#include
+#include
#include
#include
@@ -191,6 +192,8 @@
// Schedule an update for a given channel.
void requestUpdate(Channel *c);
+// Same as above, but may be called from a different thread.
+void asyncRequestUpdate(Channel *c);
// Run the given process immediately, preempting whatever may be
running.
void
@@ -481,6 +484,9 @@
ChannelList updateList;
+ChannelList asyncUpdateList;
+std::mutex asyncListMutex;
+
std::map<::Event *, Tick> eventsToSchedule;
std::set traceFiles;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I580303db01673faafc2e63545b6a69b3327a521c
Gerrit-Change-Number: 18288
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18469
Change subject: sparc: Move the interrupt types out of isa_traits.hh into
interrupts.hh.
..
sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.
Those types aren't generic or used outside of SPARC.
Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde
---
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
M src/dev/sparc/iob.cc
5 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index e6c9266..abc899e 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -43,6 +43,18 @@
namespace SparcISA
{
+enum InterruptTypes
+{
+IT_TRAP_LEVEL_ZERO,
+IT_HINTP,
+IT_INT_VEC,
+IT_CPU_MONDO,
+IT_DEV_MONDO,
+IT_RES_ERROR,
+IT_SOFT_INT,
+NumInterruptTypes
+};
+
class Interrupts : public SimObject
{
private:
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 58d8437..5bcfc04 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -61,18 +61,6 @@
const Addr PAddrImplMask = ULL(0x00FF);
const Addr BytesInPageMask = ULL(0x1FFF);
-enum InterruptTypes
-{
-IT_TRAP_LEVEL_ZERO,
-IT_HINTP,
-IT_INT_VEC,
-IT_CPU_MONDO,
-IT_DEV_MONDO,
-IT_RES_ERROR,
-IT_SOFT_INT,
-NumInterruptTypes
-};
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index b2078dd..8564c43 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -34,6 +34,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/faults.hh"
+#include "arch/sparc/interrupts.hh"
#include "arch/sparc/registers.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 4cafff4..389549b 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arch/sparc/interrupts.hh"
#include "arch/sparc/isa.hh"
#include "arch/sparc/kernel_stats.hh"
#include "arch/sparc/registers.hh"
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index f146536..1df6dec 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -40,6 +40,7 @@
#include
#include "arch/sparc/faults.hh"
+#include "arch/sparc/interrupts.hh"
#include "arch/sparc/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
--
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Gerrit-Branch: master
Gerrit-Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde
Gerrit-Change-Number: 18469
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch: Remove the mt.hh switching header.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18468
Change subject: arch: Remove the mt.hh switching header.
..
arch: Remove the mt.hh switching header.
This header was only useful in MIPS and is only used internally within
MIPS. It doesn't need to be a switching header file.
Change-Id: Id7005f73b95e122f9ab83b3b657cae3391682f26
---
M src/arch/SConscript
D src/arch/alpha/mt.hh
D src/arch/sparc/mt.hh
3 files changed, 0 insertions(+), 141 deletions(-)
diff --git a/src/arch/SConscript b/src/arch/SConscript
index ed583aa..f59b026 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -67,7 +67,6 @@
locked_mem.hh
microcode_rom.hh
mmapped_ipr.hh
-mt.hh
process.hh
pseudo_inst.hh
registers.hh
diff --git a/src/arch/alpha/mt.hh b/src/arch/alpha/mt.hh
deleted file mode 100644
index 640825b..000
--- a/src/arch/alpha/mt.hh
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2009 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- *
- */
-
-#ifndef __ARCH_ALPHA_MT_HH__
-#define __ARCH_ALPHA_MT_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for multithreaded execution.
- */
-
-#include
-
-#include "arch/isa_traits.hh"
-#include "base/bitfield.hh"
-#include "base/logging.hh"
-#include "base/trace.hh"
-
-namespace AlphaISA
-{
-
-template
-inline unsigned
-getVirtProcNum(TC *tc)
-{
-fatal("Alpha is not setup for multithreaded ISA extensions");
-return 0;
-}
-
-
-template
-inline unsigned
-getTargetThread(TC *tc)
-{
-fatal("Alpha is not setup for multithreaded ISA extensions");
-return 0;
-}
-
-} // namespace AlphaISA
-
-#endif
diff --git a/src/arch/sparc/mt.hh b/src/arch/sparc/mt.hh
deleted file mode 100644
index faf6091..000
--- a/src/arch/sparc/mt.hh
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2011 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
[gem5-dev] Change in gem5/gem5[master]: sparc: Move translation constants from isa_traits.hh into tlb.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18470
Change subject: sparc: Move translation constants from isa_traits.hh into
tlb.hh.
..
sparc: Move translation constants from isa_traits.hh into tlb.hh.
These aren't used outside of SPARC. Also get rid of some unused
constants.
Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
---
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/tlb.hh
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 5bcfc04..f42cdb9 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,23 +44,11 @@
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
-// real address virtual mapping
-// sort of like alpha super page, but less frequently used
-const Addr SegKPMEnd = ULL(0xfffc);
-const Addr SegKPMBase = ULL(0xfac0);
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
StaticInstPtr decodeInst(ExtMachInst);
-/// TLB Stuff
-const Addr StartVAddrHole = ULL(0x8000);
-const Addr EndVAddrHole = ULL(0x7FFF);
-const Addr VAddrAMask = ULL(0x);
-const Addr PAddrImplMask = ULL(0x00FF);
-const Addr BytesInPageMask = ULL(0x1FFF);
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e5e6753..0d173da 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -44,6 +44,11 @@
namespace SparcISA
{
+const Addr StartVAddrHole = ULL(0x8000);
+const Addr EndVAddrHole = ULL(0x7FFF);
+const Addr VAddrAMask = ULL(0x);
+const Addr PAddrImplMask = ULL(0x00FF);
+
class TLB : public BaseTLB
{
// These faults need to be able to populate the tlb in SE mode.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Gerrit-Change-Number: 18470
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: x86: Get rid of some unnecessary TheISA-es in x86.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18471
Change subject: x86: Get rid of some unnecessary TheISA-es in x86.
..
x86: Get rid of some unnecessary TheISA-es in x86.
The X86ISA namespace is already available.
Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4
---
M src/arch/x86/memhelpers.hh
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 416439b..59db401 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -179,7 +179,7 @@
{
if (traceData)
traceData->setData(mem);
-mem = TheISA::htog(mem);
+mem = htog(mem);
return xc->writeMem((uint8_t *), dataSize, addr, flags, res);
}
@@ -209,7 +209,7 @@
{
if (traceData)
traceData->setData(mem);
-uint64_t host_mem = TheISA::htog(mem);
+uint64_t host_mem = htog(mem);
Fault fault =
xc->writeMem((uint8_t *)_mem, dataSize, addr, flags, res);
if (fault == NoFault && res)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4
Gerrit-Change-Number: 18471
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mips: Implement readRegOtherThread and setRegOtherThread directly.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18435 )
Change subject: mips: Implement readRegOtherThread and setRegOtherThread
directly.
..
mips: Implement readRegOtherThread and setRegOtherThread directly.
These accessors can be implemented as helper functions within MIPS
without having to plumb them through a bunch of common interfaces.
There are a few problems with the way they were implemented which are
carried forward to this new implementation as well. That includes
hiding the register accesses from the ISA parser and therefore the
CPU's dependency tracking, potentially panicing or accessing a non
existent thread based on a possible set of input values, and modifying
register values even if an instruction is being executed speculatively.
Fixing these problems would be fairly involved and require changing how
dependencies are tracked in all the CPUs so that they can act across
threads, and also how registers are handled in the ISA description
itself.
The original implementation just punted on making this work in CPUs
other than the minor CPU (and potentially one or more CPU models that
were not and/or are not in the code base). Where as that implementation
might have paniced if these methods were called, this will attempt to
work, but may have incorrect behavior based on the limitations
described above. I'd consider this an acceptable tradeoff, at least for
the time being.
Change-Id: I94adceafb9812a8641c76ea3518c3285c31baf51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18435
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/mt.isa
M src/arch/mips/mt.hh
3 files changed, 110 insertions(+), 47 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 771e6f9..3406ed5 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -383,85 +383,85 @@
// Decode MIPS MT MFTR instruction into
sub-instructions
0x8: decode MT_U {
0x0: mftc0({{
-data =
xc->readRegOtherThread(RegId(MiscRegClass,
+data = readRegOtherThread(xc,
RegId(MiscRegClass,
(RT << 3 |
SEL)));
}});
0x1: decode SEL {
0x0: mftgpr({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
RT));
}});
0x1: decode RT {
0x0: mftlo_dsp0({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
INTREG_DSP_LO0));
}});
0x1: mfthi_dsp0({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
INTREG_DSP_HI0));
}});
0x2: mftacx_dsp0({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
INTREG_DSP_ACX0));
}});
0x4: mftlo_dsp1({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
INTREG_DSP_LO1));
}});
0x5: mfthi_dsp1({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
INTREG_DSP_HI1));
}});
0x6: mftacx_dsp1({{
-data = xc->readRegOtherThread(
+data = readRegOtherThread(xc,
RegId(IntRegClass,
INTREG_DSP_ACX1));
}});
0x8: mftlo_dsp2({{
-data = xc->readRegOtherThread(
[gem5-dev] Change in gem5/gem5[master]: cpu: Get rid of the (read|set)RegOtherThread methods.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18436 )
Change subject: cpu: Get rid of the (read|set)RegOtherThread methods.
..
cpu: Get rid of the (read|set)RegOtherThread methods.
These are implemented by MIPS internally now.
Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Andreas Sandberg
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/exec_context.hh
M src/cpu/thread_context.hh
6 files changed, 0 insertions(+), 119 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5f830d7..96f6cc7 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -483,21 +483,6 @@
return this->setMiscReg(reg.index(), val);
}
-#if THE_ISA == MIPS_ISA
-RegVal
-readRegOtherThread(const RegId _reg, ThreadID tid) override
-{
-panic("MIPS MT not defined for CheckerCPU.\n");
-return 0;
-}
-
-void
-setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
override
-{
-panic("MIPS MT not defined for CheckerCPU.\n");
-}
-#endif
-
/
void
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index d46cc13..58d756c 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -353,20 +353,6 @@
virtual AddressMonitor *getAddrMonitor() = 0;
/** @} */
-
-/**
- * @{
- * @name MIPS-Specific Interfaces
- */
-
-#if THE_ISA == MIPS_ISA
-virtual RegVal readRegOtherThread(const RegId ,
- ThreadID tid=InvalidThreadID) = 0;
-virtual void setRegOtherThread(const RegId& reg, RegVal val,
- ThreadID tid=InvalidThreadID) = 0;
-#endif
-
-/** @} */
};
#endif // __CPU_EXEC_CONTEXT_HH__
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 02b3dae..4ac621a 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -441,51 +441,6 @@
BaseCPU *getCpuPtr() { return }
-/* MIPS: other thread register reading/writing */
-RegVal
-readRegOtherThread(const RegId , ThreadID tid=InvalidThreadID)
-{
-SimpleThread *other_thread = (tid == InvalidThreadID
-? : cpu.threads[tid]);
-
-switch (reg.classValue()) {
-case IntRegClass:
-return other_thread->readIntReg(reg.index());
-break;
-case FloatRegClass:
-return other_thread->readFloatReg(reg.index());
-break;
-case MiscRegClass:
-return other_thread->readMiscReg(reg.index());
-default:
-panic("Unexpected reg class! (%s)",
- reg.className());
-return 0;
-}
-}
-
-void
-setRegOtherThread(const RegId , RegVal val,
- ThreadID tid=InvalidThreadID)
-{
-SimpleThread *other_thread = (tid == InvalidThreadID
-? : cpu.threads[tid]);
-
-switch (reg.classValue()) {
-case IntRegClass:
-return other_thread->setIntReg(reg.index(), val);
-break;
-case FloatRegClass:
-return other_thread->setFloatReg(reg.index(), val);
-break;
-case MiscRegClass:
-return other_thread->setMiscReg(reg.index(), val);
-default:
-panic("Unexpected reg class! (%s)",
- reg.className());
-}
-}
-
public:
// monitor/mwait funtions
void armMonitor(Addr address) override
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 24c59a2..0188660 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -429,21 +429,6 @@
this->cpu->setCCReg(this->_destRegIdx[idx], val);
BaseDynInst::setCCRegOperand(si, idx, val);
}
-
-#if THE_ISA == MIPS_ISA
-RegVal
-readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
-{
-panic("MIPS MT not defined for O3 CPU.\n");
-return 0;
-}
-
-void
-setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
override
-{
-panic("MIPS MT not defined for O3 CPU.\n");
-}
-#endif
};
#endif // __CPU_O3_ALPHA_DYN_INST_HH__
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
[gem5-dev] Change in gem5/gem5[master]: cpu: Include debug flags regardless of whether the ISA is null.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18428 )
Change subject: cpu: Include debug flags regardless of whether the ISA is
null.
..
cpu: Include debug flags regardless of whether the ISA is null.
Whether debug flags are available has no interaction with what the ISA
is.
Change-Id: I71d9204f948618831796e6c7a4c16bbebfb1a4fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18428
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Andreas Sandberg
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/SConscript
1 file changed, 42 insertions(+), 41 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 656d9f1..a8585a7 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -30,6 +30,48 @@
Import('*')
+DebugFlag('Activity')
+DebugFlag('Commit')
+DebugFlag('Context')
+DebugFlag('Decode')
+DebugFlag('DynInst')
+DebugFlag('ExecEnable',
+'Filter: Enable exec tracing (no tracing without this)')
+DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
+DebugFlag('ExecEffAddr', 'Format: Include effective address')
+DebugFlag('ExecFaulting', 'Trace faulting instructions')
+DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
+DebugFlag('ExecOpClass', 'Format: Include operand class')
+DebugFlag('ExecRegDelta')
+DebugFlag('ExecResult', 'Format: Include results from execution')
+DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
+DebugFlag('ExecThread', 'Format: Include thread ID in trace')
+DebugFlag('ExecTicks', 'Format: Include tick count')
+DebugFlag('ExecMicro', 'Filter: Include microops')
+DebugFlag('ExecMacro', 'Filter: Include macroops')
+DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
+DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
+DebugFlag('ExecAsid', 'Format: Include ASID in trace')
+DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
+DebugFlag('Fetch')
+DebugFlag('IntrControl')
+DebugFlag('O3PipeView')
+DebugFlag('PCEvent')
+DebugFlag('Quiesce')
+DebugFlag('Mwait')
+
+CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
+'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
+'ExecResult', 'ExecSymbol', 'ExecThread',
+'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
+'ExecAsid', 'ExecFlags' ])
+CompoundFlag('Exec',
[ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
+'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
+'ExecFaulting', 'ExecUser', 'ExecKernel' ])
+CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
+'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
+'ExecUser', 'ExecKernel' ])
+
if env['TARGET_ISA'] == 'null':
SimObject('IntrControl.py')
Source('intr_control_noisa.cc')
@@ -72,44 +114,3 @@
Source('checker/cpu.cc')
Source('dummy_checker.cc')
DebugFlag('Checker')
-
-DebugFlag('Activity')
-DebugFlag('Commit')
-DebugFlag('Context')
-DebugFlag('Decode')
-DebugFlag('DynInst')
-DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without
this)')
-DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
-DebugFlag('ExecEffAddr', 'Format: Include effective address')
-DebugFlag('ExecFaulting', 'Trace faulting instructions')
-DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
-DebugFlag('ExecOpClass', 'Format: Include operand class')
-DebugFlag('ExecRegDelta')
-DebugFlag('ExecResult', 'Format: Include results from execution')
-DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
-DebugFlag('ExecThread', 'Format: Include thread ID in trace')
-DebugFlag('ExecTicks', 'Format: Include tick count')
-DebugFlag('ExecMicro', 'Filter: Include microops')
-DebugFlag('ExecMacro', 'Filter: Include macroops')
-DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
-DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
-DebugFlag('ExecAsid', 'Format: Include ASID in trace')
-DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
-DebugFlag('Fetch')
-DebugFlag('IntrControl')
-DebugFlag('O3PipeView')
-DebugFlag('PCEvent')
-DebugFlag('Quiesce')
-DebugFlag('Mwait')
-
-CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
-'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
-'ExecResult', 'ExecSymbol', 'ExecThread',
-'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
-'ExecAsid', 'ExecFlags' ])
-CompoundFlag('Exec',
[ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
-'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
-
[gem5-dev] Change in gem5/gem5[master]: sim-se: bugfix for 54c77aa055e
Brandon Potter has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18448
Change subject: sim-se: bugfix for 54c77aa055e
..
sim-se: bugfix for 54c77aa055e
54c77aa055e introduced a bug which manifests as cyclical
dependency on a member initialization for the Process
class.
The current working directory (cwd) parameter is passed into
Process to initialize both the target and host versions of the
cwd. (The target and host versions may differ if the faux
filesystem is used.) The host cwd init invoked methods which
rely on the host cwd already being initialized. To avoid the
bug, the code will now rely on using the targets cwd version,
but will issue checks against the redirect paths.
Change-Id: I4ab644a3e00737dbf249f5d6faf20a26ceb04248
---
M src/sim/process.cc
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 10c68fe..d400b5d 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -456,19 +456,16 @@
std::string
Process::checkPathRedirect(const std::string )
{
-// If the input parameter contains a relative path, convert it. Note,
-// the return value for this method should always return an absolute
-// path on the host filesystem. The return value will be used to
-// open and manipulate the path specified by the input parameter. Since
-// all filesystem handling in syscall mode is passed through to the
host,
-// we deal only with host paths.
-auto host_fs_abs_path = absolutePath(filename, true);
+// If the input parameter contains a relative path, convert it.
+// The target version of the current working directory is fine since
+// we immediately convert it using redirect paths into a host version.
+auto abs_path = absolutePath(filename, false);
for (auto path : system->redirectPaths) {
// Search through the redirect paths to see if a starting
substring of
// our path falls into any buckets which need to redirected.
-if (startswith(host_fs_abs_path, path->appPath())) {
-std::string tail =
host_fs_abs_path.substr(path->appPath().size());
+if (startswith(abs_path, path->appPath())) {
+std::string tail = abs_path.substr(path->appPath().size());
// If this path needs to be redirected, search through a list
// of targets to see if we can match a valid file (or
directory).
@@ -486,7 +483,7 @@
}
// The path does not need to be redirected.
-return host_fs_abs_path;
+return abs_path;
}
void
@@ -543,17 +540,17 @@
if (filename.empty() || startswith(filename, "/"))
return filename;
-// Verify that the current working directories are initialized
properly.
-// These members should be set initially via params from 'Process.py',
-// although they may change over time depending on what the application
-// does during simulation.
-assert(!tgtCwd.empty());
-assert(!hostCwd.empty());
-
// Construct the absolute path given the current working directory for
// either the host filesystem or target filesystem. The distinction
only
// matters if filesystem redirection is utilized in the simulation.
-auto path_base = host_filesystem ? hostCwd : tgtCwd;
+auto path_base = std::string();
+if (host_filesystem) {
+path_base = hostCwd;
+assert(!hostCwd.empty());
+} else {
+path_base = tgtCwd;
+assert(!tgtCwd.empty());
+}
// Add a trailing '/' if the current working directory did not have
one.
normalize(path_base);
--
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Gerrit-Change-Id: I4ab644a3e00737dbf249f5d6faf20a26ceb04248
Gerrit-Change-Number: 18448
Gerrit-PatchSet: 1
Gerrit-Owner: Brandon Potter
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: sim-se: create Proc out files in out dir
Brandon Potter has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/12122 )
Change subject: sim-se: create Proc out files in out dir
..
sim-se: create Proc out files in out dir
Redirected output files from Process objects were being
created in the current directory instead of in the
output directory.
Change-Id: Ieb6ab5556fbcc811f4f24910da247d4dcdbc71bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12122
Reviewed-by: Brandon Potter
Maintainer: Brandon Potter
Tested-by: kokoro
---
M src/sim/fd_array.cc
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
Brandon Potter: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/fd_array.cc b/src/sim/fd_array.cc
index 0600e9f..3b0c587 100644
--- a/src/sim/fd_array.cc
+++ b/src/sim/fd_array.cc
@@ -43,6 +43,7 @@
#include
#include "base/logging.hh"
+#include "base/output.hh"
#include "params/Process.hh"
#include "sim/fd_entry.hh"
@@ -311,7 +312,8 @@
int
FDArray::openOutputFile(std::string const& filename) const
{
-return openFile(filename, O_WRONLY | O_CREAT | O_TRUNC, 0664);
+return openFile(simout.resolve(filename),
+O_WRONLY | O_CREAT | O_TRUNC, 0664);
}
std::shared_ptr
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ieb6ab5556fbcc811f4f24910da247d4dcdbc71bd
Gerrit-Change-Number: 12122
Gerrit-PatchSet: 24
Gerrit-Owner: Brandon Potter
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Faults DebugFlag now printing inst opcode if available
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18396 )
Change subject: arch-arm: Faults DebugFlag now printing inst opcode if
available
..
arch-arm: Faults DebugFlag now printing inst opcode if available
This makes it easier to debug unimplemented instructions.
Change-Id: Iaaa288037326722f07251299fd68eacb2e295376
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396
Maintainer: Andreas Sandberg
Reviewed-by: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 29 insertions(+), 12 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 9cd068f..9437471 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -496,10 +496,7 @@
// if we have a valid instruction then use it to annotate this fault
with
// extra information. This is used to generate the correct fault
syndrome
// information
-if (inst) {
-ArmStaticInst *armInst = static_cast(inst.get());
-armInst->annotateFault(this);
-}
+ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
// Ensure Secure state if initially in Monitor mode
if (have_security && saved_cpsr.mode == MODE_MON) {
@@ -587,8 +584,10 @@
}
Addr newPc = getVector(tc);
-DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x
newVec: %#x\n",
-name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
+DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
+"%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
+newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
+std::string());
PCState pc(newPc);
pc.thumb(cpsr.t);
pc.nextThumb(pc.thumb());
@@ -673,26 +672,40 @@
cpsr.ss = 0;
tc->setMiscReg(MISCREG_CPSR, cpsr);
+// If we have a valid instruction then use it to annotate this fault
with
+// extra information. This is used to generate the correct fault
syndrome
+// information
+ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
+
// Set PC to start of exception handler
Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x
PC:%#x "
-"elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr,
new_pc);
+"elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
+new_pc, arm_inst ? csprintf("inst: %#x",
arm_inst->encoding()) :
+std::string());
PCState pc(new_pc);
pc.aarch64(!cpsr.width);
pc.nextAArch64(!cpsr.width);
pc.illegalExec(false);
tc->pcState(pc);
-// If we have a valid instruction then use it to annotate this fault
with
-// extra information. This is used to generate the correct fault
syndrome
-// information
-if (inst)
-static_cast(inst.get())->annotateFault(this);
// Save exception syndrome
if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
setSyndrome(tc, getSyndromeReg64());
}
+ArmStaticInst *
+ArmFault::instrAnnotate(const StaticInstPtr )
+{
+if (inst) {
+auto arm_inst = static_cast(inst.get());
+arm_inst->annotateFault(this);
+return arm_inst;
+} else {
+return nullptr;
+}
+}
+
Addr
Reset::getVector(ThreadContext *tc)
{
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 859fd34..e04a0dc 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -60,6 +60,8 @@
{
typedef Addr FaultOffset;
+class ArmStaticInst;
+
class ArmFault : public FaultBase
{
protected:
@@ -212,6 +214,8 @@
void invoke64(ThreadContext *tc, const StaticInstPtr =
StaticInst::nullStaticInstPtr);
void update(ThreadContext *tc);
+
+ArmStaticInst *instrAnnotate(const StaticInstPtr );
virtual void annotate(AnnotationIDs id, uint64_t val) {}
virtual FaultStat& countStat() = 0;
virtual FaultOffset offset(ThreadContext *tc) = 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iaaa288037326722f07251299fd68eacb2e295376
Gerrit-Change-Number: 18396
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Report real instruction encoding when Undefined
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18395 )
Change subject: arch-arm: Report real instruction encoding when Undefined
..
arch-arm: Report real instruction encoding when Undefined
When dumping the opcode that caused an Undefined Instruction, we just
want to dump the real instruction encoding, and not the extended version
with metabits (like thumb, bigThumb etc). This was not appening when
panicking in SE mode.
The patch is also replacing custom masking in the Unknown(64) disassembler
in favour of ArmStaticInstruction::encoding() helper.
Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de
Signed-off-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/faults.cc
M src/arch/arm/insts/misc.cc
M src/arch/arm/insts/misc64.cc
3 files changed, 6 insertions(+), 5 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 665b298..9cd068f 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -749,15 +749,16 @@
// If the mnemonic isn't defined this has to be an unknown instruction.
assert(unknown || mnemonic != NULL);
+auto arm_inst = static_cast(inst.get());
if (disabled) {
panic("Attempted to execute disabled instruction "
-"'%s' (inst 0x%08x)", mnemonic, machInst);
+"'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
} else if (unknown) {
panic("Attempted to execute unknown instruction (inst 0x%08x)",
- machInst);
+ arm_inst->encoding());
} else {
panic("Attempted to execute unimplemented instruction "
-"'%s' (inst 0x%08x)", mnemonic, machInst);
+"'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding());
}
}
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 3f29865..8efb81a 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -324,7 +324,7 @@
std::string
UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
-return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
+return csprintf("%-10s (inst %#08x)", "unknown", encoding());
}
McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst
_machInst,
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 7df2f76..c219bd9 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -78,7 +78,7 @@
std::string
UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
-return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
+return csprintf("%-10s (inst %#08x)", "unknown", encoding());
}
Fault
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de
Gerrit-Change-Number: 18395
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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