[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Enable set size increase
Hello kokoro, Tiago Mück, Bradford Beckmann, Anthony Gutierrez, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18968 to look at the new patch set (#3). Change subject: mem-ruby: Enable set size increase .. mem-ruby: Enable set size increase Add NUMBER_BITS_PER_SET environment variable to control the size of the bitmask in Set.hh (default=64). Necessary for configs which require >64 instances of a given machine type. This can be set in the build_opts file, e.g. by adding the following line: NUMBER_BITS_PER_SET = Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88 --- M SConstruct M src/mem/ruby/common/SConscript M src/mem/ruby/common/Set.hh 3 files changed, 20 insertions(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88 Gerrit-Change-Number: 18968 Gerrit-PatchSet: 3 Gerrit-Owner: John Alsop Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: John Alsop Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-CC: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13521 )
Change subject: arch-arm: Add initial support for SVE gather/scatter
loads/stores
..
arch-arm: Add initial support for SVE gather/scatter loads/stores
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
A src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
7 files changed, 1,403 insertions(+), 100 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/sve_macromem.hh
b/src/arch/arm/insts/sve_macromem.hh
new file mode 100644
index 000..a31af9b
--- /dev/null
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#ifndef __ARCH_ARM_SVE_MACROMEM_HH__
+#define __ARCH_ARM_SVE_MACROMEM_HH__
+
+#include "arch/arm/generated/decoder.hh"
+#include "arch/arm/insts/pred_inst.hh"
+
+namespace ArmISA {
+
+template class MicroopType>
+class SveIndexedMemVI : public PredMacroOp
+{
+ protected:
+IntRegIndex dest;
+IntRegIndex gp;
+IntRegIndex base;
+uint64_t imm;
+
+ public:
+SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass
__opClass,
+IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+uint64_t _imm)
+: PredMacroOp(mnem, machInst, __opClass),
+ dest(_dest), gp(_gp), base(_base), imm(_imm)
+{
+bool isLoad = (__opClass == MemReadOp);
+
+int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
+
+numMicroops = num_elems;
+if (isLoad) {
+numMicroops++;
+}
+
+microOps = new StaticInstPtr[numMicroops];
+
+StaticInstPtr *uop = microOps;
+
+if (isLoad) {
+// The first microop of a gather load copies the source vector
+// register used for address calculation to an auxiliary
register,
+// with all subsequent microops reading from the latter. This
is
+// needed to properly handle cases where the source vector
+// register is the same as the destination register
+*uop = new ArmISAInst::SveGatherLoadCpySrcVecMicroop(
+mnem, machInst, _base, this);
+uop++;
+}
+
+for (int i = 0; i < num_elem
[gem5-dev] Change in gem5/gem5[master]: cpu: Fix rescheduling of progress check events
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18793 )
Change subject: cpu: Fix rescheduling of progress check events
..
cpu: Fix rescheduling of progress check events
noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout
may be triggered even though packets are being eventually sent.
noResponseEvent scheduling is also fixed. This timeout should not be
active when we are not expecting a response.
Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Signed-off-by: Tiago Muck
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18793
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/cpu/testers/memtest/memtest.cc
1 file changed, 12 insertions(+), 4 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/testers/memtest/memtest.cc
b/src/cpu/testers/memtest/memtest.cc
index 93a6ac6..742cf3b 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -120,7 +120,6 @@
// kick things into action
schedule(tickEvent, curTick());
schedule(noRequestEvent, clockEdge(progressCheck));
-schedule(noResponseEvent, clockEdge(progressCheck));
}
Port &
@@ -189,8 +188,12 @@
// the packet will delete the data
delete pkt;
-// finally shift the response timeout forward
-reschedule(noResponseEvent, clockEdge(progressCheck), true);
+// finally shift the response timeout forward if we are still
+// expecting responses; deschedule it otherwise
+if (outstandingAddrs.size() != 0)
+reschedule(noResponseEvent, clockEdge(progressCheck));
+else if (noResponseEvent.scheduled())
+deschedule(noResponseEvent);
}
void
@@ -303,6 +306,10 @@
} else {
DPRINTF(MemTest, "Waiting for retry\n");
}
+
+// Schedule noResponseEvent now if we are expecting a response
+if (!noResponseEvent.scheduled() && (outstandingAddrs.size() != 0))
+schedule(noResponseEvent, clockEdge(progressCheck));
}
void
@@ -327,6 +334,7 @@
retryPkt = nullptr;
// kick things into action again
schedule(tickEvent, clockEdge(interval));
+reschedule(noRequestEvent, clockEdge(progressCheck), true);
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Gerrit-Change-Number: 18793
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch: Add include guards to auto-gen. decode header
Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18911 )
Change subject: arch: Add include guards to auto-gen. decode header
..
arch: Add include guards to auto-gen. decode header
Change-Id: I03bfc9035b82bc1a42e799cf645d43cb5dafb4cb
Signed-off-by: Giacomo Gabrielli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18911
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/isa_parser.py
1 file changed, 6 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 48bc23f..7f09b16 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014, 2016, 2019 ARM Limited
+# Copyright (c) 2014, 2016, 2018-2019 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -1652,6 +1652,9 @@
# decoder header - everything depends on this
file = 'decoder.hh'
with self.open(file) as f:
+f.write('#ifndef __ARCH_%(isa)s_GENERATED_DECODER_HH__\n'
+'#define __ARCH_%(isa)s_GENERATED_DECODER_HH__\n\n' %
+{'isa': self.isa_name.upper()})
fn = 'decoder-g.hh.inc'
assert(fn in self.files)
f.write('#include "%s"\n' % fn)
@@ -1660,6 +1663,8 @@
assert(fn in self.files)
f.write('namespace %s {\n#include "%s"\n}\n'
% (self.namespace, fn))
+f.write('\n#endif // __ARCH_%s_GENERATED_DECODER_HH__\n' %
+self.isa_name.upper())
# decoder method - cannot be split
file = 'decoder.cc'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I03bfc9035b82bc1a42e799cf645d43cb5dafb4cb
Gerrit-Change-Number: 18911
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Gabrielli
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add support for pinned writes
Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13520 )
Change subject: cpu-o3: Add support for pinned writes
..
cpu-o3: Add support for pinned writes
This patch adds support for pinning registers for a certain number of
consecutive writes. This is only relevant for timing CPU models
(functional-only models are unaffected), and it is primarily needed to
provide a realistic execution model for micro-coded operations whose
microops can write to non-overlapping portions of a destination
register, e.g. vector gather loads. In those cases, this mechanism
can disable renaming for a sequence of consecutive writes, thus making
the resulting execution more efficient: allocating a new physical
register for each microop would introduce a read-modify-write chain of
dependencies, while with these modifications the microops can write
back in parallel.
Please note that this new feature is only leveraged by O3CPU for the
time being.
Additional authors:
- Gabor Dozsa
Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81
Signed-off-by: Giacomo Gabrielli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13520
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/reg_class.hh
10 files changed, 183 insertions(+), 45 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 22a32ec..6f9555a 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, 2013, 2016-2018 ARM Limited
+ * Copyright (c) 2011, 2013, 2016-2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -116,6 +116,9 @@
SquashedInIQ,/// Instruction is squashed in the IQ
SquashedInLSQ, /// Instruction is squashed in the LSQ
SquashedInROB, /// Instruction is squashed in the ROB
+PinnedRegsRenamed, /// Pinned registers are renamed
+PinnedRegsWritten, /// Pinned registers are written back
+PinnedRegsSquashDone,/// Regs pinning status updated after
squash
RecoverInst, /// Is a recover instruction
BlockingInst,/// Is a blocking instruction
ThreadsyncWait, /// Is a thread synchronization
instruction
@@ -173,12 +176,14 @@
/** PC state for this instruction. */
TheISA::PCState pc;
+ private:
/* An amalgamation of a lot of boolean values into one */
std::bitset instFlags;
/** The status of this BaseDynInst. Several bits can be set. */
std::bitset status;
+ protected:
/** Whether or not the source register is ready.
* @todo: Not sure this should be here vs the derived class.
*/
@@ -385,6 +390,8 @@
{
_destRegIdx[idx] = renamed_dest;
_prevDestRegIdx[idx] = previous_rename;
+if (renamed_dest->isPinned())
+setPinnedRegsRenamed();
}
/** Renames a source logical register to the physical register which
@@ -767,7 +774,7 @@
bool isCommitted() const { return status[Committed]; }
/** Sets this instruction as squashed. */
-void setSquashed() { status.set(Squashed); }
+void setSquashed();
/** Returns whether or not this instruction is squashed. */
bool isSquashed() const { return status[Squashed]; }
@@ -802,7 +809,7 @@
bool isInLSQ() const { return status[LsqEntry]; }
/** Sets this instruction as squashed in the LSQ. */
-void setSquashedInLSQ() { status.set(SquashedInLSQ);}
+void setSquashedInLSQ() { status.set(SquashedInLSQ);
status.set(Squashed);}
/** Returns whether or not this instruction is squashed in the LSQ. */
bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
@@ -825,6 +832,41 @@
/** Returns whether or not this instruction is squashed in the ROB. */
bool isSquashedInROB() const { return status[SquashedInROB]; }
+/** Returns whether pinned registers are renamed */
+bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
+
+/** Sets the destination registers as renamed */
+void
+setPinnedRegsRenamed()
+{
+assert(!status[PinnedRegsSquashDone]);
+assert(!status[PinnedRegsWritten]);
+status.set(PinnedRegsRenamed);
+}
+
+/** Returns whether destination registers are written */
+bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
+
+/** Sets destination regis
[gem5-dev] Change in gem5/gem5[master]: dev-arm: Implement a SMMUv3 model
Hello Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19008 to look at the new patch set (#2). Change subject: dev-arm: Implement a SMMUv3 model .. dev-arm: Implement a SMMUv3 model This is an implementation of the SMMUv3 architecture. What can it do? - Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add. - Large pages are supported. - Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId What it can't do? - Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported - Invalidations take zero time. This wouldn't be hard to fix. - Checkpointing is not supported - Stall/resume for faulting transactions is not supported Additional contributors: - Michiel W. van Tol - Giacomo Travaglini Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg --- M src/dev/arm/SConscript A src/dev/arm/SMMUv3.py A src/dev/arm/amba.hh A src/dev/arm/smmu_v3.cc A src/dev/arm/smmu_v3.hh A src/dev/arm/smmu_v3_caches.cc A src/dev/arm/smmu_v3_caches.hh A src/dev/arm/smmu_v3_cmdexec.cc A src/dev/arm/smmu_v3_cmdexec.hh A src/dev/arm/smmu_v3_defs.hh A src/dev/arm/smmu_v3_events.cc A src/dev/arm/smmu_v3_events.hh A src/dev/arm/smmu_v3_ports.cc A src/dev/arm/smmu_v3_ports.hh A src/dev/arm/smmu_v3_proc.cc A src/dev/arm/smmu_v3_proc.hh A src/dev/arm/smmu_v3_ptops.cc A src/dev/arm/smmu_v3_ptops.hh A src/dev/arm/smmu_v3_slaveifc.cc A src/dev/arm/smmu_v3_slaveifc.hh A src/dev/arm/smmu_v3_transl.cc A src/dev/arm/smmu_v3_transl.hh 22 files changed, 6,571 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19008 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564 Gerrit-Change-Number: 19008 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem: Remove the now unused Copy* methods from the FS port proxy.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18576 )
Change subject: mem: Remove the now unused Copy* methods from the FS port
proxy.
..
mem: Remove the now unused Copy* methods from the FS port proxy.
Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18576
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Brandon Potter
Reviewed-by: Andreas Sandberg
Maintainer: Jason Lowe-Power
---
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
2 files changed, 0 insertions(+), 49 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
Brandon Potter: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/fs_translating_port_proxy.cc
b/src/mem/fs_translating_port_proxy.cc
index 2e17cbf..6a25d11 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -119,47 +119,3 @@
}
return true;
}
-
-void
-CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
-{
-uint8_t *dst = (uint8_t *)dest;
-tc->getVirtProxy().readBlob(src, dst, cplen);
-}
-
-void
-CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t cplen)
-{
-uint8_t *src = (uint8_t *)source;
-tc->getVirtProxy().writeBlob(dest, src, cplen);
-}
-
-void
-CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
-{
-char *start = dst;
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
-
-bool foundNull = false;
-while ((dst - start + 1) < maxlen && !foundNull) {
-vp.readBlob(vaddr++, (uint8_t*)dst, 1);
-if (*dst == '\0')
-foundNull = true;
-dst++;
-}
-
-if (!foundNull)
-*dst = '\0';
-}
-
-void
-CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr)
-{
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
-for (ChunkGenerator gen(vaddr, strlen(src),
TheISA::PageBytes); !gen.done();
- gen.next())
-{
-vp.writeBlob(gen.addr(), (uint8_t*)src, gen.size());
-src += gen.size();
-}
-}
diff --git a/src/mem/fs_translating_port_proxy.hh
b/src/mem/fs_translating_port_proxy.hh
index 78adf1a..410eb7d 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -97,9 +97,4 @@
bool tryMemsetBlob(Addr address, uint8_t v, int size) const override;
};
-void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
-void CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t
cplen);
-void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t
maxlen);
-void CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr);
-
#endif //__MEM_FS_TRANSLATING_PORT_PROXY_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6
Gerrit-Change-Number: 18576
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: kern: Replace an explicitly instantiated port proxy with one from the...
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18578 )
Change subject: kern: Replace an explicitly instantiated port proxy with
one from the tc.
..
kern: Replace an explicitly instantiated port proxy with one from the tc.
That avoids having to know what type of proxy to create.
Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18578
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Brandon Potter
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/kern/linux/helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc
index ed58427..e514ef8 100644
--- a/src/kern/linux/helpers.cc
+++ b/src/kern/linux/helpers.cc
@@ -94,7 +94,7 @@
{
System *system = tc->getSystemPtr();
const SymbolTable *symtab = system->kernelSymtab;
-FSTranslatingPortProxy proxy(tc);
+PortProxy &proxy = tc->getVirtProxy();
Addr addr_lb = 0, addr_lb_len = 0, addr_first = 0, addr_next = 0;
const bool found_symbols =
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a
Gerrit-Change-Number: 18578
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
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[gem5-dev] Change in gem5/gem5[master]: cpu: Store the translating proxy with the same pointer in SE or FS mode.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18580 )
Change subject: cpu: Store the translating proxy with the same pointer in
SE or FS mode.
..
cpu: Store the translating proxy with the same pointer in SE or FS mode.
Only one is active at a time, so they can share the same pointer.
Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18580
Tested-by: kokoro
Maintainer: Gabe Black
Reviewed-by: Brandon Potter
---
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
2 files changed, 9 insertions(+), 12 deletions(-)
Approvals:
Brandon Potter: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index c9fc564..3396c75 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -49,7 +49,7 @@
_contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
kernelStats(NULL), process(_process), physProxy(NULL),
virtProxy(NULL),
- proxy(NULL), funcExeInst(0), storeCondFailures(0)
+ funcExeInst(0), storeCondFailures(0)
{
}
@@ -59,8 +59,6 @@
delete physProxy;
if (virtProxy != NULL)
delete virtProxy;
-if (proxy != NULL)
-delete proxy;
}
void
@@ -118,8 +116,8 @@
assert(virtProxy == NULL);
virtProxy = new FSTranslatingPortProxy(tc);
} else {
-assert(proxy == NULL);
-proxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
+assert(virtProxy == NULL);
+virtProxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
process,
SETranslatingPortProxy::NextPage);
}
@@ -145,8 +143,8 @@
ThreadState::getMemProxy()
{
assert(!FullSystem);
-assert(proxy != NULL);
-return *proxy;
+assert(virtProxy != NULL);
+return *virtProxy;
}
void
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index e00c86f..db4a3f4 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -115,9 +115,9 @@
* the se translating port proxy needs to be reinitialized since it
* holds a pointer to the process class.
*/
-if (proxy) {
-delete proxy;
-proxy = NULL;
+if (virtProxy) {
+delete virtProxy;
+virtProxy = NULL;
initMemProxies(NULL);
}
}
@@ -197,8 +197,7 @@
/** A translating port proxy, outgoing only, for functional
* accesse to virtual addresses. */
-FSTranslatingPortProxy *virtProxy;
-SETranslatingPortProxy *proxy;
+PortProxy *virtProxy;
public:
/*
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da
Gerrit-Change-Number: 18580
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: cpu, sim: Return PortProxy &s from all the proxy accessors.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18579 )
Change subject: cpu, sim: Return PortProxy &s from all the proxy accessors.
..
cpu, sim: Return PortProxy &s from all the proxy accessors.
This is a step towards merging the accessors for SE and FS modes.
Change-Id: I76818ab88b97097ac363e243be9cc1911b283090
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18579
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Brandon Potter
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/sim/process.cc
8 files changed, 19 insertions(+), 20 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index ed8add6..46ade24 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -146,7 +146,7 @@
PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
-FSTranslatingPortProxy &
+PortProxy &
getVirtProxy() override
{
return actualTC->getVirtProxy();
@@ -164,7 +164,7 @@
actualTC->connectMemPorts(tc);
}
-SETranslatingPortProxy &
+PortProxy &
getMemProxy() override
{
return actualTC->getMemProxy();
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e5f0187..a3698cf 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -132,7 +132,7 @@
PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
-FSTranslatingPortProxy &getVirtProxy() override;
+PortProxy &getVirtProxy() override;
void
initMemProxies(ThreadContext *tc) override
@@ -140,7 +140,7 @@
thread->initMemProxies(tc);
}
-SETranslatingPortProxy &
+PortProxy &
getMemProxy() override
{
return thread->getMemProxy();
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index 58dee98..e05721b 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -54,7 +54,7 @@
#include "debug/O3CPU.hh"
template
-FSTranslatingPortProxy&
+PortProxy&
O3ThreadContext::getVirtProxy()
{
return thread->getVirtProxy();
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8b5e49a..991c6bd 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -216,18 +216,14 @@
}
PortProxy &getPhysProxy() override { return
ThreadState::getPhysProxy(); }
-FSTranslatingPortProxy &
-getVirtProxy() override
-{
-return ThreadState::getVirtProxy();
-}
+PortProxy &getVirtProxy() override { return
ThreadState::getVirtProxy(); }
void initMemProxies(ThreadContext *tc) override
{
ThreadState::initMemProxies(tc);
}
-SETranslatingPortProxy &
+PortProxy &
getMemProxy() override
{
return ThreadState::getMemProxy();
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index bdf5a00..f8b69d0 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -65,8 +65,6 @@
class CheckerCPU;
class Checkpoint;
class EndQuiesceEvent;
-class SETranslatingPortProxy;
-class FSTranslatingPortProxy;
class PortProxy;
class Process;
class System;
@@ -152,7 +150,7 @@
virtual PortProxy &getPhysProxy() = 0;
-virtual FSTranslatingPortProxy &getVirtProxy() = 0;
+virtual PortProxy &getVirtProxy() = 0;
/**
* Initialise the physical and virtual port proxies and tie them to
@@ -162,7 +160,7 @@
*/
virtual void initMemProxies(ThreadContext *tc) = 0;
-virtual SETranslatingPortProxy &getMemProxy() = 0;
+virtual PortProxy &getMemProxy() = 0;
virtual Process *getProcessPtr() = 0;
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index acb2971..c9fc564 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -133,7 +133,7 @@
return *physProxy;
}
-FSTranslatingPortProxy &
+PortProxy &
ThreadState::getVirtProxy()
{
assert(FullSystem);
@@ -141,7 +141,7 @@
return *virtProxy;
}
-SETranslatingPortProxy &
+PortProxy &
ThreadState::getMemProxy()
{
assert(!FullSystem);
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 2006339..e00c86f 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -47,6 +47,9 @@
class Checkpoint;
+class FSTranslatingPortProxy;
+class SETranslatingPortProxy;
+
/**
* Struct fo
gem5-dev@gem5.org
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18577 )
Change subject: arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to
PortProxy &s.
..
arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.
Al(most) all of the interesting differences between the two classes
have been removed. There are some control methods which are still
specific to each type which may require treating them as their true
type, but most code that consumes them doesn't need to worry about
which is which.
Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Brandon Potter
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/alpha/linux/system.cc
M src/arch/alpha/stacktrace.cc
M src/arch/alpha/utility.cc
M src/arch/arm/stacktrace.cc
M src/arch/arm/utility.cc
M src/arch/mips/stacktrace.cc
M src/arch/sparc/utility.cc
M src/arch/x86/linux/process.cc
M src/arch/x86/pseudo_inst.cc
M src/arch/x86/stacktrace.cc
M src/base/remote_gdb.cc
M src/sim/process_impl.hh
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/syscall_emul_buf.hh
M src/sim/vptr.hh
16 files changed, 38 insertions(+), 37 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index d963d29..ae9e5ef 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -176,7 +176,7 @@
if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
Tick cpuFreq = tc->getCpuPtr()->frequency();
assert(intrFreq);
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
vp.write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988),
GuestByteOrder);
}
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index f5833b0..bf2d5b3 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -49,7 +49,7 @@
: tc(_tc)
{
Addr addr = 0;
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
if (!symtab->findAddress("thread_info_size", addr))
@@ -82,7 +82,7 @@
Addr tsk;
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
tsk = vp.read(base + task_off, GuestByteOrder);
return tsk;
@@ -97,7 +97,7 @@
uint16_t pd;
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
pd = vp.read(task + pid_off, GuestByteOrder);
return pd;
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index c644911..8264c94 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -53,7 +53,7 @@
return tc->readIntReg(16 + number);
} else {
Addr sp = tc->readIntReg(StackPointerReg);
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
uint64_t arg = vp.read(sp +
(number-NumArgumentRegs) *
sizeof(uint64_t));
diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index 837b6ad..8fadb81 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -47,7 +47,7 @@
static int32_t
readSymbol(ThreadContext *tc, const std::string name)
{
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
Addr addr;
@@ -75,7 +75,7 @@
Addr tsk;
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
tsk = vp.read(base + task_off, GuestByteOrder);
return tsk;
@@ -90,7 +90,7 @@
uint16_t pd;
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
pd = vp.read(task + pid_off, GuestByteOrder);
return pd;
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 2888ebb..2f7d916 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -107,7 +107,7 @@
}
} else {
Addr sp = tc->readIntReg(StackPointerReg);
-FSTranslatingPortProxy &vp = tc->getVirtProxy();
+PortProxy &vp = tc->getVirtProxy();
uint64_t arg;
if (size == sizeof(uint64_t)) {
// If the argument is even it must be aligned
diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
[gem5-dev] Change in gem5/gem5[master]: arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18581 )
Change subject: arch, base, cpu, gpu, sim: Merge getMemProxy and
getVirtProxy.
..
arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.
These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.
Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Andreas Sandberg
---
M src/arch/alpha/linux/process.cc
M src/arch/arm/freebsd/process.cc
M src/arch/arm/linux/process.cc
M src/arch/mips/linux/process.cc
M src/arch/power/linux/process.cc
M src/arch/riscv/linux/process.cc
M src/arch/sparc/linux/syscalls.cc
M src/arch/sparc/process.cc
M src/arch/sparc/solaris/process.cc
M src/arch/x86/linux/process.cc
M src/arch/x86/pseudo_inst.cc
M src/base/remote_gdb.cc
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/gpu-compute/cl_driver.cc
M src/sim/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
22 files changed, 178 insertions(+), 213 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/linux/process.cc
b/src/arch/alpha/linux/process.cc
index d342c5d..f129b26 100644
--- a/src/arch/alpha/linux/process.cc
+++ b/src/arch/alpha/linux/process.cc
@@ -89,7 +89,7 @@
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
-name.copyOut(tc->getMemProxy());
+name.copyOut(tc->getVirtProxy());
return 0;
}
@@ -111,7 +111,7 @@
TypedBufferArg fpcr(bufPtr);
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
- fpcr.copyOut(tc->getMemProxy());
+ fpcr.copyOut(tc->getVirtProxy());
return 0;
}
@@ -139,7 +139,7 @@
case 14: { // SSI_IEEE_FP_CONTROL
TypedBufferArg fpcr(bufPtr);
// I don't think this exactly matches the HW FPCR
- fpcr.copyIn(tc->getMemProxy());
+ fpcr.copyIn(tc->getVirtProxy());
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
diff --git a/src/arch/arm/freebsd/process.cc
b/src/arch/arm/freebsd/process.cc
index 41549ea..69424c9 100644
--- a/src/arch/arm/freebsd/process.cc
+++ b/src/arch/arm/freebsd/process.cc
@@ -109,13 +109,13 @@
BufferArg buf3(oldlenp, sizeof(size_t));
BufferArg buf4(newp, sizeof(size_t));
-buf.copyIn(tc->getMemProxy());
-buf2.copyIn(tc->getMemProxy());
-buf3.copyIn(tc->getMemProxy());
+buf.copyIn(tc->getVirtProxy());
+buf2.copyIn(tc->getVirtProxy());
+buf3.copyIn(tc->getVirtProxy());
void *hnewp = NULL;
if (newp) {
-buf4.copyIn(tc->getMemProxy());
+buf4.copyIn(tc->getVirtProxy());
hnewp = (void *)buf4.bufferPtr();
}
@@ -125,11 +125,11 @@
ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen);
-buf.copyOut(tc->getMemProxy());
-buf2.copyOut(tc->getMemProxy());
-buf3.copyOut(tc->getMemProxy());
+buf.copyOut(tc->getVirtProxy());
+buf2.copyOut(tc->getVirtProxy());
+buf3.copyOut(tc->getVirtProxy());
if (newp)
-buf4.copyOut(tc->getMemProxy());
+buf4.copyOut(tc->getVirtProxy());
return (ret);
}
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 3fcb01f..426f66a 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -117,7 +117,7 @@
strcpy(name->version, "#1 SMP Sat Dec 1 00:00:00 GMT 2012");
strcpy(name->machine, "armv7l");
-name.copyOut(tc->getMemProxy());
+name.copyOut(tc->getVirtProxy());
return 0;
}
@@ -135,7 +135,7 @@
strcpy(name->version, "#1 SMP Sat Dec 1 00:00:00 GMT 2012");
strcpy(name->machine, "armv8l");
-name.copyOut(tc->getMemProxy());
+name.copyOut(tc->getVirtProxy());
return 0;
}
@@ -147,7 +147,7 @@
auto process = tc->getProcessPtr();
uint32_t tlsPtr = process->getSyscallArg(tc, index);
-tc->getMemProxy().writeBlob(ArmLinuxProcess32::commPage + 0x0ff0,
+tc->getVirtProxy().writeBlob(ArmLinuxProcess32::commPage + 0x0ff0,
&tlsPtr, sizeof(tlsPtr));
tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
return 0;
@@ -1737,8 +1737,8 @@
// Fill t
[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add support for pinned writes
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13520 to look at the new patch set (#8). Change subject: cpu-o3: Add support for pinned writes .. cpu-o3: Add support for pinned writes This patch adds support for pinning registers for a certain number of consecutive writes. This is only relevant for timing CPU models (functional-only models are unaffected), and it is primarily needed to provide a realistic execution model for micro-coded operations whose microops can write to non-overlapping portions of a destination register, e.g. vector gather loads. In those cases, this mechanism can disable renaming for a sequence of consecutive writes, thus making the resulting execution more efficient: allocating a new physical register for each microop would introduce a read-modify-write chain of dependencies, while with these modifications the microops can write back in parallel. Please note that this new feature is only leveraged by O3CPU for the time being. Additional authors: - Gabor Dozsa Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81 Signed-off-by: Giacomo Gabrielli --- M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/free_list.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/inst_queue_impl.hh M src/cpu/o3/regfile.cc M src/cpu/o3/regfile.hh M src/cpu/o3/rename_impl.hh M src/cpu/o3/rename_map.cc M src/cpu/reg_class.hh 10 files changed, 183 insertions(+), 45 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13520 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81 Gerrit-Change-Number: 13520 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: Andreas Sandberg Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: C
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Enable set size increase
Hello kokoro, Tiago Mück, Bradford Beckmann, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18968 to look at the new patch set (#2). Change subject: mem-ruby: Enable set size increase .. mem-ruby: Enable set size increase Add NUMBER_BITS_PER_SET environment variable to control the size of the bitmask in Set.hh (default=64). Necessary for configs which require >64 instances of a given machine type. This can be set in the build_opts file, e.g. by adding the following line: NUMBER_BITS_PER_SET = Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88 --- M SConstruct M src/mem/ruby/common/SConscript M src/mem/ruby/common/Set.hh 3 files changed, 20 insertions(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88 Gerrit-Change-Number: 18968 Gerrit-PatchSet: 2 Gerrit-Owner: John Alsop Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: John Alsop Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Ilias Vougioukas, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#12). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh 8 files changed, 2,191 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 12 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
